JPS61287348A - Scramble circuit - Google Patents

Abstract

PURPOSE:To enhance the secrecy of a data while facilitating the change in a scramble pattern by deciding the read timing of a memory written with the scramble pattern at an address set optionally externally corresponding to plural series of data. CONSTITUTION:The title circuit consists of a counter 17 for designating an address, a selection circuit selecting an address set optionally corresponding to plural series of data, an adder (subtractor) 16 adding or subtracting address outputs from both the circuits, a serial/parallel circuit 19 and a timing circuit 20. Since the address of the adder (subtractor) 16 is set optionally set, an optional scramble pattern is obtained easily from one series of scramble pattern written in a memory 18 by changing the said address. Other stations not recognizing the order of the change cannot intercept the data. In outputting the former pattern, the circuit 20 activates the conversion circuit 19 and the selection circuit 15 correspondingly.

Description

[Detailed Description of the Invention] [Summary] In a scrambling circuit, by determining the read timing of a memory in which a scrambling pattern is written at an address arbitrarily set from the outside corresponding to multiple columns of data, it is possible to The scrambling pattern can be easily changed and the confidentiality of this data is strengthened.

[Industrial application field]

The present invention relates to improvements in scrambling circuits used in data transmission.

For example, in order to increase frequency usage efficiency when transmitting data over wireless lines, multi-level quadrature amplitude modulation (hereinafter referred to as multi-level QA) is used.
(abbreviated as M method) may be used.

FIG. 5 shows a block diagram of an example of a multi-level QAM (eg, 16-level QAM) wireless device transmitter.

In the figure, four binary columns of data from a carrier terminal station (not shown) are sent to a transmitting side logic circuit (T-LOG) 1 .

2, the signals are scrambled by taking an exclusive OR with the scramble pattern, and then a frame pattern for a wireless line, a meeting signal, etc. added to.

On the other hand, since carrier waves generated by the carrier wave generator 5 and orthogonal to each other are also added here, this carrier wave is amplitude-modulated by the above analog signal, and then the hybrid circuit 6
are combined to obtain a 16-value QAM modulated wave.

Note that in the case of a 16-value QAM modulated wave, there are four columns of data, but in the case of a 256-value QAM modulated wave, there are eight columns, and as the multi-value value increases, the number of data strings to be input also increases.

These data are each scrambled using a scrambling pattern in order to suppress continuous zero signals, etc., but it is desired to make the spectrum distribution of the modulated wave corresponding to the scrambled data as flat as possible.

[Conventional technology]

FIG. 6 shows a block diagram of a conventional example of a scrambling circuit, and FIG. 7 shows a waveform diagram of FIG. 6.

Therefore, taking the case of the 16-level QAM modulation method as an example, the seventh
The operation shown in FIG. 6 will be explained with reference to FIG.

In Figure 6, read-only memory (RO
(abbreviated as M) 7 contains 'A-N' as shown in Figure 7.
Four scramble patterns (for example, pseudo-random patterns, hereinafter abbreviated as PN patterns) shifted bit by bit with a period N are written. .

Therefore, when the count value from the counter 8 is added to the ROM as an address, the PN pattern corresponding to this address is output in parallel, and this PN pattern and the data added from the outside are combined into an exclusive OR circuit (hereinafter referred to as EX -O
(abbreviated as R circuit) 9-1 to 9-4 perform EX-OR and scramble the data.

[Problem that the invention seeks to solve]

However, it has been experimentally found that if the amount of shift between the plurality of PN patterns is small, it affects the spectrum distribution of the modulated wave when the multilevel value becomes large.

In other words, in the case of a 16-level QAM modulated wave, even if the amount of shift is small, it does not affect the spectrum distribution much, but 2
In the case of a 56-level QAM modulated wave, this has a large effect, causing irregularities in the spectrum and deteriorating the error rate of demodulated data. This is thought to occur because the signal does not pass through all the signal points equally during modulation (that is, it does not occur at random), so in order to improve this problem, it is necessary to find an optimal PN pattern.

Therefore, we prepare multiple ROMs in which PN patterns with different shift amounts are written and exchange them to flatten the spectrum distribution of the modulated wave. There is a problem that it takes time to obtain a pattern.

[Means for solving problems]

The above problem, as shown in FIG. an adder or subtractor 16 for adding or subtracting address output;
a memory 18 that outputs the scramble pattern written by the address output of the memory 18, a serial/parallel conversion circuit 19 that converts the serial output of the memory 18 into parallel output, the selection circuit 15, and the serial/parallel conversion circuit. This problem is solved by the scrambling circuit of the present invention, which includes a timing circuit 20 that operates in a corresponding manner.

[Effect]

The present invention uses the counter 17 as the address of the memory 18.
Add (subtract) the specified address and the address you set arbitrarily.
The value added in calculator 16 was used.

That is, since the latter address can be set arbitrarily, any scramble pattern can be easily obtained from a series of scramble patterns written in the memory 18 by changing this address.

Therefore, by changing this setting value, the scrambling pattern can be easily changed.

Furthermore, since the scrambling pattern can be changed arbitrarily, other stations that do not know the order of the changes cannot intercept the data, thereby increasing the confidentiality of the data.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a block diagram of an embodiment of the present invention.
The time chart shown in the figure is shown.

Therefore, with reference to FIG. 3, the operation of FIG. 2 will be explained using the 16-level QAM modulation method as an example.

Note that the symbols on the left side of FIG. 3 indicate the time chart of the portions with the same symbols in FIG.

In Fig. 2, the input clock CLK is input to frequency divider circuit 1.
1, the frequency is divided by 2 and 4, and the selector 10. counter 1
2. It is added to the decoder 14-1 in the serial/parallel conversion circuit 14 (see FIG. 3 - CLK, a, b).

Therefore, the counter 12, which has the same period as the period of the PN pattern written in the ROM, measures this clock and adds the value to the full adder 13 (see FIG. 3-d).

Further, the selector 10 uses the 2-divided frequency wave and the 4-divided frequency wave added here to select a terminal corresponding to a binary number in which a is the 1's digit and b is the 2's digit.

That is, the values of a and b take the value O or 1 as shown in Figure 3-a and b, but the above binary number repeats the values from 0 to 3 at the timing shown in Figure 3-a. , one of the set values added to terminals ■～■ is output, and the full adder 13
It is added to the output of the counter 12 and added to the ROM 7 (see FIG. 3-c, d, and e).

For example, 0. ■2. ■3. If 5 is added to ■ and the output of counter 12 is 1, then 1°3.4.6
Since the address of ROM 7 is added to ROM 7, ROM 7
The corresponding bits are read from the respective bits.

Therefore, by repeating this, a pattern as shown in FIG. 3-f is extracted, but this pattern is generated by the decoder 14 which decodes the output of the frequency dividing circuit 11 and generates the timing shown in FIG. 3-g. -1 and flip-flop 14-2
In the serial/parallel conversion circuit 14 consisting of ~14-5, the data is converted into parallel patterns as shown in Figure 3-g, h-1 to h-4, and scrambled with the four columns of data as described above. .

FIG. 4 is a block diagram of another embodiment of the invention. still,
This figure differs from FIG. 2 only in the selector part, and the other parts are the same.

Since the values added to terminals ◎ to ■ are settings, these values can be easily changed, but in addition, separate selectors 15-0 to j5-3 are connected to these terminals ◎ to ■, respectively, as shown in Figure 3. If you select an arbitrary set value with this, you can change the set value widely in a shorter time.

Therefore, a PN pattern with a flat spectrum distribution can be easily obtained.

It is assumed that the pattern obtained by sampling the PN pattern written in the RO 47 is also a PN pattern.

〔Effect of the invention〕

As explained in detail above, since the address of the memory where the scramble pattern is written can be arbitrarily set, there is an effect that the scramble pattern can be easily changed.

Furthermore, since the scrambling pattern can be changed variously in a short period of time, there is also the effect that the confidentiality of data is improved.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is a time chart 1 of Fig. 1, and Fig. 4 is a block diagram of another embodiment of the invention. FIG. 5 is a block diagram of an example of a transmitting section of a multilevel QAM radio device. FIG. 6 is a block diagram of a conventional example. FIG. 7 is a waveform diagram of FIG. 6. In the figure, 7 is 170M, 10 is a selector, 11 is a frequency divider, 12 and 17 are counters, 13 is a full adder, 14 and 19 are serial/parallel conversion circuits, 15 is a selection circuit, and 16 is an adder (subtractor). , 18 is a memory, and 20 is a timing circuit. Book f: 4th arm, f ri bwa 7 fig. 1 fig.
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Claims (1)

[Claims] A data transmission device that scrambles multiple columns of data, comprising: a counter (17) for specifying an address; and a selection circuit (15) that selects an arbitrarily set address corresponding to the multiple columns of data. , an adder that adds or subtracts the address output from the counter and the selector (16), and a memory (16) that outputs a scramble pattern written by the address output of the adder or subtracter (16). 18), a serial/parallel conversion circuit (19) that converts the serial output of the memory (18) into parallel output, and a timing circuit that causes the selection circuit (15) and the serial/parallel conversion circuit to operate in correspondence. (20) A scrambling circuit comprising: