JPS61276218A - Pattern for measurement of superposing error - Google Patents

Pattern for measurement of superposing error

Info

Publication number
JPS61276218A
JPS61276218A JP60116604A JP11660485A JPS61276218A JP S61276218 A JPS61276218 A JP S61276218A JP 60116604 A JP60116604 A JP 60116604A JP 11660485 A JP11660485 A JP 11660485A JP S61276218 A JPS61276218 A JP S61276218A
Authority
JP
Japan
Prior art keywords
pattern
substrate
vernier
edges
observation device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60116604A
Other languages
Japanese (ja)
Inventor
Yasuo Takahashi
保夫 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60116604A priority Critical patent/JPS61276218A/en
Publication of JPS61276218A publication Critical patent/JPS61276218A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To dissolve the deviation of the focal surface of a pattern observation device and to obtain a high-measurement precision vernier by a method wherein a pattern to be used for measuring the superposing error between the first and second patterns in the lithography process is formed so that the observation positions of the first and second patterns coincide with each other on the same plane in the focal depth of the pattern observation device using the vernier. CONSTITUTION:The depth of the pattern of a substrate 103 is adjusted and the pattern observation device is constituted so that the edges (e) of the pattern of the substrate and the edges (f) of a resist pattern 11 coincide with a focusing surface FF being conformed to the upper surface of the substrate using the vernier. Moreover, in consideration of the film thickness of films 104 to be formed on the substrate, the edges (e) of the pattern of the substrate and the edges (g) of a resist pattern 12 can be brought onto the focusing surface FF being conformed to the upper surface of the substrate. When such the vernier is used, the deviation between the images, which is generated when the focal point is made to shift, is not generated because there is not need to deviate the focal point. As a result, the reliability of the measured value is improved.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は半導体素子の製造工程におけるリソグラフィ
工程におけるもので、特にパターンの重ね合わせ誤差の
測定に用いられる。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a lithography process in the manufacturing process of semiconductor devices, and is particularly used for measuring pattern overlay errors.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

従来、リングラフィ工程における露光で、マスクを重ね
合わす際の合わせずれはバーニアを用いて測定している
Conventionally, misalignment when overlapping masks during exposure in a phosphorography process has been measured using a vernier.

その手段は、任意の形状と任意のピッチのパターンを、
垂直な二方向において重ね合わせ、その重なり具合とピ
ッチにより合わせ誤差を測定するもので、主に観察者の
目視によって行なわれている。バーニアの例、および誤
差読み取り例を第6図に示す。図に実線で示すバーニア
パターン1010゜101A、 101B・・・、Io
ta、 101b=−はいずれも基板上に等間隔に形成
されたもので、この間隔は例えば0.1μmに設けられ
ている。また1合わせに用いられたマスクのバーニアパ
ターン1020.102A、 102B・・・、102
a、 102b・・・は図面に打点を施して示しである
The means is to create a pattern of any shape and any pitch,
The method involves overlapping in two perpendicular directions, and measuring the overlapping error based on the degree of overlapping and the pitch, and is mainly performed visually by an observer. An example of a vernier and an example of error reading are shown in FIG. Vernier patterns 1010°101A, 101B..., Io shown by solid lines in the figure
ta and 101b=- are both formed at equal intervals on the substrate, and this interval is set to, for example, 0.1 μm. Also, vernier patterns 1020, 102A, 102B..., 102 of the mask used for 1 alignment
a, 102b, . . . are indicated by dots in the drawing.

ところで1図に示すように、基板のバーニアパターンと
マスクのパターンとは101Cと102Gが一致してい
る。これらの前後の図に破線で囲む部分を拡大して第7
図に示す、すなわち、マスク合わせずれは1010から
3個目であるから+3μmであることが判明している。
By the way, as shown in FIG. 1, the vernier pattern of the substrate and the pattern of the mask match 101C and 102G. The parts surrounded by broken lines in the figures before and after these are enlarged and shown in Figure 7.
In other words, the mask misalignment shown in the figure is +3 μm since it is the third mask from 1010.

また、最近、微小線幅測定機等を使用した合わせ誤差測
定も行なわれている。これは第8図に示すように、Xp
”j方向に両パターン間の間隔を測定しX1+ X2y
 ylt y2を算出するものであり、あるいは第9図
に示すように基準線X、Yをきめ、各パターンに対しこ
れと平行な部分との間隔をa1〜a4.b□〜b4の如
く測定し誤差を算出する方法である。
In addition, alignment error measurement using a minute line width measuring device has recently been carried out. As shown in Figure 8, this
``Measure the distance between both patterns in the j direction, X1 + X2y
Alternatively, as shown in FIG. 9, the reference lines X and Y are determined, and the distance between the lines and the parallel parts for each pattern is set a1 to a4. This is a method of measuring as shown in b□ to b4 and calculating the error.

上記マスク合わせを行なうバーニアは、通常第10図な
いし第12図によって示す構造に形成される。すなわち
、第10図のパターン(a)は、この基板103の主面
103aにピントを合わせて観測すると図(b)に示す
ように、パターンの底部は破線で示すようにぼける。次
に、第11図に示すように、任意の膜104、例えば5
i02膜、多結晶シリコン膜、モリブデンシリサイド膜
等を被着し、さらに第12図に示すように、レジスト膜
を積層して塗着し、露光、現像を施してレジストパター
ン105を形成する。各回における図(a) ? (b
)の表示するところは第10図における表示に同じであ
る。次に第12図に示すものにおいて、測定時の焦点位
置を膜104の凹成にした場合に観測されるパターンは
第13図(a)に示され、ピントの合っている部分は太
線で示されている。また、図(a)におけるパターンの
A−A線に沿うコントラストの出力波形が図(b)に示
される。同様に、第12図(a)における基板のパター
ンの凹成に焦点位置に合わせた場合の観測パターンを第
14図に、また基板103の主面に焦点位置を合わせた
場合の観測パターンを第15図に、さらに、レジストパ
ターン105の上面に焦点位置を合わせた場合の観測パ
ターンを第16図に夫々上記と同様に示した。
The vernier for performing the mask alignment is usually formed in the structure shown in FIGS. 10 to 12. That is, when the pattern (a) in FIG. 10 is observed while focusing on the main surface 103a of the substrate 103, the bottom of the pattern becomes blurred as shown by the broken line as shown in FIG. 10(b). Next, as shown in FIG.
An i02 film, a polycrystalline silicon film, a molybdenum silicide film, etc. are deposited, and as shown in FIG. 12, a resist film is laminated and applied, and exposed and developed to form a resist pattern 105. Diagram (a) for each episode? (b
) is the same as the display in FIG. Next, in the case shown in FIG. 12, the pattern observed when the focal position during measurement is set to the concave portion of the film 104 is shown in FIG. has been done. Further, the output waveform of the contrast along the line A-A of the pattern in FIG. 3(a) is shown in FIG. 3(b). Similarly, FIG. 14 shows an observation pattern when the focus position is set on the concavity of the substrate pattern in FIG. 12(a), and FIG. FIG. 15 shows an observed pattern when the focus position is set on the upper surface of the resist pattern 105, and FIG. 16 shows the observed pattern in the same manner as above.

なお、バーニアを読みとる場合、通常焦点面を第12図
に示したc”d、c”a、a−bの中間にとるが、パタ
ーンによってはレジストのエツジの裾曳き、基板側エツ
ジが上層の膜によりかすれる等の問題がある。また、C
とdによる読取りは二つの焦点面位(高さ)の差が大き
くなる場合が多く、パターンのエツジがうまく出方でき
ない場合が多い。
When reading the vernier, the focal plane is usually set between c"d, c"a, and a-b shown in Fig. 12, but depending on the pattern, the edge of the resist may be traced, or the edge on the substrate side may be located between the edges of the upper layer. There are problems such as blurring due to the film. Also, C
In reading with and d, the difference between the two focal plane positions (heights) is often large, and the edges of the pattern often cannot be clearly seen.

上述により従来の重ね合わせ誤差測定用パターン(バー
ニア)を読みとる場合、次のような問題がある。
As described above, when reading the conventional overlay error measurement pattern (vernier), the following problems occur.

(1)各バーニアの高さが異なるため、高倍率では焦点
深度が浅いことから同時に両バーニアに焦点が合わない
6 (2)(1)により読取り誤差が生ずる。
(1) Since the height of each vernier is different, the depth of focus is shallow at high magnification, so both verniers are not in focus at the same time.6 (2) Reading errors occur due to (1).

(3) (1)により測定装置等を用いた場合、再現性
にばらつきが大きい。
(3) When a measuring device or the like is used according to (1), there is a large variation in reproducibility.

〔発明の目的〕[Purpose of the invention]

この発明は従来の問題点に鑑み、焦点面のずれを解消し
測定精度の高いバーニアになる重ね合わせ誤差測定用パ
ターンを提供する。
In view of the conventional problems, the present invention provides an overlay error measurement pattern that eliminates focal plane deviation and provides a vernier with high measurement accuracy.

〔発明の概要〕[Summary of the invention]

この発明にかかる重ね合わせ誤差測定用パターンは、半
導体基板上に形成された第1パターンとこれに重ね合わ
せる第2パターンの組合せを少くとも1組有するものに
おいて、第1パターンと第2パターンのfR察位置がパ
ターンa察装置の焦点深度内において同一平面上になる
ように加工されたことを特徴とする。
The overlay error measurement pattern according to the present invention has at least one combination of a first pattern formed on a semiconductor substrate and a second pattern overlaid thereon, wherein the fR of the first pattern and the second pattern is It is characterized in that the detection positions are processed to be on the same plane within the depth of focus of the pattern a detection device.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の実施例につき第1図ないし第5図を参
照して説明する。なお、説明において、従来と変わらな
い部分については図面に同じ符号をもって示し説明を省
略する。
Embodiments of the present invention will be described below with reference to FIGS. 1 to 5. In addition, in the description, parts that are the same as the conventional ones are indicated by the same reference numerals in the drawings, and the description thereof will be omitted.

第1図aは基板103のパターンの深さを調整して基板
パターンのエツジeとレジストパターン11のエツジf
を基板上面に合わせたフォーカス面FFにもってきた場
合を示し、図aは断面図、図すは観測されるパターン、
図Cは図すのA−A線に沿うコントラストの出力波形を
示す。
FIG. 1a shows the edge e of the substrate pattern and the edge f of the resist pattern 11 by adjusting the depth of the pattern on the substrate 103.
The figure shows the case where the image is brought to the focus plane FF which is aligned with the top surface of the substrate.
Figure C shows a contrast output waveform along line A--A in the figure.

次の第2図に示すものは基板上に形成する膜104の膜
厚を考慮し、基板パターンのエツジeとレジストパター
ン12のエツジgを基板上面に合わせたフォーカス面F
Fにもってきた場合を示し、図a、b、Qは上記第1図
にて示す夫々と同じものとする。
What is shown in FIG. 2 below is a focus plane F in which the edge e of the substrate pattern and the edge g of the resist pattern 12 are aligned with the top surface of the substrate, taking into account the thickness of the film 104 formed on the substrate.
Figures a, b, and Q are the same as those shown in Figure 1 above.

次の第3図に示すものは、基板パターンの膜104(図
p)上にレジスト膜23を塗着しく図り)。
In the case shown in FIG. 3, a resist film 23 is applied on a substrate pattern film 104 (FIG. 3).

これに現像もしくはエツチング等を施して例えば上面が
基板の上面位に一致するように調整された膜厚のレジス
ト膜33に形成しく図r)、この上に合せのレジストパ
ターン13を形成したものである。この場合、膜厚を調
整した上記レジスト膜33はレジストに限らない。そし
て、基板パターンのエツジeとレジストパターンのエツ
ジgを基板上面に合わせたフォーカス面FFにもってく
ることによって、図a、b、Q (上記第1図に同じ)
が得られる。
This is then developed or etched to form a resist film 33 having a thickness adjusted so that the top surface matches the top surface of the substrate (Fig. r), and a matching resist pattern 13 is formed on this. be. In this case, the resist film 33 whose thickness has been adjusted is not limited to a resist. Then, by bringing the edge e of the substrate pattern and the edge g of the resist pattern to the focus plane FF aligned with the top surface of the substrate, Figures a, b, and Q (same as in Figure 1 above)
is obtained.

さらに第4図に示すものは、基板パターンが重なり合わ
せないバーニアパターンを用いるようにした特徴を有し
、一方のパターンの底面にフォーカス面を設定し、他方
のパターンは膜114の上面にフォーカスさせる。そし
て上記一方のパターンのエツジeと、他方のパターンの
膜114上に形成されたレジストパターン14のエツジ
gとを同一フォーカス面にあわせる。図a、b、Qの夫
々が示すところは上記第1図における夫々と同じである
Furthermore, the device shown in FIG. 4 has a feature in which vernier patterns are used in which the substrate patterns do not overlap, and the focus plane is set on the bottom surface of one pattern, and the other pattern is focused on the top surface of the film 114. . Then, the edge e of one pattern and the edge g of the resist pattern 14 formed on the film 114 of the other pattern are aligned on the same focus plane. The parts shown in each of figures a, b, and Q are the same as those shown in FIG. 1 above.

次の第5図に示すものは、第4図に示し説明したものと
同様に、基板パターンに重なり合わせないバーニアパタ
ーンを用いるが、このパターンを深く形成してこの基板
パターンのエツジeをレジストパターンのエツジgと同
一フォーカス面にしている6また、図at be aの
夫々が示すところは上記第1図における夫々と同じであ
る。
The one shown in FIG. 5 below uses a vernier pattern that does not overlap the substrate pattern, similar to the one shown and explained in FIG. The focus plane is the same as the edge g of 6. Also, the points shown in each of the figures at be a are the same as those in FIG. 1 above.

〔発明の効果〕〔Effect of the invention〕

この発明によれば、従来のバーニアに比し読みやすく、
かつ読取り誤差少く、測定の再現性に優れるなど数々の
顕著な利点がある。また、測定装置を用いた場合の例を
コントラストプロファイルで第1図ないし第5図、第1
3図ないし第16図に示したが、これからもわかるよう
に、コントラストが大きく、かつ、他のエツジや表面の
材質により生ずるノイズに強いプロファイルが得られた
According to this invention, it is easier to read than conventional verniers,
It also has a number of notable advantages, such as low reading errors and excellent measurement reproducibility. In addition, examples of when using a measuring device are shown in contrast profiles in Figures 1 to 5 and Figure 1.
As shown in FIGS. 3 to 16, a profile with high contrast and strong resistance to noise caused by other edges and surface materials was obtained.

特に第4図および第5図によって説明した実施例はノイ
ズに対して有効である。これにより、測定値の再現性が
顕著に向上をみた。さらに、焦点をずらさないので、焦
点を移動させるときに発生する像のずれが発生せず、測
定値の信頼性が向上した。
In particular, the embodiment described with reference to FIGS. 4 and 5 is effective against noise. This significantly improved the reproducibility of measured values. Furthermore, since the focus is not shifted, the image shift that occurs when the focus is moved does not occur, and the reliability of the measured values is improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第5図はこの発明の実施例にかかり、各回
における図aは一部の断面図、図すは観測されるパター
ン、図Cはコントラストプロファイル図、第3図におけ
る図pないし図rは図aに示すものの形成に至る途中の
状態を示すいずれも断面図、第6図は従来の目視による
重ね合わせ誤差測定用バーニア図で、第7図は第6図の
破線で囲む部分を拡大して示すバーニア図、第8図と第
9図は従来の誤差測定方法を示す平面図、第10図ない
し第12図は従来の合わせバーニアの形成順序を示し各
回における図aは断面図、図すは観測されるパターン、
第13図ないし第16図はバーニアパターンの形成され
た表面のフォーカスを変えて示す観測パターンで各図に
おける図aはパターン、図すはコントラストプロファイ
ルを示す。 11、12.13.、14.15−−−−−レジストパ
ターン103−−−−一基板 104、114−−−−一部
Figures 1 to 5 relate to embodiments of the present invention, each time Figure a is a cross-sectional view of a part, Figure 3 is a pattern to be observed, Figure C is a contrast profile diagram, and Figures P to 3 in Figure 3. r is a cross-sectional view showing the state in the middle of forming what is shown in Figure a, Figure 6 is a vernier diagram for conventional visual overlay error measurement, and Figure 7 shows the part surrounded by the broken line in Figure 6. An enlarged view of the vernier, FIGS. 8 and 9 are plan views showing the conventional error measurement method, FIGS. 10 to 12 show the formation order of the conventional mating vernier, and each figure a is a cross-sectional view. The figure shows the observed pattern.
13 to 16 are observation patterns shown by changing the focus of the surface on which the vernier pattern is formed, and in each figure, figure a shows the pattern, and figure a shows the contrast profile. 11, 12.13. , 14.15---Resist pattern 103---One substrate 104, 114---Part

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に形成された第1パターンとこれに重ね合
わせる第2パターンの組合せを少くとも1組有する重ね
合わせ誤差測定用パターンにおいて、第1パターンと第
2パターンの観察位置がパターン観察装置の焦点深度内
において同一平面上になるように加工されたことを特徴
とする重ね合わせ誤差測定用パターン。
In an overlay error measurement pattern having at least one combination of a first pattern formed on a semiconductor substrate and a second pattern superimposed thereon, the observation positions of the first pattern and the second pattern are the focal point of the pattern observation device. A pattern for measuring overlay error characterized by being processed to be on the same plane within a depth.
JP60116604A 1985-05-31 1985-05-31 Pattern for measurement of superposing error Pending JPS61276218A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60116604A JPS61276218A (en) 1985-05-31 1985-05-31 Pattern for measurement of superposing error

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60116604A JPS61276218A (en) 1985-05-31 1985-05-31 Pattern for measurement of superposing error

Publications (1)

Publication Number Publication Date
JPS61276218A true JPS61276218A (en) 1986-12-06

Family

ID=14691271

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60116604A Pending JPS61276218A (en) 1985-05-31 1985-05-31 Pattern for measurement of superposing error

Country Status (1)

Country Link
JP (1) JPS61276218A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0355865A (en) * 1989-07-24 1991-03-11 Nec Corp Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0355865A (en) * 1989-07-24 1991-03-11 Nec Corp Manufacture of semiconductor device
JPH0770577B2 (en) * 1989-07-24 1995-07-31 日本電気株式会社 Method for manufacturing semiconductor device

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