JPS61274561A - Selective calling system for digital circuit - Google Patents
Selective calling system for digital circuitInfo
- Publication number
- JPS61274561A JPS61274561A JP60117126A JP11712685A JPS61274561A JP S61274561 A JPS61274561 A JP S61274561A JP 60117126 A JP60117126 A JP 60117126A JP 11712685 A JP11712685 A JP 11712685A JP S61274561 A JPS61274561 A JP S61274561A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- parallel
- serial
- setting switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野コ
本発明はディジタル回線用選択呼出し方式に関し、特に
ディジタル無線中継回線のPCM方式によるパーティラ
インの圧会ゼ電話を選択呼出しするディジタル回線用選
択呼出し方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a selective calling system for digital lines, and particularly to a selective calling system for digital lines that selectively calls party line telephones using the PCM system of digital radio relay lines. Regarding the method.
[従来の技術]
従来、この種の選択呼出しによる打合せ電話では、PC
M信号にエンコードする前のアナログ信号側およびPC
M信号からデコードした後のアナログ信号側でインバン
ドマルチトーンによる選択呼出し方式を使用していた。[Prior Art] Conventionally, in this type of selective call meeting telephone, the PC
Analog signal side and PC before encoding to M signal
An in-band multitone selective calling method was used on the analog signal side after decoding from the M signal.
[発明が解決しようとする問題点]
上述した従来の選択呼出し方式では、トーン発信回路お
よびトーン検出回路が必要となるので、回路が複雑にな
るば、かりでなく信頼性の低下および価格も高くなると
いう欠点がある。[Problems to be Solved by the Invention] The conventional selective calling method described above requires a tone generation circuit and a tone detection circuit, so if the circuit becomes complicated, the reliability will decrease and the cost will increase. It has the disadvantage of becoming.
[問題点を解決するための手段]
本発明のディジタル回線用選択呼出し方式は、送信側に
はPCMコーダ出力と呼出し設定スイッチの値をパラレ
ルシリアル変換するパラレルシリアル変換回路出力とを
切り替える切替回路を備え、受信側にはPCMデコーダ
と、伝送路からの受信信号をシリアルパラレル変換する
シリアルパラレル変換回路出力と自装置番号設定スイッ
チの値とを比較する比較回路と、該比較回路出力が一定
時間以上一致していることを検出する一定時間検出回路
と、該一定時間検出回路の検出結果を出力する出力回路
とを備えている。[Means for Solving the Problems] The selective calling system for digital lines of the present invention includes a switching circuit on the transmitting side that switches between the PCM coder output and the output of a parallel-to-serial conversion circuit that converts the value of the call setting switch from parallel to serial. The receiving side is equipped with a PCM decoder, a comparison circuit that compares the output of a serial-parallel conversion circuit that converts the received signal from the transmission line into serial-parallel and the value of the own device number setting switch, and a comparison circuit that compares the output of the comparison circuit for a certain period of time or more. It includes a fixed time detection circuit that detects a match, and an output circuit that outputs the detection result of the fixed time detection circuit.
[実施例] 次に、本発明について図面を参照して説明する。[Example] Next, the present invention will be explained with reference to the drawings.
第1図は本発明のディジタル回線用選択呼出し方式の一
実施例を示すブロック図である。FIG. 1 is a block diagram showing an embodiment of the selective calling system for digital lines according to the present invention.
同図において、送信側にはPCMコーダlと、あらかじ
め決められている受信側の呼出し番号を設定する呼出し
設定スイッチ3と、呼出し設定スイッチ3の設定値をパ
ラレルシリアル変換するパラレルシリアル変換回路2と
、PCMコーダ/出力とパラレルシリアル変換回路2出
力を切り替えて伝送路5へ送信する切替回路4とを偏え
、受信側には伝送路5からの受信信号が入力されるPC
Mデコーダ6およびシリアルパラレル変換回路7と、自
装置番号設定スイッチつと、シリアルパラレル変換回路
7出力と自装置番号設定スイッチ9の設定値とを比較す
る比較回路8と比較回路8で比較したとき両者が一定時
間以上一致していることを検出する一定時間検出回路1
0と、一定時間検出回路10の検出結果を外部へ出力す
る出力回路11とを備えている。In the figure, the transmitting side includes a PCM coder l, a call setting switch 3 for setting a predetermined calling number for the receiving side, and a parallel-to-serial conversion circuit 2 for converting the setting value of the call setting switch 3 from parallel to serial. , the switching circuit 4 that switches between the PCM coder/output and the output of the parallel-to-serial conversion circuit 2 and sends it to the transmission path 5 is biased, and the receiving side is a PC into which the received signal from the transmission path 5 is input.
M decoder 6, serial-parallel conversion circuit 7, self-device number setting switch 1, and comparison circuit 8 that compares the output of serial-parallel conversion circuit 7 with the setting value of own device number setting switch 9.When compared by comparison circuit 8, both A fixed time detection circuit 1 that detects that the values match for a certain period of time or more.
0, and an output circuit 11 that outputs the detection result of the detection circuit 10 to the outside for a certain period of time.
続いて本実施例の動作について説明する。Next, the operation of this embodiment will be explained.
送信側からある特定の受信vs登選択呼出ししようとす
るとき、この受信側の番号を呼出し設定スイッチ3に設
定して呼出し操作を行うと、呼出し設定スイッチ3の設
定値がパラレルシリアル変換回路2に与えられてパラレ
ルシリアル変換され、切替回路4に入力される。切替回
路4は、呼出し操作中は呼出し設定スイッチ3からの指
示によりパラレルシリアル変換回路2の信号をPCM伝
送路の同期に合わせて伝送路5に送出する。When attempting to call a specific reception vs. registration selection from the sending side, if the receiving side number is set in the call setting switch 3 and the calling operation is performed, the setting value of the call setting switch 3 is changed to the parallel serial converter circuit 2. The received signal is subjected to parallel-to-serial conversion and input to the switching circuit 4. During a calling operation, the switching circuit 4 sends the signal from the parallel-to-serial conversion circuit 2 to the transmission line 5 in synchronization with the PCM transmission line according to an instruction from the call setting switch 3.
受信側では伝送路5から受信した信号がシリアルパラレ
ル変換回路7に入力され自装置番号設定スイッチ9の設
定値と比較回路8で比較され、一定時間゛(例えば0.
1秒間〉以上一致し続けていれば一定時間検出回路10
から出力回路11を介して外部のブザー等を鳴動させ自
装置が呼び出されたことを知らせる。On the receiving side, the signal received from the transmission line 5 is input to the serial-parallel conversion circuit 7, and is compared with the setting value of the own device number setting switch 9 by the comparison circuit 8, and the signal is input for a certain period of time (for example, 0.
If the match continues for more than 1 second, the detection circuit 10
An external buzzer or the like is sounded through the output circuit 11 to notify that the own device has been called.
なお、送信側で呼出し操作を行わないときは、切替回路
4はPCMコーダ1の出力を伝送路5へ送信するので、
受信側ではP CMデコーダ6によりデコードされ一般
的なPCM通信が行われる。Note that when no calling operation is performed on the transmitting side, the switching circuit 4 transmits the output of the PCM coder 1 to the transmission path 5.
On the receiving side, the signal is decoded by a PCM decoder 6 and general PCM communication is performed.
以上説明したように本発明は、ディジタル無線中継回線
の打合せ電話において、比較的簡単な回路で選択呼出し
が行われるので、高信頼性で且つ安価にサービスを提供
できる効果がある9As explained above, the present invention has the advantage of being able to provide services with high reliability and at low cost, since selective calling is performed using a relatively simple circuit in a meeting telephone on a digital wireless relay line.
第1図は本発明のディジタル回線用選択呼出し方式の一
実施例を示すブロック図である。
1−・−・−P CMコーグ、2−・・・−・パラレル
シリアル変換回路、3−・・・・−呼出し設定スイッチ
、4−一・・・切替回路、5−・−・・伝送路、6 ・
−−P CMデコーダ、7 パラレルシリアル変換回
路、8 ・ −比較回路、9 ・・−迫装置番号設定ス
イッチ、10−−一定時間検出回路、11−出力回路。
代理人 弁理士 内 原 音
効′FIG. 1 is a block diagram showing an embodiment of the selective calling system for digital lines according to the present invention. 1----P CM Korg, 2---Parallel-serial converter circuit, 3--- Call setting switch, 4--- Switching circuit, 5--- Transmission line ,6・
--P CM decoder, 7 parallel-serial conversion circuit, 8.--comparison circuit, 9...-compressor number setting switch, 10--fixed time detection circuit, 11-output circuit. Agent Patent Attorney Uchihara Otono'
Claims (1)
をパラレルシリアル変換するパラレルシアル変換回路出
力とを切り替える切替回路を備え、受信側にはPCMデ
コーダと、伝送路からの受信信号をシリアルパラレル変
換するシリアルパラレル変換回路出力と自装置番号設定
スイッチの値とを比較する比較回路と、該比較回路出力
が一定時間以上一致していることを検出する一定時間検
出回路と、該一定時間検出回路の検出結果を出力する出
力回路とを備えることを特徴とするディジタル回線用選
択呼出し方式。The transmitting side is equipped with a switching circuit that switches between the PCM coder output and the output of a parallel-to-serial conversion circuit that converts the value of the call setting switch from parallel to serial, and the receiving side is equipped with a PCM decoder and a PCM decoder that converts the received signal from the transmission line from serial to parallel. A comparison circuit that compares the serial-parallel conversion circuit output and the value of the own device number setting switch, a fixed time detection circuit that detects that the comparison circuit outputs match for a fixed time or more, and detection of the fixed time detection circuit. A selective calling method for a digital line, characterized by comprising an output circuit for outputting a result.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60117126A JPS61274561A (en) | 1985-05-30 | 1985-05-30 | Selective calling system for digital circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60117126A JPS61274561A (en) | 1985-05-30 | 1985-05-30 | Selective calling system for digital circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61274561A true JPS61274561A (en) | 1986-12-04 |
Family
ID=14704080
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60117126A Pending JPS61274561A (en) | 1985-05-30 | 1985-05-30 | Selective calling system for digital circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61274561A (en) |
-
1985
- 1985-05-30 JP JP60117126A patent/JPS61274561A/en active Pending
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