JPS6126999A - Read only memory - Google Patents

Abstract

PURPOSE:To achieve the high integration compared to an ordinary ROM of binary 1-bit constitution per memory cell by storing information of signal levels of three steps or more in a memory cell. CONSTITUTION:A load resistance 8 is so set to take any one of 16 types of resistance values, and can store information of 4-bits in a binary form. Each memory cell is set in such a way that the resistance value of the load resistance will come to a prescribed resistance value out of 16 types of resistance values. Accordingly, an A/D converter 16 has a resolution to discriminate 16 types of signal levels decided by the load resistance 8. In this manner, one memory cell can store information of signal levels of three steps or more, and the high integration can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a read-only memory (hereinafter referred to as ROM), a so-called mask ROM, which is used as a program memory, data memory, etc. and whose memory contents are fixed in a wafer process.

(Prior Art) Generally, in a ROM, one memory transistor stores one of two types of signals rlJ' and rOJ, corresponding to one bit. Therefore, the number of transistors equal to the memory capacity is required, and there is a limit to increasing the density.

(Purpose) The present invention aims to increase the density of a mask ROM by increasing the number of types of stored information per memory cell having one transistor to three or more. .

(Configuration) In the ROM of the present invention, a load resistor is connected to the transistor of the memory cell, and this resistor is set to one of three or more resistance values, and the memory cell is controlled based on the set resistance value. The output signal is configured to be detected by a detector having a required resolution.

In this way, by reading one memory cell, any of three or more types of information can be obtained.

The present invention will be specifically described below based on Examples.

FIG. 1 shows four memory cells out of a large number of memory cells. To explain one memory cell 2, the memory cell 2 is a MOS selected by a word line 4.
)-, a transistor, and a load resistor 8 connected to the drain of the MOS transistor 6. The other end of the load resistor 8 is connected to a bit line 10, and one end of this bit line 10 is connected to a constant current power supply 14 via a MoS transistor 12.
The other end is connected to an A/D converter 16 as a detector.

The load resistor 8 is set to take one of 16 resistance values, and can store 4 bits of information in binary form. Each memory cell is set such that the resistance value of the load resistor is a predetermined resistance value among 16 types of resistance values. Therefore, the A/D converter 16 has a resolution capable of identifying 16 types of signal levels determined by the load resistor 8.

The operation of this embodiment will be explained.

One memory cell 2 is selected by an address decoder (not shown).
When is selected, a current flows from the constant current power supply 14 through the MOS transistor 12 to the load resistor 8 and the MOS transistor 6, and the signal level of the bit line 10 becomes a voltage corresponding to the resistance value of the load resistor 8. /D converter 16
Detected by

Next, when the memory cell selection is switched, the signal level of the bit line 10 becomes a voltage corresponding to the load resistance of the switched memory cell. By switching the memory cell selection in this way, the signal on the bit line 10 detected by the A/D converter 16 changes stepwise in 16 steps.

The A/D converter 16 outputs the 16-step signal as a 4-bit binary signal.

As for the reading method, one memory cell can be read in one access. Also, one memory cell is accessed four times, and the A/D converter 16 uses the LSB (
It is also possible to read out four bits by sequentially reading from the least significant bit to the MSB (most significant bit).

Next, a method of setting the resistance value of the load resistor 8 of the memory cell will be explained.

A meandering pattern 20 of a high resistance polysilicon layer as shown in FIG. 2 is formed between the drain region of MOS transistor 6 of each memory cell and bit line 1o. A resist is applied thereon, and a resist pattern is formed that has openings in the area surrounded by the broken line 22 according to the resistance value to be set by exposure and phenomena. Using this resist pattern as a mask, impurities such as arsenic are ionized. The polysilicon layer is injected using an injection method and the resistance of the polysilicon layer in that region is lowered, thereby giving each memory cell a predetermined resistance value.

Although FIG. 3 also shows a similar load resistor 8.

In this case, a rod-shaped high-resistance polysilicon layer 24 is used, and ions are implanted using a resist pattern having openings 26 in predetermined areas as a mask in the same manner as shown in FIG. 2, thereby obtaining a predetermined resistance value. It is.

In the example shown in FIG. 1, when one memory cell is read out, 16 levels of signals, ie, 4-bit binary information, can be read out. Therefore, R with n memory cells
In the OM configuration, the RO has a memory capacity of 4n bits.
Become M. The types of load resistances per memory cell are not limited to those in the above embodiments, and can be increased or decreased.

Further, the A/D converter 16 for detecting many types of signal levels of memory cells may be any type having resolution sufficient to identify a given type of signal level. A sense amplifier can also be used in place of the A/D converter 16.

(Effects) According to the ROM of the present invention, information of three or more signal levels can be stored in one memory cell.
Higher density can be achieved than in the conventional ROM having a binary 1-bit configuration per memory cell.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention, and FIGS. 2 and 3 are plan views showing a method of calculating the resistance value of a load resistor, respectively. 6... Memory cell transistor, 8...
...Load resistance, 14... Constant current power supply,
16...A/D converter.

Claims (1)

[Claims] (1) Identifying a memory cell transistor having a load resistance having one of three or more types of resistance values, a constant current power source that supplies a constant current to the memory cell transistor, and an output signal based on the three or more types of resistance values. A read-only memory characterized by comprising: a detector having a resolution of 1.