JPS61269584A - Half-tone control signal processing circuit - Google Patents

Half-tone control signal processing circuit

Info

Publication number
JPS61269584A
JPS61269584A JP60112696A JP11269685A JPS61269584A JP S61269584 A JPS61269584 A JP S61269584A JP 60112696 A JP60112696 A JP 60112696A JP 11269685 A JP11269685 A JP 11269685A JP S61269584 A JPS61269584 A JP S61269584A
Authority
JP
Japan
Prior art keywords
signal
processing circuit
signal processing
circuit
luminance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60112696A
Other languages
Japanese (ja)
Inventor
Kazuhiro Kitamura
喜多村 和洋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP60112696A priority Critical patent/JPS61269584A/en
Publication of JPS61269584A publication Critical patent/JPS61269584A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00Television systems
    • H04N7/08Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division

Abstract

PURPOSE:To vary automatically an output luminance level by a simple circuit constitution, and to make a character easily visible by shifting a parallel luminance signal of (n) bits by 1 bit, based on a Y<+> signal. CONSTITUTION:A composite signal which has been received and detected is supplied to a chrominance signal processing circuit 5 and a luminance signal processing circuit 6, through an A/D conversion circuit 4. A luminance signal of (n) bits which has been processed by the circuit 6 is sent to a Y<+> signal processing circuit 7, D/A-converted 9 and applied to a matrix circuit 10. The processing circuit 7 is provided with an input memory, a digital switch, and an output memory, and in a period in which a Y<+> signal is generated, a parallel luminance signal of (n) bits is shifted by 1 bit, based on the Y<+> signal. In this way, a 1/2 luminance level can be obtained automatically, and a character of a super time can be made easily visible.

Description

【発明の詳細な説明】 (技術分野) 本発明は、文字多重放送対応のデジタルテレビにおける
ハーフトーン制御信号処理回路に関する。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a halftone control signal processing circuit in a digital television compatible with teletext broadcasting.

(従来技術) 近年、放送、パソコンのニューメディアテレビへの進展
はめざましいものがあり、RGB端子を備え、スーパー
インポーズ機能を持つパソコンテレビ、パソコンの増勢
に加え、文字多重アダプタを備えたニューメディア対応
のデジタルテレビが開発されている。
(Prior art) In recent years, there has been a remarkable progress in broadcasting and new media television from personal computers.In addition to the increasing number of personal computer televisions and personal computers equipped with RGB terminals and superimpose functions, new media equipped with text multiplex adapters are increasing. Compatible digital televisions are being developed.

従来、文字多重対応機では、文字多重放送受信時、RG
Bビデオ信号をハーフトーンにするためのハーフトーン
制御信号(以下、Y+倍信号いう)が用いられている。
Conventionally, when receiving a text multiplex broadcast, on a text multiplex compatible device, the RG
A halftone control signal (hereinafter referred to as Y+ times signal) is used to halftone the B video signal.

このY+倍信号、例えば、白文字を見易くするため、文
字の背景または輪郭部分の輝度を成る程度下げるために
用いられる。
This Y+ signal is used, for example, to reduce the brightness of the background or outline of a white character to some extent in order to make it easier to see the character.

しかしながら、従来のY+信号処理方法は、RGBビデ
オ信号のレベルを下げてハーフトーンにする手法である
ため、垂直、水平同期信号を除いたRGBビデオ信号と
Y+倍信号が重なる期間、RGBビデオ信号をハーフト
ーンにする必要があり、回路が複雑化するなどの欠点が
あった。
However, since the conventional Y+ signal processing method lowers the level of the RGB video signal and converts it into a halftone, the RGB video signal is There were drawbacks such as the need to use halftones, which made the circuit more complex.

(発明の目的) 本発明は、前述の従来の欠点を除去することを目的とす
る。
OBJECTS OF THE INVENTION The present invention aims to eliminate the above-mentioned conventional drawbacks.

(発明の構成) 本発明はこのような目的のためになされたものであり、
特にコンポジットビデオ信号のA/D変換出力を分離し
て得られるnビットの並列デジタル輝度信号を、文字多
重放送受信時に、Y+倍信号基づいて1ビットシフト処
理することにより、文字の背景または輪郭部分の輝度レ
ベルを自動的に下げるようにしている。
(Structure of the invention) The present invention has been made for the above purpose,
In particular, when receiving a teletext broadcast, the n-bit parallel digital luminance signal obtained by separating the A/D conversion output of a composite video signal is shifted by 1 bit based on the Y + times signal, so that the background or outline of the character can be processed. The brightness level is automatically lowered.

(実施例) 第1図は、本発明のデジタルテレビにおける映像信号処
理システムを示す一実施例のブロック図である。第1図
において、アンテナlで受信されたテレビ電波の中から
目的の局をチューナ2で選択し、次のブロック3で中間
周波増幅、映像検波することにより、映像検波出力とし
てコンポジットビデオ信号が得られる。このコンポジッ
トビデオ信号はA、l/D変換回路4に加えられてデジ
タルコンポジットビデオ信号に並列出力として取り出さ
れ、色信号処理回路5および輝度信号処理回路6に加え
られる。そして、ここで色差信号と輝度信号とに分離さ
れる。輝度信号は、nビ・ソトの並列デジタル信号で構
成され、Y+信号処理回路7へ加えられる。Y+信号処
理回路7で処理されたnビットの並列デジタル輝度信号
と前記色差信号はそれぞれD/A変換回路8.9により
アナログ信号に変換され、RGBマトリックス回路10
に加えられる。11は文字多重処理回路部であり、文字
多重放送を受信すると、文字信号Slと/’% −フト
ーンコントロール用のY+信号S2が出力される。文字
信号SlはRGBマトリックス回路10へ加えられ、R
GB出力回路12を介してRGBビデオ信号によるCR
T l 3の画面にスーツクーした静止文字を再生表示
する。
(Embodiment) FIG. 1 is a block diagram of an embodiment of a video signal processing system for a digital television according to the present invention. In Figure 1, tuner 2 selects a target station from among the television waves received by antenna 1, and the next block 3 performs intermediate frequency amplification and video detection to obtain a composite video signal as the video detection output. It will be done. This composite video signal is applied to an A, L/D conversion circuit 4, taken out as a parallel output into a digital composite video signal, and applied to a color signal processing circuit 5 and a luminance signal processing circuit 6. Then, it is separated into a color difference signal and a luminance signal. The luminance signal is composed of n-bisoto parallel digital signals and is applied to the Y+ signal processing circuit 7. The n-bit parallel digital luminance signal and the color difference signal processed by the Y+ signal processing circuit 7 are each converted into an analog signal by a D/A conversion circuit 8.9, and the RGB matrix circuit 10
added to. Reference numeral 11 denotes a text multiplex processing circuit section, which outputs a text signal Sl and a Y+ signal S2 for /'%-tone control when receiving a text multiplex broadcast. The character signal Sl is applied to the RGB matrix circuit 10, and the R
CR by RGB video signal via GB output circuit 12
The static characters suit-cooked are played back and displayed on the screen of Tl3.

一方、音声信号は音声信号処理回路14を介して左右チ
ャンネルのスピーカ15.16により出力される。
On the other hand, the audio signal is outputted from the left and right channel speakers 15 and 16 via the audio signal processing circuit 14.

前記構成において、本発明はnビットの並列デジタル輝
度信号をハーフトーン制御(Y+)信号に基づいてコン
トロールするY+信号処理回路7に特徴を有する。
In the above configuration, the present invention is characterized by the Y+ signal processing circuit 7 that controls the n-bit parallel digital luminance signal based on the halftone control (Y+) signal.

第2図はこのY+信号処理回路の具体的回路構成図であ
る。第2図において、71は輝度信号処理回路6から入
力されるnビットの並列デジタル輝度信号を一時記憶保
持する人力メモリ、例えばフィールドメモリであり、R
AMで構成できる。
FIG. 2 is a specific circuit configuration diagram of this Y+ signal processing circuit. In FIG. 2, reference numeral 71 is a manual memory, for example, a field memory, which temporarily stores and holds the n-bit parallel digital luminance signal input from the luminance signal processing circuit 6;
It can be configured with AM.

MSBは最上位ビット、LSBは最下位ビットをそれぞ
れあられす、73はnビットに対応したスイッチング回
路である。例えば、デジタルスイッチであり、Y+倍信
号S2)でハイレベル゛のとき、nビットのスイッチが
aポジションからbポジションへ切替わる。スイッチが
切替えられると、入力メモリ71のnビット内容は出力
メモリ72へ転送され、出力メモリ72からlビットシ
フトされた並列デジタル輝度信号があられれる。出力メ
モリ72も入力メモリ71と同様に構成できる。
MSB is the most significant bit, LSB is the least significant bit, and 73 is a switching circuit corresponding to n bits. For example, it is a digital switch, and when the Y+multiple signal S2) is at a high level, the n-bit switch switches from the a position to the b position. When the switch is toggled, the n-bit contents of the input memory 71 are transferred to the output memory 72, from which the l-bit shifted parallel digital luminance signal is obtained. The output memory 72 can also be configured similarly to the input memory 71.

次の(1)は入力メモリ71の記憶状態であり、(2)
は入力メモリ71から出力メモリ72へとシフトされた
ときの該出力メモリ72内の前記nピット輝度信号のシ
フト記憶状態を示している。
The following (1) is the storage state of the input memory 71, and (2)
shows the shifted storage state of the n-pit luminance signal in the output memory 72 when it is shifted from the input memory 71 to the output memory 72.

M S B       LS B 101100’IO・・・(1) MSB       LSB 01011001     ・・・(2)この(1)(
2)から明らかなように出力メモリ72の最上位ビット
には「0」が挿入され、出力輝度レベルは入力輝度レベ
ルの1/2となることが分かる。
M S B LS B 101100'IO...(1) MSB LSB 01011001...(2) This (1)(
As is clear from 2), "0" is inserted into the most significant bit of the output memory 72, and the output luminance level becomes 1/2 of the input luminance level.

このように、Y+倍信号発生期間、Y+倍信号基づいて
nビットの並列デジタル輝度信号を1ビットシフトさせ
ることによりI/2の出力輝度レベルを自動的に得るこ
とができ、スーパ一時の文字を見易くすることが可能で
ある。
In this way, the output brightness level of I/2 can be automatically obtained by shifting the n-bit parallel digital brightness signal by 1 bit based on the Y+ times signal during the Y+ times signal generation period. It is possible to make it easier to see.

第3図は前記文字信号S1、Y+倍信号S2)およびR
GBビデオ信号との関係を示す一例の波形図である。第
4図において、Sl、S2はそれぞれ文字多重放送受信
時、文字多重信号処理回路部11から出力される文字信
号とY+倍信号あり、S3はY+信号S2によりハーフ
トーンにした、即ち、輝度を落とした信号S4となる。
FIG. 3 shows the character signal S1, Y+multiple signal S2) and R
FIG. 3 is an example waveform diagram showing a relationship with a GB video signal. In FIG. 4, Sl and S2 are a character signal and a Y+ multiplied signal output from the text multiplex signal processing circuit section 11 when receiving teletext broadcasting, respectively, and S3 is halftoned by the Y+ signal S2, that is, the brightness is changed. This becomes the dropped signal S4.

この信号S4に文字信号Slが加えられて、文字信号S
lをスーパーしたRGBビデオ信号S5が得られる。
The character signal Sl is added to this signal S4, and the character signal S
An RGB video signal S5 superposed with 1 is obtained.

(発明の効果) 以上説明したように、本発明によればY+(ハーフトー
ン)信号の発生期間、Y+倍信号基づいてnビットの並
列デジタル輝度信号を1ビットシフトさ什ることにより
、出力輝度レベルを簡単な回路構成にて自動的に変化さ
せるこ々ができ、文字多重放送受信時の文字を見易く再
生表示できる。
(Effects of the Invention) As explained above, according to the present invention, the output luminance can be adjusted by shifting the n-bit parallel digital luminance signal by 1 bit based on the Y+ signal during the generation period of the Y+ (halftone) signal. The level can be automatically changed with a simple circuit configuration, and characters can be reproduced and displayed in an easy-to-read manner when receiving teletext broadcasting.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係るデジタルテレビにおける映像信号
処理システムを示す一例のブロック図、第2図はY+信
号処理回路の具体的回路構成図、第3図は文字信号Sl
、Y+信号S2およびRGBビデオ信号との関係を示す
一例の波形図である。 符号の説明 6は輝度信号処理回路、7はY+信号処理
回路、71は入力メモリ、72は出力メモリ、73はス
イッチング回路、11は文字多重信号処理回路部、St
は文字信号、S2はY+信号、S3はRGBビデオ信号
FIG. 1 is a block diagram of an example of a video signal processing system in a digital television according to the present invention, FIG. 2 is a specific circuit configuration diagram of a Y+ signal processing circuit, and FIG. 3 is a character signal Sl
, Y+ signal S2 and an RGB video signal. Explanation of symbols 6 is a luminance signal processing circuit, 7 is a Y+ signal processing circuit, 71 is an input memory, 72 is an output memory, 73 is a switching circuit, 11 is a character multiplex signal processing circuit section, St
is a character signal, S2 is a Y+ signal, and S3 is an RGB video signal.

Claims (1)

【特許請求の範囲】[Claims] (1)コンポジットビデオ信号のA/D変換出力を分離
して得られるnビットの並列デジタル輝度信号を一時記
憶保持する手段と、 文字多重放送の受信時に文字信号およびハーフトーン制
御信号を出力する手段と、 ハーフトーン制御信号の出力期間、該ハーフトーン制御
信号に基づいて前記nビットの並列デジタル輝度信号を
1ビットシフト処理する手段を設け、 文字の背景もしくは輪郭部分の輝度レベルを下げるよう
にしたことを特徴とするハーフトーン制御信号処理回路
(1) Means for temporarily storing and holding an n-bit parallel digital luminance signal obtained by separating the A/D conversion output of a composite video signal, and means for outputting a character signal and a halftone control signal when receiving teletext broadcasting. and means for shifting the n-bit parallel digital luminance signal by 1 bit based on the halftone control signal during the output period of the halftone control signal, thereby lowering the luminance level of the background or outline of the character. A halftone control signal processing circuit characterized by:
JP60112696A 1985-05-24 1985-05-24 Half-tone control signal processing circuit Pending JPS61269584A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60112696A JPS61269584A (en) 1985-05-24 1985-05-24 Half-tone control signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60112696A JPS61269584A (en) 1985-05-24 1985-05-24 Half-tone control signal processing circuit

Publications (1)

Publication Number Publication Date
JPS61269584A true JPS61269584A (en) 1986-11-28

Family

ID=14593200

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60112696A Pending JPS61269584A (en) 1985-05-24 1985-05-24 Half-tone control signal processing circuit

Country Status (1)

Country Link
JP (1) JPS61269584A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002199305A (en) * 2000-12-25 2002-07-12 Sanyo Electric Co Ltd Halftone circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002199305A (en) * 2000-12-25 2002-07-12 Sanyo Electric Co Ltd Halftone circuit

Similar Documents

Publication Publication Date Title
US4518984A (en) Device for flicker-free reproduction of television pictures and text and graphics pages
JPH0591528A (en) Apparatus for correcting profile of color signal
JPH05336503A (en) Video additional information discriminating device
JPS61269584A (en) Half-tone control signal processing circuit
JPH0787526A (en) Sampling rate conversion system
JP2630872B2 (en) Television receiver
JP3106560B2 (en) Video signal level display
JP3460428B2 (en) On-screen synthesis device for digital broadcast receiver
KR100251854B1 (en) The apparatus for picture in picture(pip) process
JPS60119184A (en) Television video signal processor
JPH077662A (en) Television receiver
JP3021257B2 (en) Video signal processing circuit
KR930003283B1 (en) Negative image transformer of digital tv
JPS6117653Y2 (en)
KR910000550B1 (en) Digital image signal processing system for multi-screen displaying
KR940004178Y1 (en) Tv receiving system
JP3433768B2 (en) Television equipment
JPH0350974A (en) Television receiver
JP3825856B2 (en) Video signal processing device for television receiver
JPS6171792A (en) Superimpose circuit
JPH0358691A (en) Television signal converter
JPS61147696A (en) 2-screen television receiver
JPH0666951B2 (en) Receiving machine
JPS62134774A (en) Image information processor
JPH02189086A (en) High definition television receiver