JPS61269356A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a large-capacitance capacitor having extremely high area efficiency by forming an extremely large capacitance element between a base terminal for a base grounding type transistor constituting a cascade step and a grounding point for a semiconductor integrated circuit with an amplification circuit in the semiconductor integrated circuit. CONSTITUTION:An N-type buried layer 2 is formed to a capacitance section C at the same time as an N<+> type buried layer 2 shaped to a bipolar transistor and P channel transistor forming section, and a first electrode 9 and a dielectric layer 8 are shaped to a capacitance section C at the same time as the formation of a gate oxide film 8' and a gate electrode 9' in N, P channel MOSs. An N<+> type semiconductor region 6 is shaped to the capacitance section C at the same time as a collector leading-out port 6' for the bipolar transistor, and N-type impurity introduction layers 10a, 10b are formed to the capacitance section C at the same time as the formation of source-drain regions 10a', 10b' in the N channel MOS.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to semiconductor technology and to technology that is particularly effective when applied to the formation of large capacitance in semiconductor devices, such as bipolar integrated circuits or bipolar transistors and MISFETs on the same semiconductor substrate. The present invention relates to a technique that is effective when a relatively large capacity is required in a semiconductor integrated circuit formed with an insulated gate field effect transistor (insulated gate field effect transistor).

[Background technology] Nikkei Electronics Magazine 1 published on September 26, 1983
As shown on pages 25 to 139, the capacity and speed of static RAMs are increasing.

On the other hand, the applicant and others have been conducting research from the viewpoint of reducing power consumption and increasing speed of static RAM.
We have developed a technology to configure this using both bipolar transistors and MOS transistors. The outline is as follows. In other words, an address circuit in a semiconductor memory.

In timing circuits, etc., output transistors that charge and discharge long-distance signal lines and output transistors with large fan-outs are constructed of bipolar transistors, and are used for logic processing such as inversion, non-inversion, NAND, NAND, etc.
A logic circuit that performs processing such as OR is composed of a 0M05 circuit. The logic circuit configured by the 0M03 circuit has low power consumption, and the output signal of this logic circuit is transmitted to a long-distance signal line via a bipolar output transistor with low output impedance. By transmitting the output signal to the signal line using a bipolar output transistor with low output impedance, the dependence of the signal propagation delay time on the stray capacitance of the signal line can be reduced.

The idea is to obtain a high-speed semiconductor memory with low power consumption.

High speed using the bipolar/0MO8 mixed technology mentioned above.
Based on the low power consumption SRAM technology, the present inventors have considered reducing the impedance of the power supply line.

FIG. 4 shows a part of the internal circuit of a static RAM using the bipo 50 MO8 mixed technology, which was also developed by the present inventors.

The figure shows a memory cell M that holds information.

An example of a sense amplifier SA, a data output intermediate amplifier DOIA that further amplifies the output of this sense amplifier, and a data output cover sofa circuit DOB is shown.

Complementary data line pair D is connected to memory cell M-CEL, and the other end is connected to the Y selection switch (
Column switches) Ql and τ1 are connected to the common data lines CDL and CDL. Therefore, the memory information written in one selected memory cell M-CEL can be read by detecting, by the successive sense circuit SA, changes in the potentials complementary to each other on the common data lines CDL, CDL. Each of the selection switches Ql, Ql in the Y selection switch row is constructed using an MO8 field effect transistor. The Y selection switches are all OFF (non-conducting) when they are not selected, that is, when no valid address data is input.

The sense amplifier SA includes a pair of emitter-coupled bipolar differential transistors T21tT22 and a constant current source MI.
It is composed of 5 FET T2°.

When an appropriate selection control signal Sl is applied to the gate electrode of the constant current source MISFET T2O, the sense amplifier SA performs a sensing operation.

Data output intermediate amplifier D○TA from timing generation circuit
When a high-level internal chip select signal C8 is applied to the gate electrodes of the constant current sources Mr 5FET T23 to T26, the data output intermediate amplifier DOIA performs an amplification operation.

Therefore, the output signal of the sense amplifier SA is transmitted to the common base transistor T27. T28, emitter follower transistor T29. T30, output MISFET T3s~T
38, it is transmitted to the output node N11 of the data output intermediate amplifier D○IA. Data output buffer circuit DO
B is supplied with the data output buffer 7 control signal DOC output from the timing generation circuit.

The data output buffer circuit DOB is MISFE'r'r
A pure CMOS inverter consisting of ,9*'r,O.

A quasi-CMO3/2-manpower NAND circuit consisting of transistors T41-T48, a quasi-CMO5/2-manpower NOR circuit consisting of transistors T49-T56, and a MISFET for a P-channel switch.

MISFETTea for N-channel type switches.

P channel type M I S FET Ts,
M I S F E T T for N channel current output
6o.

When the data output buffer control signal DOC is at high level, the switch MI 5FET T5. and T58 turn on, which turns off the output MISFET Tss and Te0 at the same time, so the data output buffer circuit DOB
The output Dout is in a high impedance (floating) state.

When reading information, the data output buffer control signal DC
)C becomes low level, and MISFET T5 for switch
．． and T'sa are turned off, and the data output intermediate amplifier DO
Quasi-CM in response to the signal level of output node N11 of IA
MI5 for output by the output of O3・2 manual NOR circuit
FETT,, and Te. The gate electrode of is controlled, and valid data can be obtained from the output terminal Dout.

In order to reduce the on-resistance of the output MI 5FET T6 as Too, the channel width of these MISFETs is set to an extremely large value. Then, these M I S F E T T s t T e
The gate capacitance of o becomes extremely large. However, the output part of the quasi-CMO 3/2-power NOR circuit is composed of bipolar output transistors T4 and T48, and the quasi-CMO
The output section of the 3.2-power NOR circuit is composed of bipolar transistors T6s, T, . Therefore, these output MISFETs T59. Charging and discharging of the gate capacitance of T60 is performed at high speed.

What should be noted is that in the Bi-0MO8 type static RAM of this embodiment, the output Dout rises and falls at a much faster rate (2ms to 3m5) than in the fully MOS type static RAM. That is, the output D
The capacitive load Cs1 connected to ou can be charged and discharged at high speed.

However, it has been found that there are cases in which it is not possible to achieve faster access times.

That is, when the output Dout becomes low level, the capacitive load Cs1 is discharged, and a current I flows through the ground wiring through the transistor T'eo, high frequency An induced current is generated and the ground potential fluctuates.

This fluctuation component is caused by, for example, the base-grounded transistor T27 of the data output intermediate amplifier DOIA, which has a common ground wiring.
Transistors T23 and T28 serve as constant power supplies for +l and T28.
24, T2B, the transistors T23, T24, and T25 have high impedances when viewed from the ground side, so the base-grounded transistor 'r2. ．． 'r2. The base potential of , does not change.

However, the collectors of the differential pair transistors T21 and T22 of the sense amplifier SA formed on the semiconductor substrate and the common base transistor T27 . The wiring between the emitters of T28 is long and has a large stray capacitance C between it and the ground area of the semiconductor substrate.
s exists, the high frequency fluctuation component is propagated from the ground area to the wiring via this stray capacitance Cs,
The emitter potentials of common base transistors T2 and T28 are varied. As mentioned above, since the base potential is clamped, the transistor 'r2. ．． The base-emitter potential VBE of transistors T27.'r, . T
The high speed and reliable operation of 2111 will be hindered.

The present invention has been made in view of the above.

[Object of the Invention] An object of the present invention is to provide a semiconductor technology that can increase the speed of a semiconductor integrated circuit device.

Another object of the present invention is to provide a semiconductor integrated circuit device that includes:
Our goal is to provide semiconductor technology that can most efficiently obtain large capacity.

The above-mentioned and other objects and novel features of the present invention will become clear from the description in this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

That is, in a semiconductor integrated circuit comprising an amplifier circuit including a cascade stage having a pair of grounded base transistors connected to the collector sides of a pair of input differential transistors constituting the differential input stage, the cascade stage is configured. An extremely large capacitive element is connected between the base terminal of the grounded base transistor and the ground point of the circuit.

With the above configuration, potential fluctuations of high frequency components are propagated from the ground point to the wiring through the large stray capacitance that exists in the wiring between the collector side of the input differential transistor and the emitter of the pair of grounded base transistors. Even if the emitter potential of the grounded base transistor fluctuates, a capacitive element is connected between the base terminal of the grounded base transistor and the ground point, and the potential of a high frequency component that is in phase with the emitter potential fluctuation is transmitted through the capacitive element. Fluctuations are actively propagated to the base terminal, the potential difference between the emitter potential and the base potential is made constant, and speeding up of the semiconductor integrated circuit device is achieved.

This capacitive element must have the following characteristics. In other words, in order to make the fluctuations in the emitter potential and base potential the same, the capacitance value must be as large as the above-mentioned stray capacitance, and it must also be a low impedance capacitor with good high frequency characteristics, that is, a capacitor with small parasitic resistance. be.

This capacitive element is designed to reduce its parasitic resistance in order to efficiently propagate high-frequency fluctuation components.

In other words, when the fluctuation component propagates, the apparent charge movement path is divided into two paths: one that passes through the n-type diffusion layer, and one that passes through the n-type buried layer and the n-type layer. The parasitic resistances are connected in parallel when viewed from the ground side, reducing the total parasitic resistance value and creating a capacitive element with low impedance.

Furthermore, this capacitive element is the largest capacitive element that can be formed without changing the process of forming a bipolar transistor and a MOS transistor on the same semiconductor substrate.

That is, the first electrode of the capacitive element is made of the gate material of the MoS transistor, the dielectric of the capacitive element is made of the gate oxide film of the MOS transistor, and the second electrode of the capacitive element is made of the source/drain region of the NMOS transistor. It is composed of an n-type diffusion layer formed at the same time, a collector buried layer of an NPN bipolar transistor, an n-type buried layer formed at the same time as a collector electrode extraction layer in contact therewith, and an n-type layer.

[Example] First, the present invention will be explained in detail.

FIG. 1 shows an internal circuit of a BE-CMOS static RAM to which the present invention is applied, in which grounded base transistors Q21 . Q22 and the above Q21.0
Emitter follower transistor T29 connected to 22
．． T2O and output transistors T'as, T'e. It is shown.

The characteristic feature is that the grounded base transistors Q21, Q
The reason is that the capacitive element C is connected to the common base terminal of 22.

This capacitive element C efficiently propagates the high frequency fluctuation component generated by the operation of the output transistor T60 to the base terminal, and propagates it to the output wiring 1 and L2 of the differential pair transistors Q11Q12 via the large stray capacitance Cs. Transistors Q21, Q that fluctuate due to high frequency fluctuation components
The base potential is varied in phase with the emitter potential of 2□.

This makes the bases of transistors Q21 and Q22.

Achieving high speed semiconductor integrated circuits by keeping the emitter potential constant.

This capacitive element C has the largest capacitance and is formed without changing the process of forming a bipolar transistor and a MOS transistor on the same substrate, and
In order to efficiently propagate high frequency fluctuation components, it is a low impedance capacitive element with extremely low parasitic resistance.

FIG. 2 shows a specific structure of the capacitive element.

Characteristically, in order to reduce parasitic resistance, a charge transfer path a connected to the ground potential via N-type impurity doped layers 10a and 10b and an N-well region 4°N-type buried layer 2, N+
Two charge transfer paths are provided which are connected to the ground potential via the type semiconductor region 6, and the parasitic resistances of these paths are connected in parallel to reduce the total parasitic resistance.

FIGS. 3(a), (b), and (c) show the formation process of the capacitive element.

The characteristic feature is that the capacitive element is formed without changing the process of forming bipolar transistors and MOS transistors on the same substrate.

That is, at the same time as the N+ type buried layer 2 formed in the bipolar transistor and P channel transistor forming portions,
(See Figure 3(a))
- At the same time as forming the gate oxide film 8' and gate electrode 9' of the -N and P channel MOS, the first electrode 9 and the dielectric layer 8 are formed in the capacitive part C (see FIG. 3(b)), and the gate electrode 9' of the bipolar transistor is formed. At the same time as the collector outlet 6', an N+ type semiconductor region 6 is formed in the capacitive part C (see FIG. 3(e)).
, N-channel MOS source/drain region 10a'
, 10b', an N-type impurity introduced layer 10alOb is formed in the capacitive portion C at the same time.

The present invention has been briefly explained in detail above.

Next, the present invention will be explained in detail using the drawings.

First, Figures 2 and 3 (, ), (b), (C), (d
), the structure and formation process for increasing the capacitance and lowering the impedance of the capacitive element will be explained.

In FIG. 2, 1 is a semiconductor substrate such as a P-type wheel crystal silicon substrate, and 2, 2' and 3 are an N+ type buried layer and a P+ type isolation region formed on this semiconductor substrate 1. In FIG. The N+ type buried layer 2.2' is formed by introducing an N type impurity such as antimony onto the main surface of the semiconductor substrate 1 by thermal diffusion or the like using a silicon oxide film or the like formed by oxidizing the surface of the semiconductor substrate 1 as a mask. The 6P 10-type isolation region 3 formed by diffusion is formed by removing the silicon oxide film that served as a mask for forming the N+ type buried layer, and then
It is formed by the same method as the + type buried layer (see FIG. 3(, )).

4 and 5 are the N-type round regions formed on the N medium-sized buried layer 2 and the P+ type isolation region 3 and the
This is the type well area. These well regions 4 and 5 are formed by forming an N-type epitaxial layer over the entire surface of the N+ type buried layers 2, 2' and P+ type isolation region 3 by vapor phase growth. The silicon oxide film is formed by oxidizing the surface of the silicon oxide film, and then photoetching is performed, and an N-type impurity or a P-type impurity is diffused using the silicon oxide film as a mask.

Note that a bipolar transistor and a P-channel MIS FET are formed on the N-type well region 4, and a P-channel MISFET is formed on the N-type well region 4.
An N-channel MISFET is formed on the type well region 5.

A gate electrode 9 such as a polysilicon layer is formed on the main surface of the N-type well region 4 via a gate insulating film 8 (see FIG. 3(b)).

Therefore, in this embodiment, an N+ type semiconductor region 6 is formed extending from the main surface of the substrate to the N+ type buried layer 2 along the periphery of the N type well region 4 where the capacitance is to be formed. . Although not particularly limited, this N+ type semiconductor region 6 is formed by selectively forming a field oxide film 7 for isolation on the surface of the well region 4.5, and then by ion implantation or the like to form the collector pull-up port 6 of the bipolar transistor. ' is formed at the same time as the N+ type semiconductor region (Fig. 3(c)
)reference).

Further, the gate electrode 9 is provided on the main surface of the N-type well region 4.
N+ type semiconductor regions 10a and 10b are formed in a self-aligned manner. This N+ type semiconductor region] Oa, 10b
is an N-channel type M I S F on a P-type middle L region.
ET source and drain regions 10a', 10b
' is formed at the same time (see Figure 3(d)).

In FIG. 2, the P+ type semiconductor region 11 formed on the P type well region 5 is a semiconductor region formed to apply a ground potential to the P type well region 5. In this way, by applying a ground potential to the P-type well region 5 in the vicinity of the N-type well region 4 where the gate capacitance is formed, the flow of charge accompanying charging and discharging of the capacitance is caused to flow to the P-type well, and Potential fluctuations in the N-type well region 4 are reliably prevented. P
An N-channel MISFET is formed on the type well region 5. In addition, each of the semiconductor regions 6, 10a, 10b
, 11 are each formed with an aluminum electrode layer.

Then, 1 is applied to the N+ type semiconductor regions 6, 10a, and 10b.
Apply circuit ground potential. In addition, the gate electrode 9 has
Apply a potential higher than ground potential. Then, MI constituting the gate capacitance formed on this N-type well region 4
Since the SFET is an N-channel type, when a positive voltage is applied to the gate electrode 9, only electrons that become majority carriers gather, and a channel or inversion layer is not formed under the gate electrode. Well region 4 is biased to ground potential. Therefore, the gate electrode 9 and N
A connection such that an inversion layer is formed between the type well region 4, that is, a capacitance larger than a series connection of a capacitance using the gate oxide film as a dielectric and a capacitance using the inversion layer as a dielectric. It is formed.

Moreover, on the main surface of the well below the gate electrode 9, not only the N+ type semiconductors 10a and 10b but also the N type well region 4
Since there is a path of charge through the N+ type semiconductor region 6 and the N+ type buried layer 2, which have a lower resistance value than that of As a result, the charging and discharging speed of the capacitor becomes faster, and the high frequency characteristics are improved.

In the above embodiment, the N+ type semiconductor region 6 reaching the N+ type buried layer 2 is formed around the entire periphery of the N type well region 4 where the gate capacitor is formed. 6 may be formed not on the entire periphery of the N-type well region 4 but only on a part thereof.

Further, in the above embodiment, N+ type semiconductor regions 10a are provided on both sides of the gate electrode 9 on the main surface of the N type well region 4.

The explanation has been made regarding the one in which 10b is formed.

It is also possible to form a structure in which the periphery of the gate electrode 9 is in contact with the field oxide film 7 and the N+ type semiconductor regions 10a and 10b are not provided.

FIG. 1 shows a Bi
- An example of the configuration of a read circuit of a CMO8 type static RAM is shown.

In a memory array in which a plurality of memory cells are arranged in a matrix, each memory cell MC is connected to a word line W selectively driven by a word line selection drive circuit (word driver) WDR and a complementary data line D. They are placed at each intersection with the

The complementary data line D''' is connected to the common data lines CDL and CDL via the column switch Y-SW and 'y-sw2, which are controlled on and off by the Y decoder Y-DEC.
It is connected to the. Although not shown, one, for example, 32 pairs of data lines are connected to the common data lines CDL, CDL. Then, this common data line CDL and σ
101 are respectively connected to the base terminals of a pair of grounded emitter transistors Q11 t Ql 2 constituting a differential input stage.

A constant current source CCo made of a MISFET or the like is connected to the common emitters of the transistors Ql 1 and Ql 2, and the collector terminals of the transistors Ql 11 and Ql 2 are connected to a pair of base-grounded transistors Qx 1 #Qx forming a cascade stage. It is connected to the emitter terminal of 2.

Constant current sources CC1 and CC2 are connected to each emitter terminal of the transistor QzxtQz2, and resistors R1 and R2 are respectively connected between each collector terminal and a power supply voltage terminal Vcc.

The collector terminal of the above transistor Qz 1 # Qlx and the transistor Q21? A differential input stage connected to another common data line pair (not shown) is connected to the signal line L1tL2 that connects the emitter terminal of Q22. In this case, a plurality of (for example, four) differential input stages are connected to one cascade stage. The base terminals of the transistors Q21t Q2x that make up the cascade stage are
A bias voltage generated by a resistor R3 and a constant current source CC3 connected in series is applied between the power supply voltage terminal Vcc and the ground point of the circuit.

The differential input stage and the cascade stage each constitute a differential amplifier (sense amplifier). The transistors Q21 and 022 quickly charge the relatively large stray capacitance parasitic on the signal line L1eL2, thereby increasing the read speed. The differential output of the cascade stage or its further amplified signal is sent to the output buffer DOB, where a read signal is formed and output.

In this embodiment, a clamp diode D 1 t D 2 is connected in parallel with the resistors R1 and R2 between the collector terminal of the transistor Q2x + 02□ constituting the cascade stage and the power supply voltage terminal Vcc. .

Due to this clamp diode D1+02, when a large current flows through the transistor Q2xtQzz, the collector voltage decreases and the transistor Q2 z p
Q22 can be prevented from operating in saturation.

Furthermore, in this embodiment, a capacitor C for noise propagation is connected between the base terminal of the transistor Q21 t Q22 constituting the cascade stage and the ground point.

This capacitor C can suppress the influence of fluctuations in the ground potential transmitted from the ground line of the output buffer DOB on the readout circuit.

That is, when the output of the output buffer DOB changes to low level, the ground side transistor (MISFET) in the output buffer DOB operates to extract the charge of the load capacitance connected to the output terminal, so the potential of the ground line increases. It fluctuates greatly.

On the other hand, as described above, if a plurality of differential input stages are connected in a cascade stage, the signal line 1. Stray capacitance C of L2
s becomes considerably large (about ip7). Therefore, when the potential of the ground line fluctuates as described above, the potential of the signal line L1yL2 fluctuates via the stray capacitance Cs, and the operating speed of the sense amplifier may be extremely slowed down.

For example, if the potential of signal lines L1+L2 drops due to potential fluctuations of the ground line, transistor Q2
1 t Assuming that the base potential of Q22 is constant, this causes a large current to flow through the transistor Q21°Q2□. Therefore, the collector voltage of the transistor QzxeQ22 drops to the point where it is clamped by the clamp diode D1*D2, and an accurate signal cannot be transmitted.

However, in the above embodiment, the transistor Q21FQ2
A capacitor C is connected between the base terminal of No. 2 and the ground point. Therefore, even if the potential of the ground line fluctuates and the potential of the signal line L1yL2 fluctuates, the fluctuation of the ground line is transmitted through the capacitor to the transistor Q2tyQ.
It is also transmitted to the base terminal of 2z, and the base potential is connected to the signal line L1.
*It will fluctuate in the same way as the potential of L2. As a result, the read speed will not be slowed down due to potential fluctuations on the ground line.

By the way, in order to make the base potential of the transistor Q21 t Q22 swing in the same way as the potential of the signal line L1vL2, the capacitance value of the capacitor C for noise propagation is equal to the stray capacitance of the signal line L1tL2 (approximately 2p2 on the m side). It is necessary to set the capacitance value to a relatively large value similar to that of the capacitance value. Therefore, as the capacitor for noise propagation, the above embodiment (
If the gate capacitance shown in FIG. 1) is used, a capacitance of about 2P can be obtained with a small occupied area of about 2000 μm2.

Therefore, if the above embodiment is applied to a semiconductor integrated circuit where the chip size is limited and which tends to require a large capacitor, a large capacitor can be easily mounted. Moreover, as in the above embodiment, i-0M08
If used in capacitors in circuits, large capacitance can be obtained in a small area without any process changes.

[Effects] (1) When forming a capacitive element connected between the ground point of a circuit and a higher potential point, , a well region of the same conductivity type as this is formed, a gate capacitor is formed on the surface of this well region, and this is used as the above capacitor, so that an inversion layer is not formed under the gate electrode. This effect prevents the capacitance between the gate and the well from decreasing and allows a large capacitance with extremely high area efficiency to be easily obtained.

(2) A well region of the same conductivity type as the substrate is formed on the semiconductor substrate via a high concentration buried layer of a conductivity type different from that of the substrate, and a gate capacitance is formed on the surface of this well region. Since the capacitor is used as a noise propagation capacitor in a semiconductor integrated circuit device in which a bipolar transistor and a complementary MISFET are formed on the same semiconductor substrate, such a capacitor can be formed without any process changes. It has the effect of being able to

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, in the above embodiment, the case was explained in which the capacitor was applied to a capacitor connected between the ground potential and a higher potential point. It is also possible to apply to connected capacitors.

[Field of Application] In the above explanation, we have mainly explained the application of the invention made by the present inventor to a capacitor for noise propagation in a Bi-CMO 8 type static RAM circuit, which is the field of application that formed the background of the invention. The invention is not limited thereto, but can also be applied to capacitors used in MOS integrated circuits and bipolar integrated circuits. The present invention can be used in general semiconductor integrated circuit devices that require a capacitor with a relatively large capacity.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an example of a read circuit in a static RAM as an example of using the gate capacitor of the present invention. FIG. 2 is a sectional view showing an example of the structure of the gate capacitor according to the present invention. FIGS. 3(a) to 3(d) are structural explanatory diagrams showing the manufacturing process of the gate capacitor of the present invention. FIG. 4 is a diagram showing the internal circuit of a static RAM developed by the applicant one year before the present invention. It is. 1... Semiconductor substrate, 2... High concentration buried layer (N
+ type buried layer), 3... isolation region, 4...
...Low concentration semiconductor region (N-type well region), 5...
・P-type well region, 6...high concentration semiconductor region (N+
type semiconductor region), 7... field oxide film, 8...
...Insulating film (gate oxide film), 9...Conductive layer (gate electrode), C...Noise propagation capacitor.

Claims (1)

[Claims] 1. A low concentration semiconductor region of the same conductivity type as the buried layer is formed on the main surface of the semiconductor substrate via a high concentration buried layer of a conductivity type different from that of the substrate. A conductive layer is formed on the surface of this low concentration semiconductor region via an insulating film, and a high concentration semiconductor region that reaches the buried layer from the surface of the low concentration semiconductor region is formed in a part of the low concentration semiconductor region. 1. A semiconductor integrated circuit device, wherein a capacitance between the conductive layer and the low concentration semiconductor region is used as a capacitor. 2. The insulating film and the conductive layer thereon are formed at the same time as the gate insulating film and gate electrode of an insulated gate field effect transistor formed on the same semiconductor substrate. A semiconductor integrated circuit device according to claim 1. 3. Claim 2, wherein the low concentration semiconductor region is a semiconductor region formed at the same time as a well region in which an insulated gate field effect transistor is formed.
The semiconductor integrated circuit device described in . 4. The above-mentioned high-concentration buried layer and high-concentration semiconductor region are semiconductor regions formed at the same time as the collector region of the vertical bipolar transistor and the semiconductor region serving as the collector pull-up port, which are formed on the same semiconductor substrate. A semiconductor integrated circuit device according to claim 1, 2, or 3. 5. A differential input stage to which a pair of complementary data lines connected to the input/output terminals of the memory cell are connected via a switch means, and a pair of input differential transistors constituting this differential input stage on the collector side. In a semiconductor integrated circuit device comprising an amplifier circuit comprising a cascade stage having a pair of grounded base transistors connected to each other, between the base terminal of the grounded base transistor forming the cascade stage and the ground point of the circuit. A capacitor is connected, and a low concentration semiconductor region of the same conductivity type as this buried layer is formed on the main surface of the semiconductor substrate via a high concentration buried layer of a conductivity type different from that of this substrate. A conductive layer is formed on the surface of the low concentration semiconductor region via an insulating film, and a high concentration semiconductor region reaching the buried layer from the surface is formed in a part of the low concentration semiconductor region. 2. The semiconductor integrated circuit device according to claim 1, wherein a capacitance between the conductive layer and the lightly doped semiconductor region is used as the capacitor.