JPS61260476A - Optical disk drive device - Google Patents

Abstract

PURPOSE:To smooth the speed control of a linear actuator by causing a counter circuit to count a clock pulse from a reference clock pulse generator, outputting a digital signal having a reverse size from a memory circuit and permitting a digitalanalog converter to output a speed detecting signal. CONSTITUTION:At the time of accessing a track, track crossing optical information of an optical disk 1 is given to a photodetector 72 through an objective lens, etc., held by a tracking actuator 4. An addition amplifier 74 adds the output of the photodetector 72 to obtain the sum signal of the output of the photodetector 72, that is, an RF signal S1. When said signal S1 is inputted to a speed detecting circuit 54, the speed detecting signal S6 can be obtained and inputted to a speed curve generating circuit 55. Then the current of the coil 6 of the linear actuator 5 is controlled through a power amplifier 53, and accordingly the linear actuator 5 controls the optical head 3, that is, the moving speed of the light spot. Thus the linear actuator can be smoothly controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an original disk drive device having a linear actuator that drives an original head including a tracking actuator and an objective lens in the radial direction of the original disk, particularly when accessing a track. This invention relates to a speed detection circuit necessary for controlling the speed of a linear actuator.

[Conventional technology]

FIGS. 5 and 6 are circuit diagrams showing a control system and a speed detection circuit during track access of a conventional magnetic disk storage device, as shown in, for example, the Servo Technology Manual, Volume 2 (published by the New Technology Development Center).

In FIG. 5, 50 is the magnetic head%, 51 is a position detection circuit that creates a voltage proportional to positional deviation from the output obtained by the head 50, 52 is a voice coil that controls the speed of the magnetic head 50, and 53 is a power amplifier. , 54 is a speed detection circuit that detects the speed of the magnetic head 50 based on the current flowing through the voice coil 52 and the current obtained by the power amplifier 53 and the output of the position detection circuit 51. 55 is a speed detection circuit output from the speed detection circuit 54. 57 is a servo logic circuit that generates an operation signal for the voice coil 52 based on the output of the speed curve generation circuit 55; and 57 in FIG.
is a capacitor, 58 and 5g are resistors, 60 is an operational amplifier, 61 is composed of symbols 5T to 8Q, and the position detection circuit 5
62 is a non-inverting arithmetic circuit that outputs the output of the differential arithmetic circuit 61 with the same polarity; 63 is a non-inverting arithmetic circuit that inverts the polarity of the output of the differential arithmetic circuit 61; 64A is a switch for selecting the output of the non-inverting arithmetic circuit 62;
64B is a switch for selecting the output of the inverting arithmetic circuit 63, and 65 is an operational amplifier.

66 is a resistor for inputting the output of the non-inverting arithmetic circuit 62 or the inverting arithmetic circuit 63 to the operational amplifier 65;

6T is a resistor that inputs the linear motor current signal to the operational amplifier 65, 68 is a resistor that turns the operational amplifier 65 into a low-pass filter, and 6g is a capacitor that turns the operational amplifier 65 into an integrator. a switch for selecting whether the x amplifier 65 is a low-pass filter or an integrator;
71 is a resistor for adjusting the offset of the operational amplifier 65. Note that FIG. 7 shows operating waveforms of the speed detection circuit of FIG. 6.

Further, FIG. 8 shows the original sensor signal circuit of a conventional original disk drive device disclosed in, for example, Japanese Patent Application Laid-Open No. 52-134704. FIG. 9 shows operating waveforms of the circuit shown in FIG. wi8. In the figure, T2 is a photodetector that receives the original spot obtained through the tracking actuator, T3 is a subtraction amplifier circuit that outputs a difference signal (hereinafter referred to as a tracking error signal) of each output of photodetector T2, and 74 is a photodetector. This is a summing amplifier that outputs a sum signal (hereinafter referred to as a sum signal) of each output of the amplifier T2.

Next, the operation will be explained. When accessing a track, a conventional magnetic disk drive first applies a servo signal obtained from the magnetic head 50 to the position detection circuit 51, and the voltage corresponding to one position shift (hereinafter referred to as position signal 820) is applied to the position detection circuit 51. ). This position signal 82
G and a signal detected from the power amplifier 53 as a current signal flowing through the voice coil 52 are input to the speed detection circuit 54, and a voltage corresponding to the speed (hereinafter, speed detection signal 828) is input to the speed detection circuit 54.
) is created. This speed detection signal 82B is input to the speed curve generation circuit 55 and converted into a target speed voltage for moving the magnetic head 50.

This speed voltage is supplied to the power amplifier 53 via the servo logic circuit 56. Since current for acceleration or deceleration is supplied from the output of the power amplifier 53 to the voice coil 52, a target track can be accessed while controlling the moving speed of the magnetic head 50.

Furthermore, the operation of the speed detection circuit 54 shown in FIG. 6 will be explained. The position signal 820 is sent to terminal a of the speed detection circuit 54,
A voice coil current signal 823 is input to a terminal of the speed detection circuit 54. Here, the nonlinear part and the linear part of the 1 position signal 820 are divided by the signal S22, and when the mode switching signal S22 is 1H level, the linear part of the position signal 820 is divided, and when the mode switching signal 822 is lL'' level, the linear part of the position signal 820 is divided by the signal S22. The nonlinear parts are shown below. First, in the linear part of the 1-position signal 820, the switch 70 is turned on at the 1H level of the mode switching signal S22, and the resistors 66 and 68, the capacitor 69, and the operational amplifier 65 function as a low-pass filter. The position signal 820 is input to the differential calculation circuit 61, and a speed signal is obtained at the output S21 of the differential calculation circuit 61.

This speed signal is input to a non-inverting amplifier 62 and an inverting amplifier 63.

When the polarity of the differential output 821 is l1EI, the signal S2
When the switch 64A is turned on by the lH level of the signal 826 indicating the positive polarity of 1, and when the polarity of the differential output S21 is 1 negative 1, the switch 64B is turned on by the 1H level of the signal 827, which is an inversion of the signal 826. A signal 825 is applied to the input of a low-pass filter circuit including an operational amplifier 65 and the like. On the other hand, when the 1-position signal 820 is in the nonlinear portion, the mode switching signal 822 becomes 1L level, so the switch 70 is turned off, and the resistor 66, capacitor 69, and operational amplifier 65 become an integrating circuit.

At this time, the current signal 823 of the voice coil 52 is input to the integrating circuit. Since the current in the voice coil 52 corresponds to carriage acceleration, a speed signal can be obtained by integrating this current. The signal S24 is the voice coil 52
shows the output of the integrated current. Therefore, the signal 82B can be obtained at the terminal C as a speed detection signal of the magnetic head 50.

Therefore, in magnetic disks, in the non-linear part of the position signal during track access, a speed signal is detected by integrating the current input corresponding to the carriage acceleration, and in the linear part of the position signal, the position signal is differentiated, and this is detected in the low frequency range. By removing noise with a filter and absorbing errors during integration, the carriage speed detection signal 828 is detected and sent to the speed detection circuit 54.
The output will be output.

Furthermore, it is a well-known fact that track access can be achieved even in the original disk drive using the method of a magnetic disk drive. In this case, instead of the carriage of the magnetic head 5G, it is necessary to control the speed of a tracking actuator that drives the objective lens and a linear actuator that drives the optical head including the objective lens. In FIG. 8, 72 is a two-part photodetector of the optical head, T3
is a differential amplifier 74 that takes the difference signal of the output of the photodetector 72;
is a summing amplifier that takes the sum of the outputs of the photodetectors 72. FIG. 9 shows a tracking error signal and a sum signal for the cross section of the original disk and the position of the original spot. This is a pit recorded by a person, and the depth of the pit is deeper than the depth of the guide groove 1A. As shown in FIG. 9, the position signal is a push-pull method tracking error signal 829 obtained as the difference signal of the photodetector T2 that receives the original spot obtained from the original disk 1, that is, the output of the differential amplifier 73. used. This tracking error signal 829 and the linear actuator current signal are input to the speed detection circuit 54, and the speed curve generation circuit 5
5. The coil current of the linear actuator is controlled via the servo logic circuit 56 and the power amplifier 53 to control the speed of the linear actuator. Note that 81 is the output of the summing amplifier T4.

[Problem that the invention seeks to solve]

Since the conventional source disk drive device is configured as described above, when a hole-punched optical disk is used as the source disk and track access is performed in the source disk drive device, data is recorded as shown in FIG. 9BK. Since the waveform of the tracking error signal S29 becomes almost zero in the portion where the tracking error signal S29 is detected, the output of the differentiating circuit of the speed detection circuit becomes zero, and the speed detection signal of the speed detection circuit becomes zero.

Unable to detect normal speed signal. Therefore, there are problems in that the speed of the linear actuator of the original disk drive cannot be smoothly controlled.

This invention was made to solve the above-mentioned problems, and when track accessing the original disk drive device, the speed of the original spot of the original disk can be detected normally even if the hole-drilling source disk is used. It is an object of the present invention to provide a disk drive device that can smoothly control the speed of, for example, a linear actuator using this speed detection signal.

[Means for solving problems]

The original disk drive device according to the present invention uses a comparator to perform photoelectric conversion of the optical head in order to obtain a speed detection signal that is the speed of a light spot of the optical head for drive control of the actuator that drives the optical head during track access. The signal is a rectangular wave signal, a counter circuit counts clock pulses from a reference clock pulse generator based on this rectangular wave signal, and a storage circuit outputs a digital signal with a magnitude opposite to this counted value. A digital-to-analog converter that converts a signal into an analog signal outputs a speed detection signal.

Further, in addition to the above-described configuration, another original disk drive device according to the present invention divides the output of the reference clock pulse generator into 1/N by a frequency dividing circuit, and divides the output of the digital-to-analog converter by an amplifier. The output is multiplied by IA, the output of the frequency dividing circuit is counted by selection of a selector switch, and the counted value is output as a speed detection signal via a storage circuit, a digital-to-analog converter, and an amplifier.

[Effect]

In the original disk drive device of the present invention, when accessing a track, the photoelectric conversion signal of the optical head is converted into a rectangular wave signal, a gate is opened by the rectangular wave signal, clock pulses are counted, and a digital signal having a magnitude opposite to this counted value is generated. The storage circuit outputs this digital signal, and this digital signal is converted into an analog signal by a digital-to-analog converter to obtain a speed detection signal.

In another original disk drive device according to the present invention, when the speed of the optical head is lower than a predetermined speed, that is, when the count value of the counter circuit is higher than the upper limit value, the interval between the rectangular wave signals becomes wider, and the gate opening time increases accordingly. Since the clock pulse is long, the Glock pulse is divided into 17N using a divide-by-1 circuit to produce a low-frequency clock pulse, and this low-frequency clock pulse is counted when the gate is opened.Based on this counted value, an analog signal is converted by a functional digital-to-analog converter. This analog signal is multiplied by 1/N by an amplifier to obtain a speed detection signal. Conversely, when the optical head reaches a predetermined speed or higher, i.e.
When the count value of the counter circuit is below the lower limit value, the counter circuit counts the clock pulses of the reference clock pulse generator, and based on this count value, a speed detection signal is obtained by the functional digital-to-analog converter. .

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is the original disk, 2 is a disk motor that rotates at high speed with the original disk 1 attached to its spindle, and 3
is a well-known source disk in which a source is emitted from a light source, an objective lens (not shown) is used to form a source spot on the source disk 1, and a photodetector 72 receives reflected light from the source disk 1. The optical head 4 for the apparatus is a tracking actuator of the optical head 3 for holding an objective lens (not shown) and tracking the original spot to be located at the center of the track of the original disk 1.

5 is a linear actuator for moving the optical head 3 in the radial direction of the original disk 1, 6 is a filter for the linear actuator, and 7 is an RF scratch signal input to the summing amplifier T4 to move the original disk 10 in the radial direction. This is a speed detection circuit that detects the speed of the optical head 3, that is, the original spot. Reference numerals 53, 55 and 56 are the same components as in the conventional device, and the output of the speed detection circuit T is connected to the speed curve generation circuit 55.
The signal is configured to be applied to the coil 6 via →servo logic circuit 56 →power amplifier 53.

Also, FIG. 2 is a detailed circuit diagram of the speed detection circuit 7.
In this figure, 11 is a comparator that receives the RF flaw signal from the summing amplifier T4, compares it with the reference level Vref, and outputs a gate signal for creating a digital signal, and 12 generates a pulse with a higher frequency than the RF flaw signal. 13 is an AND@ circuit that performs logical product of the outputs of the comparator 11 and the reference clock pulse generation circuit 12; 14 is a counter circuit that counts the pulse train of the output of the AND circuit 13; 15 is a counter circuit 14; A latch circuit 16 stores the output of the wrap circuit 15, a storage circuit 16 outputs speed data having a magnitude opposite to that of the data, and a digital circuit 17 converts the output data of the storage circuit 16 into an analog output. An analog (hereinafter referred to as D/A) converter; 18 is a reset command circuit that inputs the output of the comparator 11 and generates a reset pulse for initializing the output of the counter circuit 14; 19 inputs the output of the comparator 11; Each latch command circuit that generates a pulse for storing data of the counter circuit 14 in the latch circuit 15 is shown. Further, FIG. 3 shows operating waveforms of each part of the circuit of FIG. 2.

Next, the operation will be explained. In the source disk drive device shown in FIG. 1, at the time of track access, the track crossing source information of the source disk 1 is transmitted to the photodetector 7 via an objective lens (not shown) held in the tracking actuator 4, etc.
given to 2. The output of the photodetector 72 is added to the amplifier 74
By adding ↓, the sum signal of the output of the photodetector 72, the RF signal S1, is obtained. When this RF signal S1 is input to the speed detection circuit 54, a speed detection signal S6 is obtained. The speed detection signal S6 is sent to the speed curve generation circuit 55.
and the servo logic circuit 56. By controlling the current in the coil 6 of the linear actuator 5 via the power amplifier 53, the moving speed of the original head 3, that is, the original spot, by the linear actuator 5 is controlled.

In addition, in addition to the speed detection circuit shown in Fig. 2, terminals a and f
The comparator 11 inputs the RF signal S1 and compares it with a reference value Vref], thereby outputting a rectangular wave signal S2 as an output of the comparator 11. Comparator 1
1 and the reference clock pulse output outputted from the reference-based four clock pulse generation circuit 12, which is several times higher than the maximum frequency of the RF signal S1, by the AND circuit 13, the output of the AND circuit 13 is The signal S2 is 1H''
A signal S3 is obtained which is a signal of the reference Glock pulse that passes only at the level. On the other hand, when the output of the comparator 11 is input to the reset command circuit 18, a pulse signal S5 for resetting the counter 14 is generated before the counter 14 starts counting. Further, when the output of the comparator 11 is input to the latch command circuit 19, a pulse signal S4 for storing the output of the counter circuit 14 in the latch circuit 15 is generated after the count of the counter circuit 14 is completed. first,
The counter circuit 14 is reset by the output pulse signal S5 of the counter reset command circuit 18.

Next, the pulses appearing in the output signal S3 of the AND circuit 13 are counted by the counter circuit 14.

After the count of the counter circuit 14 is completed, the count result of the p counter circuit 14 is stored in the latch circuit 15 by the output pulse signal S4 of the latch command circuit 19. Latch circuit 15
When the output of is applied to the memory circuit 16, the memory circuit 1B becomes RF
A relationship inversely proportional to the period of the signal S1 (tsu!, !5RF
Since speed data having a relationship proportional to the frequency of the signal S1 is stored, speed data determined by this relationship is output from the storage circuit 16. D/A output of memory circuit 16
By inputting the signal to the converter 17, a speed detection signal S6 corresponding to the speed detection signal for the linear actuator is output from the D/A converter 17 to the output terminal C.

According to the circuit described above, when the original disk 1 for drilling is used, the sum signal of the one-source detector 72, that is, the RF signal S1, is the ninth
As shown in Figure B, R decreases in the recorded data section, but by appropriately setting the comparison value Vref of the comparator 11, R
Since the cycle of the F signal S1 can be detected, it is possible to output a stable speed detection signal S6 for the linear actuator 5 as described above.

Next, another embodiment of the present invention is shown in FIG.

4, 11 to 19 have exactly the same functions as in FIG. 2, and 20 outputs the output of the reference clock pulse generation circuit 12 to N
21 is an upper limit value detection circuit for detecting the upper limit value of the count of the counter circuit 14 from the output of the latch circuit 15. , 22 is a lower limit value detection circuit that detects the lower limit value of the count of the counter circuit 14 from the output of the latch circuit 15;
The amplifier % 24 which divides the output of the D/A converter 17 by N and outputs it selects either the output of the reference clock pulse generation circuit 12 or the output of the 1/2 division divider 20 and inputs it to the AND circuit 13. Toggle switch.

Reference numeral 25 denotes a changeover switch 26 for selecting either outputting the output of the converter 17 to the FF or outputting the output of the amplifier 23 for converting the output of the D/A converter 17 to 1/N.
2 shows a switching command circuit which outputs a signal for simultaneously switching the changeover switches 24 and 25 based on the outputs of the counting upper limit value detection circuit 21 and the counting lower limit value detection circuit 22. Further, FIG. 4B shows the operating state of the circuit of FIG. 4.

Next, the operation of this circuit will be explained. An RF flaw signal obtained during track access is applied to the input terminal, and the frequency of this RF flaw signal AC component provides an output proportional to the speed of the linear actuator 5, ie, the spot speed of the optical head 30. Assume that the frequency II [810 of the RF flaw signal AC component changes as shown in FIG. 4B. First, the speed of the light spot of the linear actuator 5, that is, the optical head 3 is high, the switching command signal S14 output from the switching command circuit 26 is 1L level, and the changeover switches 24 and 25 are each connected to the terminal d. Assume that In this case, the circuit shown in Figure 4 is Wc2
The circuit configuration is the same as that shown in the figure, and the output of the reference clock pulse generation circuit 12 is input as is to the AND circuit 13, and the RF
D/ as a speed detection signal proportional to the flaw signal frequency 810
Output signal 81B of A converter 17 is output to output terminal C. Next, as the speed of the linear actuator 5, that is, the original spot of the original head 30 gradually decreases, the speed signal output to the output terminal C also gradually decreases.

The width of the output signal of the comparator 11 gradually increases.
The count value S11 of the counter circuit 14 also increases. Count value S of counter circuit 14
11 exceeds the upper limit value (La level), the output signal 812 of the upper limit detection circuit 21 becomes 1H level, and this signal changes the output signal 14 of the switching command circuit 26 to 1H level. Therefore, the output signal 1 of the switching command circuit 26
When 4 has reached the irises Hw level, switch 2
4 and 25 are switched to the terminal e side, and the output of the 1/N frequency divider 20 is a signal obtained by dividing the frequency of the reference clock pulse by N and IK (if the frequency of the reference clock pulse is f, then f/
A pulse signal with a frequency of N) is input to the AND circuit 13. Therefore, when the reference clock pulse is selected as the clock for the output of the counter circuit 14, the count value of the comparison counter becomes 1/N.

This value is input to the latch circuit 15, and the memory circuit 16 outputs a value N times the normal speed data. Therefore, the output signal S14 of the switching command circuit 26 is 1H level, the changeover switch 25 is switched to the terminal e side, and the output signal S15 of the converter 17 is converted to 1/2 by the amplifier 23.
By lowering the gain to N, a speed detection signal 81B that is continuous with the data before switching is obtained. On the other hand, when the speed of the linear actuator 5, that is, the original spot of the optical head 3 gradually increases, the frequency of the AC component of the RF flaw signal becomes 8.
10 gradually increases, the width of the output signal of the comparator 11 gradually decreases, and the output of the counter circuit 14, that is, the count value also decreases. When the output of the counter circuit 14, that is, the count value, becomes less than the lower limit value (Lb level), the output signal S13 of the lower limit value detection circuit 22 becomes 1H level, so the output signal 814 of the switching command circuit 26 changes to IL level. . Therefore, the output signal S14 of the switching command circuit 26
is now 1L level, the changeover switches 24 and 25 are connected to the terminal d side, and the output of the reference Glock pulse generation circuit 12 is directly input to the AND circuit 13, and the output signal of the D/A converter 1T is S15 will be output as is.

Therefore, in the case of this embodiment, it is possible to increase the detection accuracy of the speed detection signal when the speed of the linear actuator 5, that is, the original spot of the optical head 3 becomes low, and it is possible to significantly improve the control performance. Become.

〔Effect of the invention〕

As described above, according to the present invention, the speed of the original spot with respect to the original disk is detected based on the photoelectric conversion signal of the photodetector, and the linear actuator is controlled based on this detection result, so that The speed of the linear actuator when the drive device accesses the track can be stably detected, and the linear actuator can be smoothly controlled based on this speed detection signal.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing a former disk drive device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a speed detection circuit of the former disk drive device according to an embodiment of the present invention, and FIG. 3 is a circuit diagram showing a speed detection circuit of the former disk drive device according to an embodiment of the present invention. An operation waveform diagram of a speed detection circuit according to an embodiment of
FIG. 4A is a circuit diagram showing a speed detection circuit according to another embodiment of the present invention, FIG. 4B is an operation waveform diagram of the speed detection circuit according to another embodiment of the invention (FIG. 4A), and FIG. Figure 6 is a configuration diagram of a conventional magnetic disk drive device, Figure 6 is a configuration diagram of a speed detection circuit of a conventional magnetic disk drive unit, Figure 7 is an operating waveform diagram of a conventional speed detection circuit, and Figure 8 is a diagram of a conventional speed detection circuit. Block diagram of the sensor signal generation circuit of the photodetector of the original disk drive device, No. 9
The figure shows an operating waveform diagram of a sensor signal generation circuit of a conventional photodetector. In the figure, 1 is the original disk and 2 is the original head. 4 is a tracking actuator, 5 is a linear actuator, 6 is a linear actuator drive coil, 7 is a speed detection circuit, 11 is a comparator, 12 is a reference clock pulse generation circuit, 13 is an AND circuit, 14 is a counter circuit, 15 is a latch circuit, 16 is a memory circuit, 1T is a D/A
Converter, 18 is a reset frequency divider circuit, 21 is an upper limit value detection circuit,
22 is a lower limit value detection circuit, 23 is a 1/N gain amplifier, 2
4, 25 is a changeover switch, 26 is a changeover command circuit, 53
is a power amplifier, 55 is a speed curve generation circuit, 56 is a servo logic circuit, 72 is a photodetector, and T4 is a summing amplifier. Note that the same reference numerals in each figure indicate the same or corresponding parts. Patent applicant Mitsubishi Electric Corporation Figure 2 Figure 3: S6 □ Figure 9 (A) (B) Procedural amendment (
(Spontaneous) 1. Indication of the incident Patent Application No. 1983-101440 2.
Name of the invention Optical disk drive device 3, Representative Moriya Shiki & Subject of amendment (1) Column for detailed explanation of the invention in the specification (2) Column 6 for a brief explanation of the drawings in the specification, Contents of correction (1) "Coil current" on page 11, line 3 of the specification is corrected to "voice coil 52 current." (2) “Width of output signal” on page 21, line 14 of the specification
Correct it to "period width of output signal". (3) "Width of the output signal" on the first line of page 23 of the specification is corrected to "period width of the output signal." (4) "2 indicates the optical head" on the third line of page 25 of the specification. ,” is replaced with “3
is an optical head,” and correct it. that's all

Claims (2)

[Claims] (1) An optical head is provided with a photodetector that forms a light spot on an optical disc having a large number of track grooves and receives reflected light from the optical disc, and when accessing a track of the optical disc, The photoelectric conversion signal of the photodetector is input to an optical disk drive device that detects the moving speed of the optical head and controls an actuator that moves the optical head in a radial direction of the optical disk based on the detected speed detection signal. a comparator that converts the signal into a rectangular wave signal; a reference clock pulse generation circuit that generates a reference clock pulse; and a gate circuit that opens a gate in response to the output of the comparator and outputs the clock pulse of the reference clock pulse generation circuit. , a counter circuit that counts pulses output from this gate circuit, and a storage circuit that inputs a count value output from this counter circuit and outputs a digital signal having a magnitude opposite to the magnitude of this count value; An optical disk drive apparatus comprising: a digital-to-analog converter that converts the digital signal output from the storage circuit into an analog signal as the speed detection signal. (2) an optical head having a photodetector for forming a light spot on an optical disk having a large number of track grooves and receiving reflected light from the optical disk; In an optical disk drive device that detects the moving speed of the head and controls an actuator that moves the optical head in the radial direction of the optical disk based on the detected speed detection signal, a photoelectric conversion signal output from the photodetector is detected. a comparator that inputs and outputs a rectangular wave signal; a reference clock pulse generation circuit that generates a reference clock pulse; a frequency divider circuit that divides the output of the reference clock pulse generation circuit into 1/N; a first selector switch for selecting and outputting the output of the pulse generation circuit or the output of the frequency dividing circuit; and an output selected by the first selector switch by opening a gate in accordance with the output of the comparator. A gate circuit that inputs and outputs pulses, a counter circuit that counts the pulses output from this gate circuit, and a digital counter that inputs the count value output from this counter circuit and has a magnitude opposite to that of the count value. A storage circuit that outputs a signal, a digital-analog converter that converts the digital signal from this storage circuit into an analog signal, and an output of the digital-analog converter
/N times the output, a second selector switch for selecting and outputting the output of the digital-to-analog converter or the output of the amplifier, and the count value output from the counter circuit. count detection means for detecting the upper and lower levels of the count value and switching both the first and second changeover switches according to the detection result; An optical disk drive device characterized in that the output selected by the second changeover switch is used as the speed detection signal.