JPS61260343A - Data processing system - Google Patents

Abstract

PURPOSE:To perform fast address conversion by adding a little hardware and to increase an input/output processor by providing a connecting device, a memory access processing request means, a memory access processing request means, the 1st bus, and the 2nd bus. CONSTITUTION:A central processor 1 performs processing corresponding to a received command. When access is attained in absolute mode wherein address conversion is not necessary, the central processor 1 sends out a received address to an address bus 10-1 as it is and the command is converted to format matching with a memory interface and outputted as command pulses 10-2, accessing a main storage device. Then, the input/output processor 3 fetches read data outputted from the main storage device to a data bus 10 10-3 in a read buffer register 3-7. At this time, a fetch instruction for the data is sent from the central processor 1 to the request control circuit 2-4 in the connecting device 2 and further sent to the memory access control part 3-3 of the input/ output processor 3 which makes the request, and the memory access control part 3-3 sends out a signal to the read buffer register 3-7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing system, and more particularly to a data processing system including a main memory, a central processing unit, and a plurality of input/output processing units.

[Conventional technology]

In a weighing machine system that employs a virtual memory method, addressing in a channel program consisting of a plurality of input/output commands is performed using logical addresses, while data transfer is performed using absolute addresses. Therefore, a conversion means for converting a logical address into an absolute address is required, and a channel dynamic address conversion (DAT; Dynam
ic Address Translation) method is generally adopted.

The following address conversion methods using channel DAT are known.

fil A method in which the input/output processing unit performs conversion while referring to control tables (segment tables, page tables, etc.) in the main memory, and does not require dedicated hardware.

(2) Address translation buffer y inside the input/output processing device
(TLB; Translation L
ookaside13uffer) method.

The 11+ method requires several memory accesses in one conversion process, and is therefore unsuitable for processing that requires high speed, such as data chain processing.

In addition, in the method (2) above, the hardware increases significantly and address translation buffers are present in multiple locations in the central processing unit and the input/output processing unit.
Means for ensuring content consistency is required, resulting in significant control complexity.

Therefore, in order to eliminate the above-mentioned drawbacks, a method has been devised in which memory access other than data transfer is requested to the central processing unit, and address translation is performed at high speed using an address translation buffer within the central processing unit.

For example, as shown in Japanese Unexamined Patent Publication No. 59-186023, a data processing system having a semi-independent type input/output processing unit that requests the central processing unit to perform memory access other than data transfer by the input/output processing unit is already known. It is.

In such a data processing system, when a plurality of input/output processing devices are connected due to expansion of the system scale, a configuration as shown in FIG. 3 or FIG. 4 is adopted. That is, as shown in FIG. 3, the main memory unit (MMU) 5-
Multiple central processing units ((C
PLIO and CPUI) 5-2 and 5-3 and multiple input/output processing devices 1m (IOPO and l0P1
) 5-4 and 5-5, and the corresponding central processing units and input/output processing units are connected to each other, or as shown in FIG. A central processing unit (CPU) 6-2 and a connection device (CBtJ) connected to this central processing unit 6-2 are connected to the common bus to which 6-1 is connected.
)6-3 respectively, and this connecting device 6
-3 has multiple input/output processing devices (IOPO and IO
P1) A configuration is adopted in which 6-4 and 6-5 are connected respectively.

[Problem that the invention seeks to solve]

However, the conventional data processing system shown in Figure 3
Since a plurality of central processing units and input/output processing units are used, the hardware increases and control between processors is required, making the control complicated.

Furthermore, in the conventional data processing system shown in FIG. 4, the number of interfaces for data transfer is narrowed down to one, and competition for memory requests occurs in two places.
There was a problem in that the transfer capacity of data transfer decreased.

[Means for solving problems]

The data processing system of the present invention includes a main storage device, a central processing unit connected to the main storage device via a first bus, a plurality of input/output processing devices, and a plurality of input/output processing devices connected to each of the plurality of input/output processing devices. In a data processing system having a plurality of input/output devices, a connection device connected to the central processing unit and the plurality of input/output processing devices, and for requesting the connection device to perform specific memory access processing other than data transfer. selects one of the specific memory access processing requests from the plurality of input/output processing devices and sends the selected request to the memory access processing request means provided in each of the plurality of input/output processing devices; memory access processing requesting means provided in the connection device to request the central processing unit; and the main storage device based on the specific memory access processing that the central processing unit performs in response to the request from the requesting means. transfers the information on the first bus outputted by and a plurality of second buses provided corresponding to each of the input/output processing devices.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing in detail the structure of an embodiment of the present invention, and FIG. 2 is a block diagram showing a simplified structure of this embodiment. Referring to FIG. 2, in this example,
One central processing unit (CPU) 1, one connection unit (CBU) 2 connected to this central processing unit 1, and a plurality of units (in this embodiment, 2 units) each connected to this connection unit 2.
input/output processing units (IOPO and l0PI) 3 and 4 of the input/output processing units (IOPO and l0PI), input/output units (not shown) connected to these input/output processing units 3 and 4, respectively, and the central processing unit via a common bus 10. 1 and a main memory unit (MMU) 7 connected to input/output processing units 3 and 4, respectively.

Referring to FIG. 1, the central processing unit 1 has an address bus 1.
0-L command bus 10-2 and data bus 1O-3
It is connected to a common bus lO consisting of.

The connection device 2 includes an address selector circuit 2-1, a command selector circuit 2-2, and a request selection circuit 2-3.
and a request control circuit 2-4.

The input/output processing device 3 also includes a microprogram control section 3-1, an arithmetic unit 3-2, a memory access control section (MAC) 3-3, and a command register (CMR) 3.
-4, logical address register (LAR) 3-5, write data buffer register (WB) 3-6, gate circuit 3-6a, read data buffer register (RB
) 3-7, data transfer section 3-9, and input/output boat section 3
-10. The input/output processing device 4 also has a similar configuration.

The address selector circuit 2-1 sets the address 1lf to the logical address register 3-5 of the input/output processing devices 3 and 4.
i3-5a and 4-5a, and is connected to the central processing unit 1 via the address Al24a, and selects one of the address information supplied from the input/output processing units 3 and 4 to It is supplied to the processing device 1.

The command selector circuit 2-2 is connected to the command registers 3-4 of the input/output processing units 3 and 4 via command lines 3-4a and 4-4a, respectively, and is connected to the central processing unit via a command line 2-28. 1. The central processing unit 1 selects one of the command information supplied from the input/output processing units 3 and 4 and supplies it to the central processing unit 1.

The request selection circuit 2-3 connects the request line 3-3 to the memory access control unit 3-3 of the input/output processing devices 3 and 4.
8 and 4-38 and accept lines 13-3b and 4-3b, respectively, and is connected to the central processing unit 1 via request &12-3a and accept line 2-3b. Further, this request selection circuit 2-3 is connected to the address selector circuit 2-1 and the command selector circuit 2-2, respectively.
-2 Instructs to select address information and command information supplied from either one of the input/output processing devices 3 and 4. Furthermore, the request selection circuit 2-3
It is also connected to the request control circuit 2-4, and instructs the control circuit 2-4 to supply the control information supplied from the central processing unit 1 to either one of the input/output processing units 3 and 4.

The request control circuit 2-4 is connected to the central processing unit l via a control line 2-30, and is also connected to the memory access control unit 3 of the input/output processing units 3 and 4 via control lines 3-30 and 4-3c. -3, respectively, and supply control information supplied from the central processing unit 1 to either one of the input/output processing units 3 and 4.

The microprogram control section 3-1 includes an arithmetic unit 3-
2. Memory access control unit 3-3, command register 3
-4, logical address register 3-5, write data buffer register 3-6, read data buffer register 3
-7 and data transfer unit 3-9 respectively, and input/output processing bag W3 or 4 is connected based on the microprogram.
Control the entire operation.

The arithmetic unit 3-2 includes an arithmetic unit and a register group, and generates a fixed address for the main memory 7 under the control of the microprogram control section 3-1, and stores this fixed address in the logical address register 3-5. supply

The memory access control unit 3-3 connects the request line 3-38
It is connected to the request selection circuit 2-3 via the accept line 3-3b and to the request control circuit 2-4 via the control line 3-3C.

The memory access control unit 3-3 also controls the gate circuit 3-3.
68, and controls the opening and closing of this gate circuit 3-68.

The command register 3-4 supplies command information to the command selector circuit 2-2 via the command line 3-43 under the control of the microprogram control section 3-1.

The logical address register 3-5 supplies address information to the address selector circuit 2-1 via the address line 3-58 under the control of the microprogram control section 3-1.

The write data buffer register 3-6 is connected to the internal bus 3-6.
11, the write data supplied from the data transfer unit 3-9 is temporarily stored, and this write data is transferred to the gate circuit 3-9.
68 and data bus 10-a via data bus 10-a.
-Supply to 3.

The read data buffer register 3-7 is connected to the data bus 1.
The read data supplied via 0-3 and 10-a is temporarily stored, and the read data is sent to the data transfer unit 3-9 via the internal bus 3-11.

The data transfer section 3-9 includes a microprogram control section 3-9.
1, data is transferred asynchronously to address bus 10-1, command bus 10-2, and data bus 10-3 of common bus 10 via bus 3-a consisting of address bus, command bus, and data bus. It inputs and outputs data directly to and from the common bus IO via the bus 3-a, and is also connected to the input/output port section 3-10.

The input/output boat section 3-10 has a plurality of input/output boats (five in this embodiment), and an input/output device (not shown) is connected to each boat.

Note that reference numeral 10-b indicates a data bus corresponding to the data bus 10-a connecting the data bus 1O-3 and the input/output processing device 4, and reference numeral 4-a indicates the data bus corresponding to the data bus 10-a connecting the data bus 10-3 and the input/output processing device 4. The buses corresponding to the bus 3-a connecting the two are shown.

Next, the operation of the data processing apparatus of this embodiment configured as described above will be explained.

First, the central processing unit 1 creates a channel program written in logical addresses in the main memory 7 (see Figure 2), and issues a "CNCT instruction 2."
By executing the command ", the central processing unit 1 instructs the input/output processing unit 3 or 4 to start an input/output operation via a dedicated line (not shown). At this time, the input/output processing unit 3 or 4 Which one to select is determined based on the IOP number included in a part of the header of the channel program.Here, the case where the input/output processing device 3 is selected will be explained.

The input/output processing unit 3 recognizes the activation instruction from the central processing unit 1 through the microprogram of the microprogram control unit 3-1. The input/output processing device 3 generates a fixed address in the main storage device 7 using the arithmetic unit 3-2 under the control of the microprogram and writes it into the logical address register 3 in order to read the channel program pointer indicating the start address of the channel program. -5, and also stores a command pattern according to the request (in this case, a command instructing absolute mode read access) in the command register 3-4. In response to completion of storing the address and command, the microprogram gives an instruction to the memory access control section 3-3. Based on this instruction, the memory access control unit 3-3 sends a memory access request to the connection device 2 via requests 8 & 3-3a, and at the same time sends a memory access request to the connection device 2 via requests 8 & 3-3a.
5 and the contents (address and command) of the command register 3-4 are sent to the connecting device 2 through the address klA 3-5a and the command line 3-48.

Request line 3-38 from memory access control unit 3-3
The memory access request sent through the connection device 2
The received request is input to a request selection circuit 2-3 located inside the input/output processing device 4, and is checked in this circuit 2-3 to see if there is a conflict with a request from another input/output processing device 4.

When the request selection circuit 2-3 accepts the memory access request, the request selection circuit 2-3 requests the central processing unit 1 to access the memory via the request line 2-38, and also requests the address selector circuit 2-3 to access the memory. 1 and the command selector circuit 2-2 select the address and command from the input/output processing device 3, and the address *
2-1a and the command line 2-28 to the central processing unit 1.

If the central processing unit 1 is able to accept the memory access request from the connection device 2, it returns an accept signal to the request selection circuit 2-3 via the accept gland 2-3b, and further sends the request selection circuit 2-3 to the request selection circuit 2-3. returns this accept signal to the input/output processing device 3 that is the source of the request, so that the input/output processing device 3 recognizes that the request has been accepted.

Next, the central processing unit 1 performs processing according to the received command, that is, if address translation is necessary,
The central processing unit 1 performs address translation by referring to the address translation buffer provided within the device 1. In this case, since the access is in the absolute mode that does not require address translation, the central processing unit 1 The receiver sends the received address as is to the address bus 10-1, and also converts the command into a format suitable for the memory interface (in this case, a read command) and sends it to the command bus 10-1.
-2, the main storage device 7 is accessed.

Subsequently, the input/output processing device 3 takes in the read data output from the main memory w7 onto the data bus 10-3 as a result of the above access into the read buffer register 3-7.
At this time, the data import instruction is sent from the central processing unit 1 to the request control circuit 2-4 in the connection device 2 via the control line 2-30, and is further sent to the request control circuit 2-4 of the input/output processing device 3 that is the request source. The data is sent to the memory access control unit 3-3. In response to this fetch instruction, the memory access control unit 3-3 reads a signal for receiving and taking data on the data bus 10-3 via a signal line (not shown).
7, the memory access is completed and the channel program pointer is stored in the read data buffer register 3-7.

Next, the input/output processing device 3 retrieves the first word of the channel program using the read pointer. Since the channel program pointer is written as a logical address, the next access process converts the logical address into an absolute address. Need to convert. Therefore, the microprogram sends a command including an address conversion request to the command register 3-4, and also transfers the contents of the read data buffer register 3-7 (channel program pointer) to the logical address register via the internal bus 3-11. Transferred to 3-5. Then, the memory access control unit 3
-3, a memory access request is sent.

The subsequent processing is performed in the same manner as described above, but the central processing unit 1 adds a step of converting the logical address received into an absolute address. As a result of the access by the central processing unit 1, the first word of the channel program is output onto the data bus 10-3, and the input/output processing unit 3 takes in the data in the same manner as described above.

Further, if the request from the input/output processing unit 3 is a write operation, the request is processed in the same procedure as described above, and the central processing unit 1 transfers the 7 address to the address bus 10 for accessing the main storage device 7. -1 and at the same time control Qln 2-
3c instructs the input/output processing device 3 to output the write data onto the data bus 10-3. This instruction is transmitted from the control circuit 2-4 to the memory access control unit 3-3 via the control line 3-30, and finally the contents of the write data buffer register 3-6 are output to the data bus 10-3. The data is written to the main storage device 7.

So far, the case where the input/output processing device 3 has been started has been described, but the operation is similar when the input/output processing device 4 is started.

In the above embodiment, the case where there are two input/output processing devices has been described, but it is clear that the present invention can be applied to a case where there are three or more input/output processing devices by slightly expanding the connecting devices.

〔Effect of the invention〕

As explained above, the present invention provides a common connection device for a plurality of input/output processing devices to control memory access processing other than data transfer occurring in the plurality of input/output processing devices, and also provides data transfer. By using a common bus directly connected to memory, multiple input/output processing units can share the address translation buffer in the central processing unit and perform high-speed address translation with a small amount of hardware. This has the effect of increasing the number of input/output processing devices without reducing the data transfer capacity.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram showing a simplified version of the data processing system shown in Fig. 1, and Figs. 3 and 4 show an example of a conventional data processing device. FIG. 3 is a block diagram showing each. In the figure, 1...Central processing unit, 2...Connection device, 2-1...Address selector circuit, 2-2
...Command selector circuit, 2-3...Request selection circuit, 2-4...Request control circuit, 2-38...Request line, 2-3b...Accept line, 2-3c...control line, 3.4...input/output processing device, 3-1...microprogram control section, 3-2
... Arithmetic unit, 3-3 ... Memory access control section, 3-4
... Command register, 3-5 ... Logical address register, 3-6 ... Write data buffer register, 3-6a ... Gate circuit, 3-7 ... Read data buffer register, 3
-9...data transfer unit, 3-10...input/output port unit, 7...main storage device, 10...common bus. Figure 2'1F13 Figure 4

Claims (1)

[Claims] A main storage device, a central processing unit connected to the main storage device via a first bus, a plurality of input/output processing devices, and a plurality of input/output processing devices respectively connected to the plurality of input/output processing devices. a data processing system having an input/output device, a connection device connected to the central processing unit and the plurality of input/output processing devices, and a connection device for requesting the connection device to perform specific memory access processing other than data transfer; a memory access processing request means provided in each of the plurality of input/output processing devices, and selecting one of the specific memory access processing requests from the plurality of input/output processing devices and transmitting the selected request to the central processing unit. a memory access processing requesting means provided in the connection device for requesting a processing device; and a memory access processing requesting means provided in the connection device for requesting a processing device; information on the first bus to be transferred to the corresponding input/output processing device, and information to be sent by the input/output processing device to the main storage device based on the specific memory access processing on the first bus. A data processing system comprising: a plurality of second buses provided corresponding to each of the input/output processing devices for data transfer to the input/output processing device.