JPS61259359A - Method of synchronous bus control - Google Patents

Abstract

PURPOSE:To attain hardware synchronization between modules in a high speed over the limit of assurance of simultaneous by the software management by using a start and a signal in operation to hand shake the measuring operation timing existing in each measuring module. CONSTITUTION:The measuring modules 101-10n are connected to a system bus (synchronous bus) 2 provided respectively with an READY transmission and reception circuit 11 transmitting and receiving an READY signal, a TRIG transmission and reception circuit 12 transmitting and receiving an inverted TRIG signal, a BUSY transmission and reception circuit 13 transmitting and receiving an inverted BUSY signal and an EOP circuit 14 transmitting and receiving an inverted EOP signal. For example, in transmitting the READY signal, the level of the bus goes to H at the end of external synchronization, the high level is kept during the synchronization and the level goes to L when a trailing edge of the inverted EOP or a command from a CPU1 is received. In receiving a signal, it is discriminated by the leading of the said signal for the transmission and reception enable state of the inverted TRIG, the inverted BUSY and the inverted EOP signal, and it is discriminated at the trailing synchronization end to bring the level of the inverted TRIG signal, the inverted BUSY and the inverted EOP signal to H level.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a synchronous bus control method for performing hardware synchronization between a plurality of measurement modules. (Prior art) Conventionally, in systems in which multiple measurement modules are connected, measurement sequence processing has been performed by software management on the main body side prepared to manage the operation of each measurement module. There is.

(Problem to be Solved by the Invention) However, with this kind of processing, there is a problem that measurement concurrency that is faster than the processing speed of the system software (language translation, system bus communication speed, etc.) cannot be ensured. Ta.

Furthermore, by combining measurement elements (for example, combining AD conversion and DA conversion), it is possible to ensure simultaneous measurement of multiple measurement modules, but this is limited in terms of system configuration flexibility. There were many cases and it was not practical.

In view of these points, it is an object of the present invention to perform hardware synchronization between modules at a high speed exceeding the limit of guaranteeing simultaneity by software management when performing measurements with multiple measurement modules ensuring simultaneity of measurement. The object of the present invention is to provide a synchronous bus control method that allows for the synchronous bus control.

(Means for solving the problem) In order to achieve such an object, the present invention synchronizes the measurement operation timings existing in each measurement module by handshaking with activation and operation signals, The present invention is characterized in that, based on a judgment on the measurement module side, a signal to stop measurement in a synchronous operation is used as an end timing and is notified to other measurement modules via a synchronous bus.

(Example) The present invention will be described in detail below using the drawings. FIG. 1 is an embodiment of a system for carrying out the method of the present invention. In the figure, 1 is the upper CPIJ.

2 is a system bus including a synchronous bus, 10+, 102~1
On is a measurement module. These multiple measurement modules are connected to the system bus in a similar manner.

Each measurement module includes a READY transmitting/receiving circuit 11 for transmitting and receiving a READY signal (positive logic), and a TRIG transmitting/receiving circuit 12 for transmitting and receiving a TRIG signal (negative logic).
, BtJS for transmitting and receiving BtJSY signals (negative logic)
A Y transmitting/receiving circuit 13 and an EOP transmitting/receiving circuit 14 for transmitting and receiving an E0100 signal (negative logic) are provided, and are connected to a synchronous bus.

READY signal, TRIG signal, BUSY signal and EO
The details of the P signal synchronization operation are as follows.

(+) When transmitting READY signal: (Sent by the module with the TRIG signal reception function specified.) ■When external synchronization operation preparation is complete, the signal becomes 11 F(", and the IF(1" state is maintained during the synchronization operation.

- Set to "L" at the falling edge of EOP or when receiving a command from the host CPU.

At the time of reception + (Received by the module designated with TRIG signal transmission function.) ■At the rising edge of this signal, it is determined that the TRIG signal, BLJSY signal, and EOP signal can be transmitted and received. .

■When this signal falls, it is determined that the external synchronization operation is complete, and the TRIG signal, BLIS master signal, and EO
Set the P signal to "H".

<2) When transmitting the TRIG signal (usually the pulse width is 5 oonsec or more): 1-Notifies the module receiving the RIG of the start of the measurement operation. Only one module transmits the TRIG signal during synchronous operation.

When receiving: Measurement operation starts at the falling edge of this signal.

(3) When sending BUS Y signal: ■ TRIG signal is sent by the module that receives the TRIG signal.
The signal is set to L'' within about 200 nsec from the fall of the G signal, and maintained at L during the measurement operation.

■Module that receives TRIG signal When the measurement operation is completed, it is set as "I-1".

When receiving: Only one module receives the BtJSY signal during synchronous operation.

■Module that transmits TRIG signal At this point, transmission of the rfflTRIG signal of L'' is interrupted.

■Module that transmits TRIG signal TRIG multiplied signal 1 pulse output at do.

(4) E OP signal (signal with a pulse width of approximately 500 nsec or less generated due to data abnormality in the measurement module) At the time of transmission: - In the module that transmits the TRIG signal, it is output when the BLJSY signal is "HIt".

■The module that receives the TRIG signal outputs it within about 200 nsec from the rising edge of BUSY signal.When receiving: At the falling edge of this signal, the READY signal is set to “L”.
shall be.

The input/output terminals of each circuit for transmitting and receiving such signals are constructed as shown in FIG. In other words, READY
, TRIG, BIJSY, EOPf7) signal transmitting/receiving circuits, at their input/output terminals, the input signal is sent to the buffer BL.
(=-1 to 4), and the output signal is output at the Nant gate Gl (J-1 to 4) of the oven collector. These inputs and outputs are commonly connected, and +
It is pulled up to 5 volts and resistor R2z (L=1
~4) to the common line and to each signal line of the synchronous bus.

The operation in such a configuration will be explained next with reference to the time chart of FIG.

1) Let us take as an example the case where there are three time measurement modules. When each measurement module 10+, 102, and 103 completes their synchronous operation preparations in response to a command from the host CPU 1, they receive a READY signal (
output) to 'H'.

2) The READY signal at point ■ is the AN of the READY output of each module.
II Hlj under condition D (because an open collector is used to output each synchronous bus signal).

In other words, the READY signal appearing on the synchronous bus is "'H".
'' is determined by the module with the slowest preparation time in 1) above! 3) RE to all time measurement modules 10+ and 102 and 103 in ■
Notify that the ADY signal is H'°.

Module 10. starts the measurement operation for generating the TR[G signal. The measurement operation here refers to some functional operation built into the module 10+.

4) When the point measurement module 10+ of ■ completes its measurement operation, T
Activate RIG signal output.

5) At point 1' of ■, the RI G signal is output to the bus, and the measurement module 1
0+, notify 102.103.

The time measurement modules 102 and 103 of 6>■ each independently set the BUSY signal to "L II" and output the BUSY signal to the bus 2. The measurement modules 102 and 103 activate each measurement operation.

7) The time measurement module 103 of (2) recognizes that the BUSY signal is L'' and prohibits the next TRIG signal output.

8) The time measurement module 102.10z of ■ completes the measurement operation, and
Set the tJSY signal to “H”.

9) The BUSY signal at point ■ is the AN of the BUSY signal output of each module.
Under D condition, Hn is obtained.

10〉[Phase] time measurement module 10+ has input BUSY signal °H
'', a measurement operation is started to generate the next RIG signal.

As described above, the operations 4) to 10) are repeated.

11) Time point 0 Assume that the EOP requirement is established in the module 101 and the EOP signal is output.

12) Notify the measurement modules 101, 102 and 103 of the EOP signal at time 0.

13) Measurement modules 101 and 102 that received the EOP signal at time point (■).
103 sets the READY signal to "L". This causes the measurement operations of all measurement modules to stop.

(Effects of the Invention) As described above, according to the present invention, each of the plurality of measurement modules performs a synchronous operation by handshaking the timings of four signals of the synchronous bus, that is, the READY signal and the TR, using hardware. This makes it possible to ensure measurement simultaneity that is faster than the processing speed of system software such as language translation and system bus communication.

Additionally, the flexibility of the system configuration is no longer limited by the ability to perform high-speed simultaneous measurements with multiple modules without composing measurement elements.

[Brief explanation of drawings]

FIG. 1 shows the method of the present invention in practice! FIG. 2 is a diagram showing the circuit configuration of the signal input/output end of the measurement module, and FIG. 3 is a time chart for explaining the operation. 1...CPU12...System bus, 10+, 10
2~10n...Measurement module, 11...READ
Y transmitting/receiving circuit, 12...TRIG transmitting/receiving circuit, 13.
...BUSY transmitting/receiving circuit, 14...EOP transmitting/receiving circuit.

Claims (1)

[Claims] In a bus system in which a plurality of measurement modules are connected to an upper CPU via a synchronization bus, the measurement operation timings existing in the individual measurement modules are synchronized by handshaking with activation and operation signals,
A synchronous bus control method in which a measurement stop signal in a synchronous operation is determined by a measurement module and is used as an end timing to notify other measurement modules via a synchronous bus.