JPS61259334A - Data transferring system - Google Patents

Abstract

PURPOSE:To improve processing efficiency by executing immediately a transferring processing in case of the bit error of an ID part which can be corrected by ECC. CONSTITUTION:When the data for one sector are transferred from a disk device to a disk control device 1 are transferred, the data of the ID part (a) are applied to an ECC circuit 71 for ID, even when the bit error is detected, the data of a data part (b) corresponding to the IDa are continuously transferred as they are, and applied to an ECC circuit 72 for the data part (b). During the time, the error of the ID part (a) is analyzed, can be corrected by the correcting ability held by an ECC part 7, the data are transferred to the calculating system and the processing of the next selector can be continuously executed.

Description

[Detailed Description of the Invention] [Summary] In a data transfer method, when a bit error occurs in the identifier section, processing of the sector is stopped and bit error analysis/correction processing is performed. Correspondingly, E.C.
In the case of a bit error that can be corrected in the C section, the sector processing is continued to be performed, thereby making it possible to improve the processing efficiency of data writing/reading.

[Industrial application field]

The present invention relates to a data transfer method that continues sector processing when a bit error that can be corrected with an error correction code occurs in an identifier section.

As the usage of information processing systems becomes more sophisticated and complex, the amount of data handled has become enormous, and in order to quickly process this huge amount of data, there has been a growing demand for faster processing speeds. .

One way to deal with this request is to improve efficiency even a little, for example when performing data write/read processing.

[Prior Art and Problems to be Solved by the Invention] As a prior art, data writing/reading control for a disk device by a disk control device will be explained as an example.

FIG. 4 is a block diagram illustrating the prior art, and FIG. 5 is a data transfer status diagram in the prior art.

The block diagram in FIG. 4 shows a part of a conventional disk control device, including an interface control circuit 2 that controls the interface with a host computer system (not shown), and a host computer system (not shown). a buffer register 3 for storing data transferred from the computer or for storing data transferred to a host computing system (not shown);
, a gate 3a serving as a gate for exiting to data bus a for transporting data to a host computing system (not shown), and a gate for exiting to data bus b for transporting data to a disk device (not shown). A gate 8b serving as a gate, and a serial/parallel converter 4 that converts parallel data to serial data and serial data to parallel data.
, an ECC circuit 5 that detects bit errors in the identifier section (hereinafter referred to as ID section) and data section of each sector and corrects them within its capabilities; and ECC analysis control that controls error analysis in the ECC circuit 5. It consists of a circuit 6 and a formant control circuit 8 that controls writing/reading of data format (sector format in this example) on a disk device (not shown).

For example, when the disk controller 1 controls reading of one sector (1) as shown in FIG. 5, the data read by the disk device (not shown) is serially/ It is transferred to the parallel converter 4. It is assumed that each sector has an ID section (a) at the beginning and a data section (b) after that, and an ECC is recorded in the last section of the 10th section (a) and the data section (b), respectively. .

The ECC circuit 5 detects the presence or absence of a bit error in the sector (1) based on the format data of the sector (1) read out by the formant control circuit 8 and the ECC.

In addition, ■ is a write gate signal, ■ is a read gate signal, ■ is a clock signal, ■ is an ID part (a) signal, and ■ is a data part (bl (f number), respectively.

On the other hand, in the serial/parallel converter 4, the clock signal ■
The transferred serial data is converted into parallel data and sent to data bus b. At this time, gate 3b opens and this data is stored in buffer register 3.

Next, under the control of the interface control circuit 2, the gate 3a
, and transfers the data stored in the Banofa register 3 to an upper host computing system (not shown).

During the above series of operations, if a bit error is detected when the data of the third 10 part (a) is applied to the ECC circuit 5 as shown in FIG. Then, according to instructions from a predetermined circuit (not shown), the ECC analysis control circuit 6 causes the ECC circuit 5 to analyze the bit error, and if it is possible to correct it with the ability of the ECC circuit 5, corrects it, and stores the corrected data. It is sent to the serial/parallel converter 4.

After the above processing is performed, the data section (bl) is read out after one rotation of the disk medium (not shown).

In addition, FIG. 5 shows the above-mentioned data transfer situation, and "1" indicates the data part (bl) to the host computing system (not shown).
"4" is the data read status of each sector from the disk device (not shown), "5" is the error data check status, and DT is the data section of sector N (b
) data, (DT + 1) indicates the data section (bl data, etc.) of sector (N+1). If the bit error in the ID section (al) is detected as a bit error exceeding the correction ability of the ECC circuit If so, the error data is transferred to the host computing system (not shown) via the interface control circuit 2, and the host computing system (not shown) executes an error handling routine.

As described above, even if the bit error in the 10th part (a) can be corrected with the ability of the ECC circuit 5, the reading process of the data part (b) is performed after one rotation of the disk medium (not shown), so the disk There is a problem in that the data transfer process is stopped while waiting for one rotation of the medium (not shown).

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention.

Figure 1 shows the serial/parallel converter 4 explained in Figure 4.
．． l1ICC analysis control circuit6. Former 7) Control circuit 8
, a buffer section 30.31 for storing data of two sectors worth of data section (b), and an ECC section 7 having an ECC processing function for 10 sections (al and data section (b)). There is.

[Effect]

From the disk device (not shown) to the disk controller 1
The host computing system (not shown) has a buffer that stores two sectors of data to be transferred to the host computer system (not shown).
Data is transferred one sector later than the sector transferred from the disk device (not shown).

Therefore, when data for one sector is transferred from the disk unit W (not shown), even if a bit error is detected in the ID part (a), the data corresponding to the ID part (a) The data in section (b) continues to be transferred as is and is applied to the ECC processing function for data section ('b).

During this time, the error in the ID section (a) is analyzed and the ECC section 7
If the data can be corrected using its correction capability, the corresponding data can be transferred to a host computing system (not shown) and the next sector can be processed continuously.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 and 3.

FIG. 2 is a block diagram explaining the present invention in detail, and FIG. 3 is a data transfer status diagram according to the present invention. Note that the same reference numerals refer to the same objects throughout the plan.

Also, "1" shown in FIG. 3 is the timing of data transfer to the host computing system (not shown), "2" is the time to store data in the buffer register 30a, and "3" is the time to store data in the buffer register 31a. Storage time, “4”
"5" indicates the data transfer time from sector (1) to the disk control value w1, and "5" indicates the ECC analysis timing.

Furthermore, rDTJ is sector N, rDT+IJ is sector (
N+1), rDT+2 J is sector (N+2),
rDT+3 J indicates the sector (N+3), and ror+4J indicates the data of the sector (N+4) notator section (bl).

Next, the operation of this embodiment will be explained based on FIG.

The disk control device 1 receives a read command from an upper host computer system (not shown).
(not shown) to read the Nth sector (1) and transfer the read data. Of the transferred read data, 10 copies (a) data is for ID E.
The CC circuit 71 is applied to detect bit errors.

On the other hand, the data DT in the data section (bl) is applied to the data ECC circuit 72 to detect bit errors, and the serial/
The data is stored in the buffer register 30a via the parallel converter 4. In addition, the actions of game) 3a and 3b at this time are the 4th
It is the same as the one explained in the figure and performs the same operation.

When the transfer of the first sector (1) is completed, the next sector (
The data (DT +1) of 1) is transferred in the same manner and starts being stored in the buffer register 31a. At the same time, the data DT stored in the buffer register 30a
is transferred to a host computing system (not shown) under the control of interface control circuit 2.

The same operation as above is repeated until, for example, the data of the fourth sector (1) is transferred and the IDJflECC
If a bit error is detected when the circuit 71 is applied, the ECC analysis control circuit 6 controls the ECC analysis of the ID ECC circuit 71 under instructions from a circuit not shown.

Note that the format control circuit 8 performs the same operation as explained in FIG.

Next, the data (DT + 3
) is applied to the data ECC circuit 72 and stored in the buffer register 31a. During this time, the ECC analysis is completed, and if this bit error can be corrected with the correction ability of the ID ECC circuit 71, the correction process is performed immediately, and it becomes possible to accept the data transfer of the next sector (1), and continue the data transfer. (DT + 4) processing is performed.

If the correction cannot be corrected with the correction capability of the IDJ11 IECC circuit 71, the data transfer process will be immediately stopped, this will be reported to the host computing system (not shown), and the host computing system (not shown) will detect the error. Execute processing routines.

〔Effect of the invention〕

According to the present invention as described above, an ID that can be corrected by ECC
If there is a bit error in the data section, data transfer in the data section can be performed immediately without waiting for rotation of the disk medium, and data writing/reading operations can be efficiently processed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a data transfer status diagram according to the present invention, and FIG. 4 is a block diagram explaining the prior art. FIG. 5 shows data transfer status diagrams in the prior art. 2 and 4, 1 is a disk control device, 2 is an interface control circuit, 3, 30a, 31a are buffer registers, 3a, 3b are gates, 30.31 is a buffer section, 4 is a serial/
Parallel converter, 5 is ECC circuit, 6 is ECC analysis control circuit, 7
is the ECC section, 71 is the ECC circuit for the ID section, 72
is the ECC circuit for the data section; 8 is the format control circuit; 1 '45 Figure

Claims (1)

[Scope of Claims] A device (1) for controlling data writing/reading operations of a disk device having a sector format consisting of an identifier part and a data part, comprising a buffer part (3) for storing data in each sector.
0, 31) and an ECC section (7) that detects and corrects bit errors in the identifier section and the data section in the sector, and detects and corrects bit errors in the identifier section. If detected, the sector processing continues and the detected bit error is analyzed by the ECC analysis control circuit (6), and when the bit error analysis result can be corrected by the ECC unit (7), A data transfer method characterized in that the next sector processing is also continuously processed.