JPS61258400A - Nonvolatile semiconductor storage device - Google Patents

Nonvolatile semiconductor storage device

Info

Publication number
JPS61258400A
JPS61258400A JP60100759A JP10075985A JPS61258400A JP S61258400 A JPS61258400 A JP S61258400A JP 60100759 A JP60100759 A JP 60100759A JP 10075985 A JP10075985 A JP 10075985A JP S61258400 A JPS61258400 A JP S61258400A
Authority
JP
Japan
Prior art keywords
voltage
power supply
memory cell
current
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60100759A
Other languages
Japanese (ja)
Inventor
Masanori Kobayashi
正典 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP60100759A priority Critical patent/JPS61258400A/en
Publication of JPS61258400A publication Critical patent/JPS61258400A/en
Pending legal-status Critical Current

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  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE:To measure directly the transistor characteristics of a memory cell obtained after writing, by using a control circuit which applied the voltage of a program power supply system to a word line of the memory cell and can select only the current supplied to the memory cell to flow it to a power supply and then setting a control mode for said control circuit. CONSTITUTION:For a control circuit having the circuit constitution where three memories are selected by an EPROM, a signal 12 is set at a high level with a signal 8 turned off respectively. Thus no current is flowed from a program power supply. While a signal 14 is set at a low level and it is possible to supply the voltage that can cover a voltage range required to obtain the voltage Vth through V-I measurement to a node 9 since a transistor 6 is depressed. Then no current flows to other circuits on a CD basis owing to CMOS. Therefore, the above-mentioned state is set for measurement of the program power supply voltage and the current flowed from a lead power supply to secure square characteristics. Then voltage/current characteristics can be obtained as shown in the diagram. As a result, the voltage Vthp can be measured directly after programming of the EPROM with high reproducibility and high accuracy within 0.1V.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、内部メモリーをプログラムした後、その内部
メモリセルの書込み後のしきい値電圧(以後Vthp 
 と称す)の測定を可能にした不揮発性半道伏紀惜鉢情
(Di下EFROMと称す)に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a method for programming an internal memory and then determining the post-program threshold voltage (hereinafter referred to as Vthp) of the internal memory cell.
The present invention relates to a non-volatile semi-difficult memory (referred to as Di EFROM) that has made it possible to measure EFROM.

〔発明の概要〕[Summary of the invention]

本発明はMPROMのメモリセルにデーターを書込んだ
後、書込み後のvth  を測定する手段において、書
込んだメモリセル以外に電流が流れないようにし、かつ
ワードラインに高電圧をかけ、書込まれ高い値となった
Vthpを、外部端子から電圧−電流を測定することに
よって正確に直接的に測定できるようにしたものである
In the present invention, after writing data to a memory cell of an MPROM, in the means for measuring vth after writing, current does not flow to any other than the written memory cell, and a high voltage is applied to the word line. This allows Vthp, which rarely reaches a high value, to be accurately and directly measured by measuring voltage-current from an external terminal.

〔従来の技術〕[Conventional technology]

従来、EPROMでは、プログラム後のメモリセルのv
th  を正確に測定することが、EFROMの良品選
別、または信頼性試験等において重要とされている。こ
れまでに、EPROMのプログラム後のvth  を測
定する有力な手段として、最大動作電圧(以下VCCm
aXと称す)を測定し、そのVccmaxを曹込み後の
vth に換算する方法が知られている。ここで、書込
み後のメモリセルがそのvth が8〜10V以上とな
り、5vで使用する際に、ワードラインの電圧が5v以
下であることからメモリセルはON状態にならない。し
たがってvth  を上げることによってメモリのデー
タを決定するわけである。
Conventionally, in EPROM, v of a memory cell after programming is
Accurately measuring th is considered important in selecting non-defective EFROMs or in reliability tests. Until now, maximum operating voltage (hereinafter referred to as VCCm
There is a known method of measuring Vccmax (referred to as aX) and converting the measured Vccmax to vth after cooling. Here, when the vth of the memory cell after writing becomes 8 to 10 V or higher and is used at 5 V, the memory cell does not turn on because the word line voltage is 5 V or lower. Therefore, the memory data is determined by increasing vth.

動作電圧を上げるとワードラインの電圧は上り、たとえ
ばメモリセルのvth が8vまで上りているとすると
動作電圧を8v以上に上げればメモリセルはON状態と
なり、メモリのデータは逆転することになる。データが
逆転することにより、動作電圧を8v以上上げるとlP
ROMのデータ読み出しは誤動作となる。したがって最
大動作電圧によってメモリセルがON状態となる電圧、
すなわち書込み後のvth  を知ることができる。
When the operating voltage is increased, the word line voltage increases. For example, if the vth of the memory cell has risen to 8V, if the operating voltage is increased above 8V, the memory cell will be turned on and the data in the memory will be reversed. If the operating voltage is increased by 8V or more due to data inversion, lP
Reading data from the ROM will result in a malfunction. Therefore, the voltage at which the memory cell is turned on at the maximum operating voltage,
That is, it is possible to know vth after writing.

〔発明が解決しようとする問題点及び目的〕しかし、従
来のVccmazを換算して書込み後のvth  を求
める方法は、V(jCInaXをvth  に換算する
際に伴う、回路条件の設定誤差を含んでいる。t タv
ccmaXはセンスアンプ系を介して判断することから
、メモリセルかON状態となる時に、センスアンプ系で
のわずかな充電電荷の有無によってその精度はα5V以
内にしぼりこむことは困難である。さらに動作電圧はリ
ード電源系であるので耐圧が10〜12V近辺であるの
で、vthがICM7近くのときは測定できなくなる。
[Problems and Objectives to be Solved by the Invention] However, the conventional method of calculating Vth after writing by converting Vccmaz is There is. t ta v
Since ccmaX is determined via the sense amplifier system, it is difficult to narrow down its accuracy to within α5V depending on the presence or absence of a slight charge in the sense amplifier system when the memory cell is turned on. Furthermore, since the operating voltage is a lead power supply system, the withstand voltage is around 10 to 12 V, so it becomes impossible to measure when vth is close to ICM7.

従来技術ではこのような問題点をかかえている。そこで
、本発明は従来のこのような問題点を解決するために、
誉込み後のメモリセルのトランジスタ41を直接測定し
、二側カーブよりメモリセルのVthpを直接、かつ正
確に、また高いvthpをも測定可能にすることを目的
としている。
The conventional technology has such problems. Therefore, in order to solve these conventional problems, the present invention has the following features:
The purpose of this method is to directly measure the transistor 41 of the memory cell after it has been assembled, and to directly and accurately measure the Vthp of the memory cell from the two-sided curve, and also to make it possible to measure even high vthp.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点を解決するためにメモリセルのしきい値電圧
を上げてデータを記憶させる不揮発性半導体記憶装置に
おいて、メモリセルのワードラインにプログラム電源系
の電圧をかけ、電源に流れる電流をメモリセルに流れる
電流だけにできる制御回路と前記制御回路を制御するモ
ードを設定したことを特徴とする。
In order to solve the above problems, in a nonvolatile semiconductor memory device that stores data by increasing the threshold voltage of the memory cell, a program power supply system voltage is applied to the word line of the memory cell, and the current flowing through the power supply is applied to the memory cell word line. The present invention is characterized in that a control circuit that allows only current to flow in the control circuit and a mode for controlling the control circuit are set.

〔作用〕[Effect]

上記のように構成されたKFROMにおいては端子をプ
ログラム状態に設定し、誓込みデータを71としてプロ
グラム電源電圧とリード電源に流れるリード電流を測定
し二側特性をとると、直接、選択されたメモリセルの書
込み後のVthpを測定スることができ、かつプログラ
ム電源は高耐圧なので高いVthp  まで測定が可能
である。
In the KFROM configured as above, if the terminal is set to the program state and the pledge data is 71, the program power supply voltage and the read current flowing to the read power supply are measured and the two-side characteristics are taken, it is possible to directly select the selected memory. It is possible to measure Vthp after writing to the cell, and since the program power supply has a high withstand voltage, it is possible to measure up to a high Vthp.

〔実施例〕〔Example〕

以下に実施例に添って本発明を説明する。j1!1図は
本発明の一実施例を示す。1はプログラム電源、2はリ
ード電源、3は]]’AMOSメモリセル、4,5はN
ch  )ランジスタ、6はNch  デプレショント
ランジスタ、7.8はpch  )ランジスタを示す。
The present invention will be explained below with reference to Examples. Figure j1!1 shows an embodiment of the present invention. 1 is a program power supply, 2 is a read power supply, 3 is ]]'AMOS memory cell, 4 and 5 are N
6 indicates an Nch depletion transistor, and 7.8 indicates a pch) transistor.

9はノードで10.11..12゜13.14は信号ラ
インを示す。ここでlPROMにおいて選択されたメモ
リを3とする、第1図に示す回路構成による制御回路を
本発明モードの1例に設定すると、第1図において12
の信号はHlghとなり、8はOFFする。これにより
てプログラム電源からは電流は流れない。また、14の
信号をLoとするが、6のトランジスタはデグレシ目ン
であるのでノード9に■−工測測定よってvth  を
求めるのに必要な電圧範囲をカバーできる電圧を供給す
ることができる。他の回路には0MO3であることから
Do的には電流が流れない。したがって、前記状態に設
定してプログラム電源電圧とリード電源より流れる電流
を測定し二側特性にすると第2図のような電圧電流特性
が得られる。第2図において直線のX軸へのインターセ
プトポイントがプログラム後のvth  となるこの測
定によれば、良い再現性とQ、1v以下の精度か得られ
る。また、20v以上の7thpの測定も可能である。
9 is the node 10.11. .. 12°13.14 indicate signal lines. Here, if the control circuit with the circuit configuration shown in FIG. 1 is set as an example of the mode of the present invention in which the memory selected in the lPROM is 3, in FIG.
The signal becomes Hlgh, and the signal 8 turns OFF. As a result, no current flows from the program power supply. Further, the signal at 14 is set to Lo, but since the transistor at 6 is a degreaser, it is possible to supply a voltage to node 9 that can cover the voltage range necessary to obtain vth by means of -2-constructive measurement. Since the current is 0MO3 in other circuits, no current flows in the other circuits. Therefore, when the above state is set and the current flowing from the program power supply voltage and the read power supply is measured and two-sided characteristics are obtained, voltage-current characteristics as shown in FIG. 2 are obtained. According to this measurement, in which the intercept point of the straight line to the X-axis in FIG. 2 is vth after programming, good reproducibility and accuracy of Q and 1v or less can be obtained. It is also possible to measure 7thp of 20v or more.

尚設定するモードとしては、他にリードモード時にワー
ドラインをvppに設定することができる、モードやプ
ログラムモード時デンター人力を?IFとしてメモリセ
ル以外をスタンバイ状態に設定できるモード等ビットラ
インにメモリセル以外の電流を流さずワードラインにv
pp系の電圧を加えることができるモードの設定が数多
く可能である。
In addition, the modes that can be set include the mode in which the word line can be set to VPP in the read mode, and the mode in which the word line can be set to VPP in the read mode, and the mode in which the word line can be set to VPP in the program mode. A mode that can set non-memory cells to standby state as an IF, etc. No current other than memory cells flows to the bit line and V to the word line.
Many mode settings are possible in which pp-based voltage can be applied.

〔発明の効果〕〔Effect of the invention〕

本発明は、以上説明したように、lPROMにおけるプ
ログラム後のVthp を直接的に再現性良く、0.1
v以内の精度で測定でき、さらに高いVthpも測定で
きる。
As explained above, the present invention directly adjusts Vthp after programming in lPROM to 0.1 with good reproducibility.
It can be measured with an accuracy within V, and even higher Vthp can be measured.

【図面の簡単な説明】[Brief explanation of the drawing]

*1Sは本発明の一実施例でE’FROMのメモリセル
の選択及び書込み読み出し切シ換え回路図である。第2
図は本発明によって測定される電圧−電流特性図である
。 1・・・・・・プログラム電源 2・・・・・・リード電源 5・・・・・・?AMOSメモリ七ル 4.5・・1・・Nch)ランジスタ ロ・・・・・・Nchデプレシ璽ントントランジスタ7
・・・・・・pchトランジスタ9・・・・・・ノード 10.11.12,13.14・・・・・・信号ライン
15・・・・・・センスアンプ 第1図 第2図
*1S is an E'FROM memory cell selection and write/read switching circuit diagram in one embodiment of the present invention. Second
The figure is a voltage-current characteristic diagram measured by the present invention. 1...Program power supply 2...Read power supply 5...? AMOS memory 7.5...1...Nch) transistor......Nch depressing transistor 7
......pch transistor 9...node 10.11.12, 13.14...signal line 15...sense amplifier Fig. 1 Fig. 2

Claims (1)

【特許請求の範囲】[Claims]  メモリセルのしきい値電圧を上げてデータを記憶させ
る不揮発性半導体記憶装置において、メモリセルのワー
ドラインにプログラム電源系の電圧をかけ、電源に流れ
る電流をメモリセルに流れる電流だけにできる制御回路
と前記制御回路を制御するモードを設定したことを特徴
とした不揮発性半導体記憶装置。
In a nonvolatile semiconductor memory device that stores data by increasing the threshold voltage of a memory cell, a control circuit that applies a program power supply voltage to the word line of the memory cell and reduces the current flowing to the power supply only to the current flowing to the memory cell. and a mode for controlling the control circuit.
JP60100759A 1985-05-13 1985-05-13 Nonvolatile semiconductor storage device Pending JPS61258400A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60100759A JPS61258400A (en) 1985-05-13 1985-05-13 Nonvolatile semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60100759A JPS61258400A (en) 1985-05-13 1985-05-13 Nonvolatile semiconductor storage device

Publications (1)

Publication Number Publication Date
JPS61258400A true JPS61258400A (en) 1986-11-15

Family

ID=14282436

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60100759A Pending JPS61258400A (en) 1985-05-13 1985-05-13 Nonvolatile semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS61258400A (en)

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