JPS61255594A - Semiconductor memory circuit - Google Patents

Abstract

PURPOSE:To prevent a lowering of a reading speed owing to a deterioration of a reading power source voltage by detecting a bit line level by a feedback circuit to control a discharge of the bit line. CONSTITUTION:A feedback control circuit formed by N-type and P-type transistors N50, P20, N30 detects that a level of a bit line V10 is high, turns off the transistor N50 and raises a level of the nodal point V30. Thereby, the transistor P30 becomes further non-conductive and a level of a nodal point V50 is lowered and a transistor 70 is turned off and a level of a nodal point V60in raised. Then, a transistor N80 is turned on, an improper potential of the line V10 is discharged and rapidly lowered and a delay of a reading speed owing to a deterioration of a reading power source voltage is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor memory circuits, particularly detection circuits, used in semiconductor memory devices such as read-only memories.

[Summary of the invention]

The present invention relates to a semiconductor memory circuit used in a semiconductor memory device such as a read-only memory, particularly a detection circuit, in which a discharge having the function of lowering the potential of a bit line is controlled by a feedback control circuit that inputs potential information of the bit line. By installing a circuit, a decrease in read speed due to a decrease in read power supply voltage is prevented. [Prior Art] A conventional example is shown in FIG. N1 is a memory cell transistor, which is an N-channel type MOS transistor. WL is the output signal of the word line selection decoder, oN2 is the bit line selection N-channel type MO8) transistor,
Y is the output signal of the bit line selection decoder.

N5, N5, and N4 are N-channel type MOS transistors; IM and P2 are P-channel type MOS transistors.

The feedback control circuit consisting of N5, N3, and P2 causes a large current to flow from the power supply circuit consisting of transistor N4 to the bit line v1 when the bit line v1 is at a low potential level, since the transistor N5 becomes more conductive. On the other hand, when the bit line v1 gradually rises and reaches a certain set potential level, the transistor N5 becomes more non-conductive, so the power supply circuit and the bit line are cut off, and the bit line v1 is lowered to that set potential level. It has the function of stabilizing the level.

The range of potential change between on and off of the memory cell transistor N1 at the node v6, which is also the input point of the next-stage sense amplifier, is determined by the ability of the transistor P1.

[Problems and objects to be solved by the invention] After a series of read operations are performed at a certain high read power supply voltage 'VDD, a series of read operations are performed at a lower read power supply voltage VDD1. When operation begins and a memory cell is selected that is ON with the same bit line as in the case of the previous high power supply voltage, the bit line remains at a certain high level determined by the previous high read power supply voltage. , It takes time to lower the bit line potential to the bit line potential level when the memory cell is ON with the current low read power supply voltage 7DDi because conventionally, only memory cell transistors with small current capacity or means for lowering the bit line potential are used. That is, there is a problem in that the read speed is delayed.

SUMMARY OF THE INVENTION The purpose of the present invention is to solve these conventional problems and provide a circuit that detects when the bit line level is at a potential level that does not match the read power supply voltage and reduces the potential. [Means for Solving the Problem] In order to solve the above problem, a power supply circuit supplies a power supply voltage to the bit line of the selected memory cell transistor in order to detect the storage state of the memory cell transistor. a discharge circuit that removes potential from the bit line of the memory cell transistor; and a discharge circuit that receives potential information of the bit line of the memory cell transistor as input, and determines the power supply level of the power supply circuit to the bit line of the memory cell transistor and the The present invention is characterized by comprising a feedback control circuit that controls the level of discharge from the bit line of the memory cell transistor of the discharge circuit.

[For production]

In the semiconductor memory circuit configured as described above, even if the read power supply voltage drops midway through, the feedback control circuit quickly detects the high bit line potential state and performs read operation with the bit line potential reduced. Since the power supply voltage is lowered to an appropriate level that matches the power supply voltage, it is possible to prevent a reduction in the read speed. Embodiment Embodiments of the present invention will be described below with reference to the drawings.

Hlo is a memory cell transistor and is an N-channel MO
5) It is a transistor. WLZ is the output signal of the word line selection decoder, 0N20 is the bit line selection N-channel type MO3) transistor, Yz is the output signal of the bit line selection decoder. Plo, P2O are P channel type MO3)
A feedback circuit consisting of transistors 0N50, N30, and P2O is connected to the second
When the 0 bit line V10, which has the same function as the feedback circuit consisting of N5, N3, and P2 in the figure, is at a low potential, N50 becomes more conductive, and the bit line V10 is brought to a certain set potential level from the power supply circuit consisting of the transistor N40. When this happens, N50 is brought into a non-conductive state to cut off the bit line V10 and the power supply circuit, thereby stabilizing the potential of the bit line.

P-channel type MO8) transistor P10 is a transistor 0P30. P2O is a P-channel type M'i5''S transistor, N60, N7
0 and N80 are N-channel type [03) transistors.

Transistors F30, P2O, N50, N70, N
The circuit 80 has the function of lowering the potential of the bit line V10 when the potential level of the via line V10 is not at a level matching the read power supply voltage VDD.

Specifically, the transistors N50 and P2O mentioned above
. The potential level of <,
) As v50 shifts downward, transistor N70 becomes more non-conductive, and the potential level of node V60 moves upward.

This causes transistor N80 to become conductive, thereby inappropriately dropping the potential on bit line V10.

In the embodiments described above, the read power supply voltage 'V
A delay in read speed due to a decrease in DD can be prevented by introducing a feedback circuit that detects the bit line potential and reduces the bit line potential.

〔Effect of the invention〕

As explained above, the present invention has a function of detecting the bit line potential and lowering the bit line potential.
The feedback control circuit is effective because it prevents a delay in the read speed due to a decrease in the read power supply voltage (VDi).

[Brief explanation of drawings]

FIG. 1 is a semiconductor memory circuit diagram according to the present invention, and FIG. 2 is a conventional semiconductor memory circuit diagram. '7DD...Read power supply voltage Pl, P2, Pl 0, P2O, P2O, P2O
...P-channel type MOS transistors N1, N2
, N3 , N4 , N5 , N10 , N20, N3
0. N40. N50. N60. N70°N80...-N
Channel type MO3) transistor Vl, N2,
N5, N4. 71 0, N20. v60, N40, 'V50.760... Node YZ
, Y... Output signal of the bit line selection decoder WL, WLZ... Output signal of the word line selection decoder or higher

Claims (1)

[Claims] a power supply circuit that supplies power to the bit line of the memory cell transistor in order to detect the storage state of the selected memory cell transistor; a discharge circuit that removes potential from the bit line of the memory cell transistor; and a discharge circuit that removes a potential from the bit line of the memory cell transistor; a feedback control circuit that receives potential information of a bit line of a transistor and controls a power supply level of the power supply circuit to the bit line of the memory cell transistor and a discharge level of the discharge circuit from the bit line of the memory cell transistor; A semiconductor memory circuit comprising: