JPS61255384A - Thin film transistor matrix and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] In a thin film transistor (TPT) matrix,
By arranging a light-opaque drain bus line above the TPT via the TPT protective film, it is possible to reduce the area occupied by the pass line and increase the area occupied by the display pixels.

[Industrial application field]

The present invention relates to the structure and manufacturing method of a semiconductor device, and more specifically, to the structure and manufacturing method of a thin film transistor matrix used for switching each pixel of a liquid crystal display, electroluminescent display, electrochromic display, etc.

[Conventional technology]

The thin film transistor shown in plan view in FIG.
147 is provided, and a TFT 4 using a semiconductor film as an active layer is provided at each intersection of the gate line 46 and the drain line 47.
2 and a display electrode 41 are formed, and a metal light-shielding film is placed over the gate electrode of the TFT section 2 via an insulating film to prevent the TPT from being constantly turned on due to external light. ing.

[Problem that the invention seeks to solve]

In the prior art, the drain bus line was formed in the same process as the drain electrode of the TPT.

Therefore, the TFT section and the drain bus line each require separate areas, resulting in a disadvantage that the pixel occupation rate becomes small when the TFT matrix is applied to a display device.

The present invention was created in view of these points, and the TP
In an active matrix type display device using TFTs, the purpose is to increase the pixel occupation rate and improve the display performance by arranging the TFT section and the drain bus line three-dimensionally.

[Means for solving problems]

An embodiment of the invention is shown in the plan view of FIG. 1, and FIG.
FIG. 3 is a cross-sectional view taken along line nn in the figure.

1 and 2, 10 is a glass substrate, 11 is a display electrode, 12 is a drain bus line, and 13 is a TPT.

14 is a gate, 15 is a gate pass line, 16 is a gate insulating film, 17 is an active layer, 18 is a drain, 19 is a source, 20 is a TPT protective film, and 33 is a TPT channel protective film.

In FIG. 1, the drain bus line 12 is placed above the TFT via the TPT protection 11*20, so that the area occupied by the drain bus line is reduced.

[Effect]

The present invention employs a TPT matrix structure in which a low dielectric constant material such as polyimide is formed thickly and used as a protection layer for the TPT, and a drain bus line is placed on top of the TPT matrix, without electrically affecting the TPT. , it is possible to reduce the area occupied by the TPT and the drain bus line, thereby increasing the pixel occupation rate, and if the semiconductor film constituting the TPT is photoconductive, the drain bus line above the TPT can be replaced with an opaque film. TPT than keeping it as
By taking advantage of the fact that the drain bus line can also serve as a light-shielding film, it is possible to provide an active matrix display device with excellent display performance.

〔Example〕

FIGS. 1 and 2 show an example of the configuration of one pixel of the TPT matrix according to the present invention, with FIG. 1 being a plan view and FIG. 2 being a sectional view taken along the -shore line in FIG. 1. According to the conventional method shown in FIG. 4, the drain bus line 43 and the TFT 42 are located at different locations, whereas in the embodiment shown in FIG. 1, both are located at the same location.

In Figure 1, the drain and drain bus line are connected to TP.
Since they are fabricated via a T protective film (see the cross-sectional view in FIG. 2), connection holes are required to connect them. In this embodiment, this hole, that is, the drain/drain bus contact hole 21 is arranged on the extension line of the gate electrode. With this arrangement, the drain bus line 12 can have a simple linear shape. For this reason, it is necessary to facilitate patterning to separate the source and drain, and in this embodiment, the gate electrode 14 is bent into a hook shape. When using such a gate electrode shape, it is extremely effective to use a self-alignment method to align the gate and source/drain.

The embodiment shown in FIGS. 1 and 2 has a pass line of 50μ1
In this example, when one pixel pitch is 450 Atm, the pixel area is 0.108n2 in FIG. 4, while it is 0.12602n2 in FIG. 1, which is an approximately 17% increase in pixel area. Note that the lines shown as 100 μI in FIGS. 1 and 4 have been added for the purpose of understanding the dimensions of those shown in the same figures.

In this example, the semiconductor film is hydrogenated amorphous silicon (
a-3i: H, 1000 layers), the gate insulating film is silicon nitride (SiN) 3000 layers, and the TPT protective film is polyimide 1 μm thick. Normally, when a metal film is placed on top of the TPT and used as a light-shielding film, the light-shielding film is at ground potential or floating potential, but in this example, it is at the signal potential of the drain, so there is a risk that this potential may affect the TPT. There is. However, the film thickness d(
μm), the relative dielectric constant is ε, and the gate insulating film has ε/d=610.3, while the TPT protective film has ε/d=3.
/1, it is understood that the influence of the signal line potential on the TPT is about 1/7 of that of the gate potential.

Furthermore, there are differences in the gate insulating film/semiconductor film interface and the TPT protective film/semiconductor film interface, and in reality, the influence of the signal line is hardly recognized even when approximately 100 μm is applied.

A method of manufacturing the embodiment of FIG. 1 will now be described with reference to FIG.

■ Chromium (Cr) is vapor-deposited, and Figure 3 (cross-sectional view of al, (
A gate electrode 14 shown in the plan view of bl is formed.

■By plasma CVD method, silicon oxide film 31 (3000 people), amorphous silicon film 32 (a-Si) (1000 people), silicon dioxide film 33 (5i02) (1000 people),
A-St film formation 4 (100 people) was continuously formed.

(2) When a positive resist is applied to the entire surface and the back side is exposed, the gate electrode 14 becomes a mask, and when developed, only the resist above the gate electrode remains.

■ Using the remaining resist as a mask, the SiO2 film 33 (10
00) and the a-Si film 34 (100).

■N” a-Si film 35 (approximately 300 people), titanium film 36 (Ti) (1000 people), aluminum M on the entire surface
Aoi 37 (8β) (3,000 people) is killed.

(2) Remove the portion formed on the resist by lift-off (Fig. 3(C)). Note that FIG. 3 TC) is an enlarged sectional view.

■ Patterning the drain electrode, and as shown in FIG. 3(C), the upper part of the gate electrode 14 is a-St, SiO2+
Etch a-Si, Tin Al.

A plan view of the drain region 38 and source region 39 is shown in FIG.
It will be as shown in dl.

(2) Polyimide is applied and patterned as shown in FIG. 3 (e+). In this figure, the shaded area is the area 40 from which the polyimide has been removed.

(2) ITO (indium tin oxide) is applied to the entire surface and patterned to form display electrodes 11 (FIG. 3(e)).

[Phase] Chrome (700 people), Aj! (10000
A film is formed and patterned as shown in FIG. 3(f).

The contact 21 made at this time is for connecting the TPT and the display electrode. Note that this contact 21 is omitted in FIG.

〔Effect of the invention〕

As described above, according to the present invention, the pixel occupation rate of an active matrix display device using TPT can be increased, so the entire screen of a liquid crystal panel, EC panel, etc. can be bright and have high contrast, and display performance can be improved. You can make improvements.

[Brief explanation of the drawing]

FIG. 1 is a plan view of an embodiment of the present invention, FIG. 2 is a sectional view taken along line nn in FIG. 1, and FIG. 3 is a diagram showing the steps of the method of the present invention. (dl, (e), (f) are plan views, (a) and (
C) is a cross-sectional view. FIG. 4 is a plan view of the conventional example. In FIGS. 1 to 3, 10 is a glass substrate, 11 is a display electrode, 12 is a drain bus line, and 13 is a TPT. 14 is a gate electrode, 15 is a gate pass line, 16 is a gate insulating film, 17 is an active layer (semiconductor 1!ti), 18 is a source electrode, 19 is a drain electrode, 20 is a TPT protective film 21 is a contact part, 31 is a nitride Silicon film, 32 is a-5T film, 33 is 5i02 film, 34 is a-St film, 35 is n''a-3III, 36 is titanium film, 37 is Al film, 38 is drain region, 39 is source region, 40 is the part from which polyimide has been removed. 1, Poor ・ゝ', 2r

Claims (3)

[Claims] (1) A plurality of gate lines (14) and the gate lines (1
4), and a thin film transistor using a semiconductor film as an active layer (17) and a display electrode ( 11) A thin film transistor matrix comprising: a drain bus line (12) arranged above the transistor via a thin film transistor protective film (20). (2) As a material for the drain bus line (12),
The thin film transistor matrix according to claim 1, characterized in that a conductive material that is opaque to light is used. (3) Step of forming a gate electrode on the glass substrate (10), silicon nitride (16),
Step of successively forming films of amorphous silicon (17), silicon dioxide, and amorphous silicon; Step of applying positive resist to the entire surface of the substrate (10) and patterning the resist by exposing from the back side of the substrate; Masking the remaining resist. a step of etching the top layer of amorphous and the underlying silicon dioxide, a step of sequentially forming films of amorphous silicon containing high concentration of impurities, titanium, and aluminum on the entire surface of the substrate, and removing the remaining resist along with the film above it. a step of patterning the drain electrode (19); a step of applying a material for the thin film transistor protective film (20) to the entire surface of the substrate and patterning it to form the display electrode (11) forming part and the drain/drain bus line contact; a step of removing the protective film in the hole (21) portion; a step of forming a material film for forming the display electrode (11) on the entire surface of the substrate and patterning it to form the display electrode (11); A method for manufacturing a thin film transistor matrix, comprising the steps of forming an aluminum film and patterning it to form a drain bus line (12) and a contact portion (21).