JPS61252785A - Picture processor - Google Patents

Abstract

PURPOSE:To easily form a picture processor capable of outputting for printing in a printer or the like by digitizing the picture information drawn on a surface uneven in brightness. CONSTITUTION:When an analog switch 106a of a brightness photometry circuit (100a) is turned on, the photometry is performed by a split photoelectric converting element a (4a) and the analog brightness data logarithmically compressed by an operation amplifier 104a, and a log diode 105a is inputted to an A/D converter 115 and digitized. Subsequently, an address value selecting the A/D converter 115 from a CPU107 is outputted to an address bus 108. When an IOR signal of a control bus 110 is outputted, the digitized brightness compression data is fetched. By the CPU107 this stored data is calculated and rewritten to a value suitable for a binary coded conversion of a camera picture signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an image processing device that divides an analog luminance image into multiple parts and determines a threshold value for digitized luminance based on the read luminance of the divided areas.

[Prior art and its problems] Recently, so-called "electronic blackboards" have appeared that print out information such as characters and figures written on a board as they are. These "electronic blackboards" are: ■The blackboard itself is equipped with a coordinate input device such as a digitizer.

■For example, use a white film as the blackboard (what is written on),
There are devices that use line feet to detect this using a line-type optical image sensor, but in any case, the mechanism is built into the blackboard itself, making it large and not easily portable and expensive. ing.

Object of the Invention The present invention was made in view of the above circumstances, and provides image processing that is easy to carry, is not limited to blackboards, and is capable of processing things written or displayed on walls, screens, etc. The purpose is to provide equipment.

Another object of the present invention is to provide an image processing device that has a simple structure and is inexpensive.

"Embodiment of the Invention" Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment according to the present invention, in which 2 is a CRT display device, 3 is a release switch, 7 is a print switch, and 100a to 100p are brightness photometry circuits a to p. Since they have the same configuration, only the brightness photometry circuit a (100a) is shown in detail. 4a in the brightness photometry circuit a (100a) is a multi-division photoelectric conversion element a, 10
4a is operational amplifier a, 105a is log diode, 10
6a is an analog switch. Multi-divided photoelectric element a (4
a) is connected between the inverting input terminal and the non-inverting input terminal of the operational amplifier a (104a), the output terminal and the inverting input terminal of the operational amplifier 101 are connected to the non-inverting input terminal, and operates as a voltage follower. ing. A resistor 103 and a constant current source 102 are connected to a non-inverting input terminal of the operational amplifier 101, creating a constant voltage source. Furthermore, a log diode 105a is connected between the inverting input terminal and the output terminal of the operational amplifier a (104a), with the inverting input terminal side as the cathode.
4a) operates as a logarithmic compression amplifier. The output terminal of operational amplifier a (104a) is connected to the analog switch (10
6a).

107 is a control unit (hereinafter referred to as CP) that controls the entire control of this embodiment.
108 is an address bus, 109 is a data bus, and 110 is a control bus, and the CPU 107 controls each unit via these buses. Also, 111 is C
An RT address bus 112 is a CRT data bus used for read/write control to the video RAM 127.

113 is a latch circuit A, 114 is a decoder, and 115 is A
-D converter, 116 is latch circuit B, 117 is DA converter, 118 is comparator, 119 is shift register A, 120 is latch circuit C, 121, 122 are analog switches, 123 is shift register B, 124 is CPU
107 is a ROM that stores control procedures, etc., and 125 is a RAM.
, 126 is a CRT control unit that controls the CRT display of the CR7 display device 2, 127 is a video RAM that stores the display image of the CR7 display device 2, 128 is a printer control unit,
129 is a printer, and 130 is a camera section.

FIG. 2 shows an external front view of the apparatus of this embodiment having the above configuration, and FIG. 3 shows a rear view thereof.

Figure $2 is an external view of the photographic lens side of this embodiment, and 1 is the photographic lens of the camera section 130. Further, in Fig. 83, 2 is a display cathode ray tube of a CRT display device, 3 is a release switch, and 4 is a cathode ray tube cover with a multi-segment photometry surface (hereinafter referred to as the cover). The surface of the cover 4 facing the cathode ray tube 2 is shown in Fig. As shown in FIG. is arranged, so that the brightness from the cathode ray tube 2 can be measured.

Further, 5 is a power switch, 6 is a reset switch, 7 is a print switch for instructing printing to the printer 129, 8 is a feed switch, and 9 is a print data output window of the printer.

The operation of this embodiment having the above configuration will be explained below with reference to the flowchart of FIG.

The following description will be made regarding print output processing by the printer 129 of image information drawn on a general blackboard.

When the power switch 5 is turned on and the device of this embodiment is powered on, the process proceeds to step Sl, where the image information captured by the camera section 130 is displayed on the cathode ray tube 2 as it is. This display on the cathode ray tube 2 is performed in the following sequence.

When the device is powered on, the CPU 107 activates the latch circuit C.
By outputting an address value for selecting l2O to the address bus 108, outputting data for turning on the analog switch 121 and turning off the analog switch 122 to the data bus 109, and turning on the ■OW signal of the control bus 110, the latch circuit C
The data on the data bus is latched to l2O, the analog switch 121 is turned on, and the image signal from the camera section 130 is output for display on the cathode ray tube 2 of the CRT display device.

Here, the H5YNC signal from the CRT control section 126 is a horizontal synchronization signal of the camera section 130, and the V5YNC signal is a vertical synchronization signal of the camera section 130, which are respectively output to the camera section 130. Also, this signal is the CPU 107
It is also output to the interrupt input terminals INTl and INT2 of the .

The operator checks the image display displayed on the cathode ray tube 2, determines whether the screen layout of the blackboard image is OK in step S2, and moves the device in step S3 if the screen layout needs to be changed. The direction of the photographing lens 1 is changed and the screen is rearranged. When the screen arrangement is OK, the process proceeds from step S2 to step S4, and the cover 4 is closed.

When the cover 4 is closed, the release switch 3 is turned on (closed) as shown in step S5.The release switch 3 is normally off and is pulled up by the resistor 131.
It is connected to the interrupt terminal INTO of the CPU 107.

Therefore, when the release switch 3 is turned on by closing the cover 4, an interrupt is generated in the CPU 107, and the 2 (input conversion program processing) starting from step S6 is started. This 2E conversion processing program is stored in the ROM 124. , the CPU 107 performs processing according to this program.

First, in step S6, the multi-divided photoelectric conversion element (light receiving element) 4
The brightness of each divided area 4A to 4P is measured by a to 4p. Specifically, an address value for selecting the latch circuit A113 is output from the CPU 107 to the address bus 108,
The data bus 109 is connected to the brightness photometry circuit a-p (iota-
Loop) analog switches 106a-106p are output, and the control bus 110
The IOW signal is output. As a result, latch circuit A1
13, data on the data bus 109 is latched and decoded by the decoder 114 connected to the output thereof, and only one of the analog switches 106a-106p is turned on. First, luminance photometry circuit a (100
When the analog switch 106a in a) is turned on, the analog luminance data side-lighted by the split photoelectric conversion element a (4a) and logarithmically compressed by the operational amplifier 104a and the log diode 105a is input to the A-D converter 115 and digitized. Ru. Next, from the CPU 107 to the A-D converter 1
When the address value for selecting 15 is output to the address bus 108 and the IOR signal of the control bus 110 is output, the digitized brightness compressed data is sent to the CPU.
107. From CPU107 to RAM125
An address value for selecting is output to the address bus 108, the brightness compressed data is output to the data bus 109,
When the MEMW signal is output to the control bus 110, the RAM 125 stores the brightness compressed data on the data bus 109.
Execute repeatedly.

All the luminance data detected in each of the divided areas 4A to 4P is compressed and digitized and sequentially stored in the RAM 125.

Then, in the following step S7, the CPU 107 rewrites this stored data into pieces suitable for binary conversion of the camera image signal. Here, the camera image signal is connected to the non-inverting input terminal of the comparator 118. The output terminal of the DA converter 117 is connected to the inverting input terminal. Further, the output terminal of the comparator 118 is connected to a shift register A119. Shift register A11
9 is used to input a serial signal and convert it into a parallel signal.

Synchronization of the binarization level (inverted input terminal signal) of the comparator 118, which changes depending on the camera image signal and luminance information, will be described below.

When the CPU 107 receives an interrupt due to the V5YNC signal, due to the time difference with the interrupt due to the H5YNC signal,
The starting point of the odd field in the interlaced system is found, and from there the sequence of creating a synchronizing signal and capturing the bivalent data is executed. First of all, CPU107 is RAM125
The zero-order data latch (latch circuit )116 is output to the address bus 108, the luminance data taken in by the CPUIO7 is output to the data bus 109, the IOW signal of the control bus 110 is output, and the latch circuit B11B is written to the latch circuit B116. The output terminal is the DA converter 11
7, and the output terminal of the DA converter 117 is connected to the inverting input terminal of the comparator 118. Therefore, a bivalent comparison level is set based on the photometric luminance data from the side light element 4a and output to the comparator 118. The camera image signal is synchronized with the brightness information of the photometric element 4a, and the set 2
It is binarized with a digitized comparison level voltage and inputted to the shift register A119.

These two image signals are sequentially stored in the video RAM 127 by the CRT control unit 126 in step S8. Then, in the following step S9, one screen, that is, the divided area 4A~
It is checked whether up to 4P has been completed and if it has not been completed, the process returns to step S7 to perform photometry of brightness information of the next divided area and storage of image information in the video RAM 127. That is, 12g5 after the start of the odd field, the binarized comparator level is replaced with the voltage of the luminance data from the divided area 4B in the same manner. Furthermore, after 12JLS, the voltage of the data in the divided area 4C1 is replaced with the voltage of the data in the divided area 4D after 12g5, and binarization conversion is performed. The next H5YNC signal replaces the data voltage of divided area 4A again, and H
The above operation is repeated until the 5YNC signal is input 60 times.

By the 60th H5YNC signal, the luminance data is replaced with the data of the divided areas 4E to 4H, and the binarization level is changed to at in the same manner as above. When the 120th H5YNC signal is input, the data of divided areas 4 to 4L are further input to 1.
After the 80th time, if there is a 0th order V5YNC signal that makes the 4M to 4P data a binary level as described above, it becomes an even field.

The data in the divided area 4C is converted to a binary level, and further converted to 1zI.
After LS, the data in the divided area 4D is converted to a binary level, and the binary level is switched in the same manner as above until the next V5YNC signal is received.
4, the binarized data of the entire screen is stored.

The photometry timing during this period is shown in FIG. In FIG. 6, 4a to 4p indicate the binary level photometric data of the multi-division photoelectric conversion elements (photometric elements) in each divided area 4A to 4P, and the number on the HSYNC signal indicates the number of times the H5YNC signal arrives. . When the binarized imaging data for the plan surface is stored in the video RAM 127 in this way, the CPU 1
07 proceeds from step S9 to step S10, and this 2
The digitized data is displayed on the cathode ray tube 2. CPU10
7 outputs the address value to select the latch circuit Cl2O to the address bus 108, and outputs the latch data to turn off the analog switch 121 and turn on the analog switch 122 to the data bus 1.
At 09, the IOW signal is output from the control bus 110, the latch circuit Cl2O is latched, and the analog switches 121 and 122 are switched. As a result, the signal from the shift register B123 is supplied to the CRT display device 2 instead of the image signal from the camera section 130.

The CRT control unit 126 scans the read address of the video RAM 127 from the CRT address bus 111, reads out the sequentially stored z-valued image data as parallel data, and supplies it to the shift register B 123 via the CRT data bus 112. The shift register B123 converts this parallel read data into serial data, supplies it to the CRT display device 2 from the analog switch 122, and displays it on the cathode ray tube 2 as a 2-piece image. Although not shown, the shift clock of this shift register B123 is CR
It is output from the T control section 126. This binary screen is displayed until the reset switch 6 is pressed or the power switch 5 is turned off (step Sll,
Step S12).

To make a hard copy of this binarized screen using the printer 129, the print switch 7 is pressed. When the print switch 7 is pressed, the INT3 of the CPU 107
An interrupt is generated at the terminal, and step 51 starts from step Sll.
Proceed to step 3 to execute print processing. Note that since this print data is binary data, a normal dot printer can be used.

The CPU 107 starts the printer control unit 128, and the printer control unit 128 reads two screens worth of data from the video RAM 127.
The digitized image data is sequentially read out and sent to the printer 129 to be printed out. Reading of the binarized image data from the video RAM 127 may be performed by direct memory access control from the printer controller 128, or by
The image data may be sequentially read from the video RAM 127 under the control of the PU 107 and supplied to the printer control unit 128. Even during this printout process, the CRT control unit 126 may sequentially read display data from the video RAM 127 and send it to the CRT data bus. 112, and the printer control unit 128 takes in the parallel data on the CRT data bus 112 or the serial data from the shift register B123, and outputs the V5YNC signal and H5YNC signal.
The start of one screen's worth of data may be detected by a signal and printed out sequentially.

When the partial reset switch 6 is turned on, step S is resumed.
1, the image captured by the camera unit 130 is displayed on the cathode ray tube 2.
will be displayed.

In the above explanation, an example was explained in which 2-E data is stored in the video RAM 127, but it is possible to easily convert it into multi-value data by outputting a multi-value comparison level from the D-A converter 117 as a threshold higher than that. can do. This can be easily done by changing the latch data sent by the CPU 107 to the latch circuit B116, by providing a plurality of comparators 118, or by driving them in a time-division manner.

As explained above, according to this embodiment, when the camera unit 130 performs binarization processing on image information drawn on a blackboard, wall surface, screen, etc., the amount of light irradiated onto the blackboard etc. by lighting etc. Even if there are changes in the amount of light reflected from the blackboard, etc., the characters on the blackboard can be clearly seen at any position on the screen after binarization, and the printer that prints out this image must also be a special printer, such as a multi-gradation printer. It can be done with a regular printer instead. In addition, by measuring the average brightness of the entire screen and determining the threshold value as in the past, the brightness of the blackboard is not uniform and after two parts, a part of the blackboard becomes white and the letters disappear. It also turns black and the letters disappear. However, in the present invention, even if a reference level is set at which characters can be clearly seen after binarization in a certain part, the digitization threshold of the luminance level is determined by dividing the threshold into multiple parts, so the characters in other parts become invisible. It also has a simple structure and can be carried.

"Effects of the Invention" As explained above, according to the present invention, image information drawn on a surface with non-uniform overall brightness can be appropriately converted into a digital image with a simple configuration, and can be easily converted into a digital image using a printer, etc. An image processing device capable of print output can be provided.

Furthermore, by capturing image information with a camera, there are no restrictions on the portion of the image information that can be processed, and the image processing apparatus can be used in a very wide range of applications.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment according to the present invention, Fig. 2 is a front view of this embodiment, Fig. 3 is a rear view of this embodiment, and Fig. 4 is a partially closed cover of this embodiment. An enlarged view of a part of the cover seen through in the direction of the cathode ray tube in the closed state. FIG. 5 is an operation control flowchart of this embodiment, and FIG. 6 is a timing chart of image data binarization control of this embodiment. In the figure, 1...taking lens, 2...CRT display device (
Braun tube], 3... Release switch, 4... Force 1<-14A~4P... Divided area, 4a~4p...
Multi-division photoelectric conversion element, 5...power switch, 6...
Reset switch, 7...Print switch, 101
゜104a~104p... operational amplifier, 102...
Constant current source, 103, 131...Resistor, 105a
~105p...Log diode, 106a-
106p. 121.122...Analog switch, 107...
CPU, 108...address bus, 109...data bus, 110...control bus, 111...
CRT address bus, 112...CRT data bus,
113.116,120...Latch circuit, 114...
- Decoder, 115...A-D converter, 117...
D-A converter, 118... comparator, 119, 1
23...Shift register, 129...Printer, 1
30... Camera section. Figure 2 Figure 3

Claims (2)

[Claims] (1) A reading means for reading image information, an output means for outputting the image information read by the reading means, a brightness reading means for reading the brightness of the image information output from the output means, and a brightness read by the brightness reading means. and a brightness image output means for at least binarizing the brightness of the read image based on the threshold determined by the threshold value determining means to obtain a digital brightness image. An image processing apparatus characterized in that the means reads the analog luminance image outputted from the output means by dividing it into multiple parts. (2) The image processing apparatus according to claim 1, wherein the reading means is a television camera.