JPS61251962A - Matrix multiplier - Google Patents

Abstract

PURPOSE:To operate a sum of products at a high speed with the simple constitution in terms of a row vector made of two constant and two real numbers composed of the product of a mantissa part and power of two and a column vector made of two variables and one fixed value by latching them the mantissa part and an exponent part shift register, inputting sequentially (x) and (y) and executing the prescribed arithmetic processing. CONSTITUTION:In terms of the product sum of the row vector composed of two real numbers amX2<ae-m> and bmX2<be-m>, and the constant (e) and the column vector composed of two variables (x) and (y) and the constant '1', the am and the bm in registers 13 and 14 are loaded in multipliers 21, 22, and the ae and the be in registers 15 and 16 are loaded in control blocks 23, 24. (x), (y) and a sine bit S are transmitted to the multipliers 21 and 22 through shift registers 17 and 18 corresponding to the trigger pulses CLK2 and CLK23 of the blocks 23 and 24, and simultaneously the am and the bm are loaded. The outputs of the multipliers 21 and 22 are inputted to adders 31 and 34. An (e) in the shift register is inputted to the multiplier 31 in accordance with the CLK1 and its output is inputted to the multiplier 34, whose output is transmitted to a shift register 35, thereby obtaining a desired result (u).

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a matrix multiplier that calculates the product of a row vector and a column vector, which is necessary for coordinate transformation particularly in graphic processing.

[Technical background of the invention and its problems] In recent years, graphic processing systems using computers have come into widespread use. This system generally consists of a graphics definition system and a graphics display system.

Then, virtual space (xy-space) is created using the figure definition system.
The figure defined in is subjected to several transformations by the figure display system and is mapped to real space (UV-space). This real space is the CRT of the graphic display device.
Compatible with tube surfaces and electrostatic plotter paper surfaces.

Now, the conversion in the two-dimensional coordinate space is based on equation (1).

x, y: Absolute value coordinates in virtual space u, v: absolute value coordinates in real space In the above formula (1), a, b, and c are constant terms.

d is a real number expressed as a floating point number, and X.

y is an integer expressed in two's complement. Therefore, in order to convert the above equation (1), sum-of-product calculations involving complicated floating-point processing are required. For this reason, the conversion of equation (1) above has conventionally been performed by a microprocessor in a host computer or peripheral device. However, performing the above conversion using a host computer or microprocessor requires a large amount of processing time, which poses a problem as a bottleneck for high-speed display.

[Object of the invention] This invention was made in view of the above circumstances, and its purpose is to solve the problem of a-X+b-y+e (
A and b are constant terms and real numbers, x and y are variable terms and integers, and e is a constant term and must be a fixed-point number. It is about providing.

[Summary of the invention] If this invention is J: 8mX2.

Constant terms a, b expressed as bmX2be-m (am.

bm is a multi-bit integer expressed in two's complement, ae, b
A row vector consisting of three elements: e, m are integers satisfying O≦ae, be≦m) and a constant term e (e is a fixed-point number with p bits in the integer part and q bits in the fraction part, expressed in two's complement). and the variable term x, y (x, y are two-bit integers expressed in two's complement) and a column vector consisting of three elements with an identification value of 1. A matrix multiplier is provided that performs a summation operation.

The matrix multiplier has an 8m register that latches am, a bm register that latches bm, and counts m and q according to the basic clock signal at the start of operation.
a first control means that repeatedly generates a first control trigger pulse synchronized with the tarok signal when counting the difference between the two and
A second control means performs counting according to the basic clock signal at the start of operation, and repeatedly generates a second control trigger pulse synchronized with the same clock signal when only ae is counted; , be, the third control means repeatedly generates a third control trigger pulse synchronized with the same clock signal.

The matrix multiplier also includes a first shift register that latches e and shifts its contents downward in response to a first control trigger pulse from the first control means, and a first shift register that latches e and shifts its contents downward in response to a first control trigger pulse from the first control means; a second shift register that shifts downward in response to a second control trigger pulse from the means;
The third shift register has a third shift register that latches and shifts its contents downward in response to a third control trigger pulse from a third control means, and first and second multipliers of lXff bits. The serial output bits from the second shift register and the contents of the 8m register are fed to a first multiplier;
The serial output bits from the third shift register and the contents of the bm register are provided to a second multiplier. The first multiplier combines the serial output bits from the second shift register with 8
The second multiplier performs multiplication by the contents of the m register in response to a second control trigger pulse from the second control means, and the second multiplier multiplies the serial output bit from the third shift l-register by the contents of the bm register. is executed in response to a third control trigger pulse from the third control means, and the lowest digits 1 to 1 of the multiplication results are output for each multiplication operation. That is, the first. The second multiplier is
The multiplication result of a-x and by is output in 1-bit units.

The matrix multiplier further includes addition means.

The adding means is supplied with the output bits from the first and second multipliers and the serial output bits from the first shift register. The adding means repeatedly adds these three types of input bits.

Now, the operation of the first shift register is controlled by the first control trigger pulse from the first control means, the operation of the second shift register and the first multiplier is controlled by the second control trigger pulse from the second control means, The operation of the third shift register and the second multiplier is controlled by a third control trigger pulse from the third control means. Therefore, the first . Each bit data from the second multiplier and the first shift register is correctly aligned,
Therefore, the addition means outputs the product-sum operation results indicated by a-x+b-y+e in order from the lower bits.

[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a matrix multiplier according to an embodiment of the present invention. The matrix multiplier in FIG.
It is used to calculate u (=a −x+b −y+e) in the equation. In FIG. 1, 11 is an X register that latches a variable term X given from the outside (upper processor), and 12 is an X register that latches a variable term y also given from the outside.

x and y are bit integers expressed as two's complement numbers.

In this example, =24.

Now, the constant term a-d in the above equation (1) is a real number (R)
It is. A real number (R) has a mantissa part (P) and an exponent part (E-)
It is expressed by the following equation (2).

R=Px2E-(2) The exponent part E- can take a value expressed as -8≦F-≦t(3). However, s and t are positive integers. The above equation (3) can be rewritten as O≦E≦m (4) by setting m=s±t and E=E−+S. In addition, equation (2) can be rewritten as R= Pmx 2 ''' (5) by setting Pm=PX2t.As is clear from equation (4), the exponent part E - m of equation (5) above is O or negative. In this example,
A real number (R) in the form of equation (5) above is applied. That is,
In this embodiment, unlike a normal floating point number, the exponent part of all the handling data (real numbers) is set to be less than or equal to O, and accordingly, the mantissa part is multiplied by 21 in advance.

From the above, the constant terms a, b, c, d are a=amx2
ae-m b=bmx2"'-" C=CmX2°e-m d=dm×2d0-IIl Where, ■am-dm is an l-bit integer expressed in two's complement, ■ae~ad, m is an integer that satisfies the following conditions: O≦ae, be, ce, de≦m.

Further, the constant terms e and f in equation (1) are expressed as two's complement numbers, and are fixed point numbers with p bits in the integer part and q pits in the decimal part.

When these are used, U and V in the above formula (1) become the formula (6).

It becomes as shown in equation (7).

'u=am -x -2ae-m e-m +bm-y・2 +e (6)v=cm
-x -2Ce-me-m 10dm-y.2 +f (7) The above equation (6) is schematically shown in FIG. 2.

As is clear from the above explanation and FIG. 2, m is
The reference point (position) for each handling data decimal point position is shown, and ae and be are am (am-x) and bm from the reference point.
(Indicates the number of bits up to the least significant bit of bm-y>.

The number of bits from the reference point to the least significant bit of e is (
m−q) bits. Therefore, am(am-x)
, bm (bm-y) by counting ae and be, and e by counting m-q to determine the processing start timing, thereby making it possible to correctly align the digits.

Referring again to FIG. 1, 13 is an am register that latches the constant term am, 14 is a bm register that latches the same <bm, and 15 is an aem register that also latches ae. 16 is a be register that latches the same <be. be. a
As described above, m and bm are 2-bit integers expressed as two's complement numbers. In this example, 2=24. am
, bm, ae.

be is given in advance from the outside (upper processor). 17 is an X shift register that loads the variable term X (X coordinate value) latched into the X register 11 and shifts its contents downward in response to the control trigger pulse CLK2; 18 is a variable latched into the X register 12; This is a y shift register that loads the term y (y coordinate value) and shifts its contents downward in response to the control trigger pulse CLK3.

Further, reference numeral 19.20 is a flip-flop that latches the sign bit S of x and y from register 11.12 and supplies it to the most significant bit MSB position of shift register 18.19.

21 loads the held content am from the am register 13 and outputs the serial output bit X from the X shift register 17.
1×2 bits (multiplier with E=24>, 22 is bm
Load the held content bm from the register 14 and perform multiplication between the serial output bit Y- from the X shift register 18 according to the control trigger pulse CLK31)
It is an l-bit (2=24) multiplier. Multiplier 21.2
2 is the least significant bit LS of the result for each multiplication operation.
It is designed to output B. The multipliers 21 and 22 are
For example, it is constructed using 25LS14 (1×8 bit multiplier) of 3 m each made by AMD, USA.

23 and 24 have built-in counters (not shown), and control trigger pulses CLK2. Control block (DE
LAY>. Control blocks 23 and 24 register 1
After loading ae and be from 5.16 and counting down their values using the basic clock signal CLK to reach "OII," add 3 to the control trigger pulse CLK2.CL- synchronized with the same tarlock signal CLK k+l times (k =24.J2
=24) is set to occur. control block 23
The control trigger pulse CLK2 from X shift register 1
A control trigger pulse CLK3 from a control block 24 is supplied to an X shift register 18 and a multiplier 22. Further, 25 is a control block (DELAY>) that generates the control trigger pulse CLK1.The control block 25 internally holds a predetermined value m-q, and when the operation starts, m-q is stored in an internal counter (not shown). ) and load its value into the basic clock signal CLK.
After counting down and reaching "O", the control trigger pulse CLK1 synchronized with the same tally clock signal CLK is generated p+q times. As mentioned above, m is the number of bits from the reference point to the decimal point. For example, it is 51. Also, p and q are the number of bits of the integer part and fractional part, respectively, of e given as a constant term from the outside. In this example, p = 40.q = 8. .

Reference numeral 26 denotes an e shift register which latches e given as a constant term from the outside and shifts its contents downward in response to the control trigger pulse CLK1. The serial output bit Ei of the e shift register 26 is
MSB of , and a flip-flop (L) 27 for timing correction.

31 is a 1-bit adder (ADD>) that adds the serial output bit AX"j of the multiplier 21 and the output bit E-1 of the flip-flop 27; 32 is an addition flip-flop (L); and 33 is a multiplication 34 is a flip-flop 32.3 for timing correction that holds the serial output bit BY-k of the device 22.
A 1-bit adder (ADD>
, 35 are p+q bits (p+q
=48) U shift register. The addition result R7 of the adder 34 is serially input to the U shift register 35 starting from its MSB.

Next, the operation of one embodiment of the present invention will be explained with reference to the timing chart of FIG. In addition, in Fig. 3, T
i<i=1.2. . . 98) represents a clock cycle, RDY represents a status signal indicating the state of the matrix multiplier shown in FIG. 1, and Dl represents a clock cycle.

D2. D3 shows the change in the values (ae, be, m-q) loaded into control block 23.24.25.

In the matrix multiplier shown in FIG. 1, before calculating U for each pair of X and y, am
, ae, bm, be, and e are given sequentially. and am
is set in the am register 13, and ae is set in the ae register 15. Also, bm is stored in the bm register 14, b
e is set in the bem register 16 and e is set in the e shift register 26, respectively. After this, only the X, y pair is sequentially given from the outside, and coordinate transformation is performed continuously.

Now, the operation of the matrix multiplier in Figure 1 is as follows:
is set in the registers 11 and 12, and the status signal RDY of a status circuit (not shown) becomes 1-1i (lh level), and the process starts (T1).

First, am in the am register 13 is sent to the multiplier 21, and b
bm in the m register 14 is sent to the multiplier 22, ae in the aem register 15 is sent to the control block 23 (not shown), and be in the be register 16 is sent to the control block 24 (not shown).
), X in the X register 11 is transferred to the X shift register 17, and y in the X register 12 is transferred to
Each is loaded into the shift register 18 (T2)
. Also, at T2, the sign bit S of X in the X register 11 is loaded into the flip-flop 19, and the sign bit S of y in the X register 12 is loaded into the flip-flop 20, respectively. Further, in step 2, m-q held in the control block 25 is loaded into a counter (not shown) in the block 25. The control blocks 23, 24, and 25 then count down based on the basic clock signal CLK since the loaded value becomes "O". In this example, ae=Q, be=4L m-
q=51-8=43. Therefore, in the control block 24, between T3 and 66, and in the control block 25, T3
A countdown is performed during the period from -T46. Note that since ae=0 in the control block 23, no countdown is performed.

This operation corresponds to the process of aligning the decimal points in FIG.

Control blocks 23, 24, and 25 control trigger pulses CLK1 . Generate CLK2°CLK3. Specifically, the control blocks 23, 24, 25 directly convert the pulse train of the basic clock signal CLK into control trigger pulses CLK1. Output as CLK2 and CLK3. Note that since the control block 23 has ae=Q,
Control trigger pulse CLK2 is generated from T3.

The control trigger pulse CLK2 from the control block 23 is
The signal is supplied to a shift register 17 and a multiplier 21. As a result, the X shift register 17 starts a downward shift operation (right shift operation). X shift register 17
The serial output bits X-j from the LSB of
supplied to The multiplier 21 loads the content am of the am register 13 in response to the control trigger pulse CLK2 from the control block 23, and multiplies the content am by X-j from the X shift register 17 in response to the control trigger pulse CLK2. Let's do it.

Then, the multiplier 21 calculates the LSB (AX-j) of the product.
Output. As is well known, this AX-j is the L of the addition result of the upper bit string of AX'j-1 output last time and the bit string indicating the current 1×2 bit multiplication result.
It is SB. That is, in the multiplier 21, when the above addition result is obtained, it is shifted to the right by 1 bit, the serial output bit is used as AX-j, and the remaining bits are internally used for addition with the next 1×2 bit multiplication result. Retained. In the X shift register 17, when the contents held therein are shifted to the right by one bit by the control trigger pulse CLK2, the held bit of the flip-flop 19, ie, the sign bit S, is input to the MSB thereof.

On the other hand, the control trigger pulse CLK from the control block 24
3 is supplied to X shift register 18 and multiplier 22. As a result, the X shift register 18 starts a downward shift operation (right shift operation). The serial output bit Y- from the LSB of X shift register 18 is provided to multiplier 22. The multiplier 22 is connected to the control block 24
The content bm of the bm register 14 is loaded in response to the control trigger pulse CLK3 from the control trigger pulse CLK3, and the content bm of the bm register 14 is multiplied by Y' from the X shift register 18.
Do so accordingly. The multiplier 22 then calculates the LSB of the product.
(BY”k) is output.

In addition, the control trigger pulse CLK from the control block 25
1 is supplied to the e shift register 26. This allows e
The shift register 26 starts a downward shift operation (right shift operation). The serial output bit Ei from the LSB of the e shift register 26 is sent to the flip-flop 27.
The signal is temporarily held, subjected to timing adjustment, and supplied to the adder 31 as E'i. The B input of the adder 31 is supplied with the serial output bit AX'j from the multiplier 21.

Therefore, in the adder 31, (E
'-i+AX-j) is temporarily held in the flip-flop 32, subjected to timing adjustment, and supplied to six inputs of the adder 34. The B input of the adder 34 is connected to the multiplier 22
The serial output bit BY-k is once held in the flip-flop 33, subjected to timing adjustment, and then supplied. Therefore, the addition result of 34 adders 34 is R”m
(E -i + AX -J 1BY -k) is U
It is serially input to the MSB of the shift register 35.

The above operation is repeated, and the addition result R of the adder 34 is
The serial input to the U shift register 35 of IIl is p+
When it is repeated q (=48) times, the contents of the shift register 35 at that time are the required U (=a・x+b−y+e
). Note that in this embodiment, the U shift register 3
5, but the upper p (=40) bits, that is, the data U' of the integer part is used as the result. That is, in this embodiment, q (=8) bits of the fractional part are used to improve the precision of the calculation.

Now, the serial output bit E1 from the LSB of the e-shift register 26 is also input to the MSB of the same register 26. That is, the e shift register 26 receives the control trigger pulse CL.
The rotation is shifted according to K1. Therefore, the control trigger pulse CLK1 of 1) 10 (=48) from the control block 25 causes the
When the rotational shift is performed p+q times in step 6, the content at that time becomes e. In this case, there is no need to set e in the e shift register 26 again in the calculation of the next pair of X and y. Of course, an e register (similar to the ae register 15 and bem register 16) is provided to hold e,
If necessary, the data may be loaded from the e register to the e shift register 26.

As described above, according to this embodiment, by using the matrix multiplier shown in FIG. 1, it is possible to calculate U (=a=22-.x+by10e). Also the first
The matrix multiplier shown in the figure is v (=c −x0d・y+f
) can also be used for calculation. In this case, the am register 13 may be used for the cm latch, the bm register 14 for the 6m latch, the ae register 15 for the ce clutch, the be register 16 for the de clutch, and the e shift register 26 for the f latch. Similarly, the multiplier 21 is set to cm
The multiplier 22 may be used to multiply dm and y, and the U shift register 35 may be used to latch V. In this case, regarding the calculation operation, a, b, e, and u are replaced by c, d, and f in the explanation of the operation of U calculation described above.

I would like it to be read as ■. Further, by providing two matrix multipliers shown in FIG. 1, one for calculating U and one for calculating V, it is also possible to calculate U in parallel.

In this case, there may be only one set of the X register 11 and the X register 12. It is also possible to use the matrix multiplier shown in FIG. 1 alternately for calculating U and (2). However, in this case, am register 13, bm register 14, ae
Register 15, be register 16, e shift register 2
It is necessary to set data to 6 each time U or V is determined.

Note that the matrix multiplier according to the present invention is applicable not only to coordinate transformation in graphic processing but also to multiplication of row vectors and column vectors in general arithmetic expressions such as the one expressed by equation (1).

[Effect of the invention] As detailed above, according to the present invention, a, b.

A row vector consisting of three elements e (a, b are constant terms and real numbers, e is a constant term and fixed point number), and X, V
, 1 (X, y are variable terms and integers) and a column vector consisting of three elements, and the product-sum operation represented by a x b - y e can be performed at high speed with a simple hardware configuration. I can do it.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a matrix multiplier according to an embodiment of the present invention, FIG. 2 is a diagram explaining the invention in detail, and FIG. 3 is a timing chart for explaining the operation. 11...X register, 12...X register, 13.
...am register, 14...bm register, 17...
・X shift register, 18...y shift register, 2
1.22... Multiplier, 23-25... Control block, 26... e shift register, 31, 34... Adder, 35... U shift register.

Claims (2)

[Claims] (1) am x 2^a^e^-^m, bm x 2^b^e^
Constant terms a, b expressed as -^m (am, bm are l-bit integers expressed in two's complement, ae, be, m are 0≦
ae, an integer satisfying be≦m) and a constant term e (e is 2
A row vector consisting of three elements, variable terms x, y (x, y are 2-bit integers expressed in 2's complement), A matrix multiplier that performs a product-sum operation represented by a, x + b, y + e, which is a product of a column vector consisting of three elements with a fixed value of 1, and an am register that latches the above am and an am register that latches the above bm. bm register; a first control means that performs counting according to the basic clock signal when the operation starts, and repeatedly generates a first control trigger pulse synchronized with the basic clock signal when the difference between the m and q is counted; At the start, counting is performed according to the basic clock signal, and when the ae is counted, a second control trigger pulse is repeatedly generated in synchronization with the basic clock signal.
a control means, a third control means that performs counting according to the basic clock signal at the start of operation, and repeatedly generates a third control trigger pulse synchronized with the basic clock signal when the above be is counted; and a third control means that latches the e. , a first shift register that shifts the contents downward in response to the first control trigger pulse from the first control means, and a first shift register that latches the x and transfers the contents to the second a second shift register that shifts downward in response to a control trigger pulse; and a third shift register that latches the y and shifts its contents downward in response to the third control trigger pulse from the third control means. a 1×l register, for performing multiplication of the serial output bit from the second shift register by the contents of the am register in response to the second control trigger pulse from the second control means;
a first bit multiplier and a 1×l bit for performing multiplication of the serial output bit from the third shift register by the content of the bm register in response to the third control trigger pulse from the third control means; a second multiplier of
and addition means for adding the least significant bit of the multiplication result output from the second multiplier for each multiplication operation and the serial output bit from the first shift register. matrix multiplier. (2) The first control means generates the first control trigger pulse p+q times, the second control means generates the second control trigger pulse k+l times, and the third control means generates the third control trigger pulse p+q times. The matrix multiplier according to claim 1, characterized in that the pulse is generated k+l times.