JPS61250874A - Magnetic disc device - Google Patents

Abstract

PURPOSE:To increase the disc capacity at formatting by inputting an OR between a logic value of the 2nd logical value storage circuit and a sector pulse to a control circuit and deciding the access to the next sector when the data is accessed based on the 1st logical value storage circuit. CONSTITUTION:When a host computer side outputs a reset signal to reset a mode flip-flop 1 thereby bringing the initial state of an SCTINH signal to an H level, a SCTP signal 1 becomes an SCTP signal 2 through an AND gate 6 and a control circuit 7 reads the address part of a sector at its leading. When an object address is obtained, a DACS is set, the OR of an AND gate 2 is established, the SCTINH signal goes to L and read or write from/to a disc is performed. Even when the address to the data part is finished and the next SCTP signal 1 is outputted, since the SCTINH signal is at L level and then neglected. On the other hand, the SCTINH signal is reset at the trailing of the SCTP signal 1 and te next SCTP signal 2 applies access to the address part.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a magnetic disk device (hereinafter referred to as l-IDD).

[Technical Blue Use of Invention].

In general, a sector of a disk format in an HDD has a gap G corresponding to the read cycle time of the program and the switching time of the read/write operation of the magnetic head, as shown in FIG. It consists of a data byte (hereinafter referred to as a data section) D.

By the way, there are two types of switching time of the magnetic head described above: a switching time from write to read, and a switching time from read to write.

Note that switching from write to read occurs when accessing a sector, and the time required for this is called write recovery time.

This write recovery time is generally 10μsec.
Above, if the data transmission speed to the disk is 1sec
Assuming 1.2 Mbits per c, a gap of about 13 bits or more is required.

In an HDD with a sector format determined in consideration of the above-mentioned facts, if the data transfer rate on the system side is slower than the transfer rate to the disk, the address part of the disk is not allocated consecutively, for example. By using a buffer to reduce the data transfer speed on the system side, even when transferring data of two or more sectors,
This prevents so-called "rotation waiting" from occurring. By the way, in such an HDD, when accessing the disk, it is necessary to read out data in the address section continuously.

[Problems with the Background Art] However, in the HDD as described above, the address section of the disk is not allocated consecutively, and therefore the data section of the disk cannot be accessed continuously.

For this reason, each sector must include a gap corresponding to the write 1 to recovery time, and there is a problem in that the disk capacity at the time of A-matte is relatively reduced.

[Purpose of the Invention] The present invention has been made to solve the problems of conventional HDDs as described above. The purpose of the present invention is to provide an HDD that achieves a relative increase in disk capacity during formatting by controlling so that there is no need to provide a gap to ensure the storage capacity.

[Summary of the Invention] That is, the HDD of the present invention is a magnetic disk device in which writing and reading of data on a disk is controlled by a hard sector method, in which either a read gate or a write gate is opened by inputting a sector pulse, and a sector is opened. a control circuit that outputs an access instruction signal that instructs access to the data section; a first logic value holding circuit that stores a logic value that indicates whether sector addresses are continuously assigned; a second logical value holding circuit that is set by the logical sum of the logical value held in the first logical value holding circuit and the logical value of the access instruction signal outputted by the control circuit and reset by the sector pulse; a logical sum signal of the logical value held in the second logical value holding circuit and the sector pulse is used as a sector pulse input of the control circuit, and the control circuit is configured to hold the first logical value. The present invention is characterized in that, after accessing the data portion of the sector based on the state of the circuit, it is determined whether or not to access the sector located next to the sector.

[Embodiments of the invention] DESCRIPTION OF THE PREFERRED EMBODIMENTS Details of embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of essential parts of an embodiment of the present invention.

In the figure, 1 is a MODE flip-flop that stores the control mode according to instructions from the host computer, and 2
is an AND gate, and a sector inhibit flip-flop (IJ, bottom, 5CTI
NI- (referred to as a flip-flop) 4 is an OR gate that takes the logical sum of the clear pulse and the output of the OR gate 5;
6 is an AND gate that takes the AND of the 5CTINH signal output from the 5CTINH flip 70 block 3 and the output of the 6R gate 5; 7 is the format timing control for the disk; A control circuit that controls data access and generates read gate timing pulses, write gate timing pulses, write clock pulses, etc. is shown.

FIG. 2 is a timing chart showing the relationship between signal levels in each part of FIG. 1.

First, in accordance with FIG. 2, a case will be explained 1' in which allocation of address portions of sectors of a disk is performed continuously.

In the following, it is assumed that each sector includes a gap corresponding to the write recovery time from when the write gate closes to when the read gate opens, and the case where a write operation is performed to the data portion of the sector will be explained. .

First, when the combi coater outputs a mode set signal, the MODE flip-flop 1 becomes set. At this time, the SCT I NH flip-flop 3 is not set. In addition, a logical sum signal (hereinafter referred to as 5C) of the index pulse and sector pulse is output from the OR gate 5.
(referred to as TP1 signal) passes through AND gate 6 to 5CT
This becomes the P2 signal.

This 5CTP2 signal is input to the control circuit 7, but the second
As shown in the figure, the 5CTP2 signal is activated by the header access flag (hereinafter referred to as HA) in the control circuit 7 at its leading edge (rising edge).
C8) is set, and the read gate is opened by setting HAC8. As a result, the control circuit 7 reads the address part of the sector, searches for the target address, and when the target address is found, sets a data access flag (hereinafter referred to as DAC 8).
Access the data section. Furthermore, the control circuit 7 is D
Open the light gate based on AC8 Sera 1~.

When the access to the data part of the sector is completed, the HAC 8 is set again by the next sector pulse, and the address part is accessed.

The time T shown in FIG. 2 corresponds to the write recovery time, which in this case is ensured by being included in each sector.

Next, the case where a sector is accessed without considering the write recovery time will be explained with reference to FIG.

In this case, the host computer first outputs a mode reset signal to reset the MODF flip-flop 1, and sets the initial state of the 5CTINH signal to the "H" level. Therefore, the first 5CTP signal 1 is A
5CTP (i number 2) passes through the ND gate 6, and HAC8 is set by the leading edge (rising edge) of the 5CTP signal 2 as in the previous example, and the read gate is opened by this setting of HAC8.As a result, the control circuit 7 reads the address part of the sector, searches for the target address, and sets DAC8 when the target address is found.When DAC8 is set, a logical sum is established in AND gate 2, and the 5CTINH signal goes to "L level." When the DAC 8 is set, the read gate or write gate for the data section is opened, and a read or write operation to the disk is performed.

When the access to the data section is completed and the next 5CTP signal 1 is output, the 5CTINH signal is at "L level", so the logical sum is not established in the AND gate 6, and the 5CTP signal 1 is ignored. Ru. Therefore, the sector located next to the sector in which the data portion was accessed is not accessed.

On the other hand, since it is reset at the trailing edge (falling edge) of the SCT-P signal 1, when the next 5CTP signal 2 is generated, the HAC8 is set again and the address section of the next sector is reset. is accessed.

In this way, in the HDD of this embodiment, by resetting MODE flip-flop 1, it is possible to secure the write recovery time T for one sector or more, and when determining the byte length of one sector, write recovery It becomes unnecessary to set a gap in consideration of time T.

[Effects of the Invention] As described above, the present invention includes a control circuit that opens either a read gate or a write gate in response to a sector pulse input and outputs an access instruction signal instructing access to the data portion of the sector; a second logical value holding circuit that is set by the logical sum of the logical value that continuously assigns sector addresses and the logical value of the access instruction signal output by the control circuit and is reset by the sector pulse; , the logical sum signal of the logical value held in the second logical value holding circuit and the sector pulse is used as the sector pulse input of the control circuit, and the control circuit operates based on the state of the first logical value holding circuit. After accessing the data portion of a sector, it is determined whether or not to access the sector located next to the sector, so even if disk addresses are not allocated consecutively, There is no need to provide a gap in the sector to ensure write recovery time, and as a result, the disk capacity at the time of formatting can be relatively increased.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of the main parts of an embodiment of the present invention, and Fig. 2 shows the signal level relationship of each part when sector address allocation is performed continuously in an embodiment of the invention. FIG. 3 is a timing chart showing the signal level relationship of each part when write recovery time is not taken into account. FIG. 4 is a diagram showing the sector contents of a general 1" DD disk format. 1・・・・・・・・・MODE flip-flop 2.6
...AND gate 3...SCT lNl-1 flip-flop 4.5...OR gate 7...Control circuit

Claims (1)

[Claims] (1) In a magnetic disk device in which writing and reading of data to and from a disk is controlled by the hard sector method, access is performed by opening either the read gate or the write gate by inputting a sector pulse and instructing access to the data portion of the sector. a control circuit that outputs an instruction signal; a first logical value holding circuit that stores a logical value indicating whether or not sector addresses are continuously allocated; a second logical value holding circuit that is set by a logical sum of the logical value of the access instruction signal output from the control circuit and reset by the sector pulse; A logical sum signal of the logical value held in the logical value holding circuit and the sector pulse is used as a sector pulse input of the control circuit, and the control circuit controls the sector pulse based on the state of the first logical value holding circuit. A magnetic disk device characterized in that, after accessing a data portion, it is determined whether or not to access a sector located next to the sector.