JPS61250751A - Information processor - Google Patents

Abstract

PURPOSE:To improve remarkably the utilizing efficiency of a ROM by dividing a data into a high-order bit and a low-order bit and storing the low-order bit into the ROM as one word in the lump. CONSTITUTION:In taking an address where the high-order M-bit and the low- order (N-M)-bit of the i-th word of a data are stored in a memory device as Ai and Bi respectively, the data is stored in the memory device in the relation of Bi=[W/2+(N-M)/M.Ai], where [ ] indicates a Gauss' symbol. The address Bi is formed by shifting the address Ai right by [logz(N/(N-M))] bits and giving '1' to at least one bit including the most significant bit by an address forming device. The low-order bit is stored in the ROM as one word in the lump so as to improve remarkably the utilizing efficiency of the ROM.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to an information processing device, and particularly to an information processing device that reads a memory,
It relates to things that perform various processes based on read data.

(Prior Art) In recent years, information processing devices have come to perform sophisticated processing along with advances in semiconductor technology. An example of such an information processing device is a one-chip microprocessor (hereinafter referred to as a microcomputer).

A block diagram is shown in FIG. 14, and the operation will be explained.

The ROM 2 is read out according to the address information generated by the program counter 1. The ROM 2 is usually called an instruction ROM and stores in advance instructions to be executed by the microcomputer. Based on the data output from ROM2, AlO2, RAM4. The l105 exchanges predetermined data at a predetermined timing and performs information processing. For example, Intel's microcomputer 8049 corresponds to this. In Intel 8049, ROM2
Reading is performed in units of 8 bits, with 8 bits for short instructions and 16 bits for long instructions. In this case, two consecutive words of data are read.

(Problems to be Solved by the Invention) However, in the above configuration, even if the required data length is, for example, 12 bits, 16 bits of data will be read. Conversely, ROM2
In this case, when 12 bits of data are stored, 4 bits are wasted.

In view of the above problems, the present invention provides an information processing device that improves the efficiency of ROM usage.

(Means for solving problems) One aspect of the present invention is to solve the above problems.

Let Ai and Bi be the addresses where the upper M bits and lower (NM) bits of the first word of data are stored in the storage device, respectively, where [] is a Gaussian symbol, and [] Represents the integer part of the number in .

It has a storage device in which the above data is stored.

The above address Bi is the above address Ai.

At least 1 bit shifted right and including the most significant bit
It has an address generator that creates an address by adding 1 to a bit.

(Operation) The present invention uses the above-described configuration to divide data into upper bits and lower bits, and stores the lower bits together in the ROM as an l word. This results in fewer or no unused bits.

ROM utilization efficiency can be significantly improved.

(Example) An embodiment of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram when the information processing device according to the present invention is used in an electronic musical instrument. To explain this Figure 1, 1
-1 is a keyboard. Reference numeral 1-2 is a tablet, and is an operation section for instructing the selection of tones of musical tones output from five electronic musical instruments. Reference numeral 1-3 denotes an effect switch, which controls various effects on musical tones 1, such as turning on/off effects such as vibrato and tremolo. (2)-4 is a microcomputer, and 5 corresponds to, for example, Intel's microcomputer 8049. Reference numeral 1-5 denotes a musical tone generating section, which performs waveform calculations and frequency calculations based on control signals given from the microcomputer 1-4. Reference numeral 1-6 is a data bank, which is a ROM (read-only memory) that stores waveform data and envelope data used in the musical tone generator 1-5. Reference numeral 1-7 is a filter, which is a ROM (read-only memory) that stores waveform data and envelope data used in the musical tone generator 1-5. -5 removes the aliasing noise of the musical tone signal output from the 5. 1-8 are speakers.

Next, the operation of the electronic musical instrument shown in FIG. 1(a) will be explained. The microcontrollers 1-4 follow the instructions written inside them in advance.
Keyboard 1-1. The states of the tablet 1-2 and the effect switch 1-3 are sequentially searched. Also, the microcomputer 1-4 is the keyboard 1-1
It sends an assignment signal that allocates the chord of the pressed key to a plurality of channels of the musical tone generator 1-5 based on the 0N10FF state of the key, and also sends out an assignment signal that allocates the chord of the pressed key to a plurality of channels of the musical tone generator 1-5 based on the state of the tablet 1-2 and the effect switch 1-3. and sends control data. In the musical tone generating section 1-5, the assignment signal and other control signals sent from the microcomputer 1-4 are taken into internal registers, and based on these signals, necessary waveform data and envelope data are generated from the data bank 1-6. The musical tone signal is synthesized while reading out.

The musical tone signal synthesized in this musical tone generating section 1-5 is
The signal is sent through a filter 1-7 to a speaker 1-8 to generate musical tones.

FIG. 1(b) shows a timing diagram when data is transferred from the microcomputer 1-4 to the tone generator 1-5. Further, Table 1 shows the contents of data sent from the microcomputer 1-4 to the tone generator 1-5. In Table 1.

NOD is note octave data, and note data ND, octave data OCT, and key-on data Ko
It consists of n. The specific details are shown in Table 2.
Table 3 shows the bit configuration of note data NO.
Table 4 shows the correspondence between octave data OCT and pitch range. That is, if you want to output the 6th octave tone of the note G# (hereinafter abbreviated as G#6) to the musical tone generator 1-5 from channel 1, the address in FIG. 1 (b) is 00000.
001, 10011110 as data to microcontroller 1
-4 will be sent.

Next, PDD is pitch detune data, which is 8-bit data for shifting the tuning. PDD is expressed in two's complement notation, and the variable range is -128 to +12.
There are 256 ways of 7. RLD is release data, which is 4-bit data that controls the attenuation characteristic after key-off. VOL is the volume flag, and this bit is set to '
When set to 1'', it is possible to control the output level of the musical tone signal from the musical tone generating section 1-5 in accordance with the volume data VLD described later.DMP is a damper flag, which controls the attenuation after key-off in the case of a piano type envelope. This is a flag that causes rapid attenuation, and functions when DMP = 1. SQL is a solo flag, and when a musical tone with the same note name as another channel is assigned, the musical tone that is occurring in that channel and the tone that is about to be generated are This is a flag that selects whether or not to match the phase characteristics of the musical tones.

When 5QL=1, phase matching is canceled.

TAB is tablet data, and the data specified by tablet 1-2 in FIG. 1 is stored in these 5 bits. PE is a pitch extent flag, and a pitch extent is applied to the channel for which this bit is set to '1'.VLD is volume data, and together with the volume flag VOL mentioned above, the level of the musical tone output from the channel is determined in 8-bit detail. This series of data can all be set independently for each channel.

Next, the calculation sequence in the tone generating section 1-5 will be explained.

Tables 5 and 6 show the calculation sequences of the tone generator 1-5. In this musical tone generating section 1-5, the calculation sequence has two modes, an initial mode and a normal mode, in order to process more data in a short calculation cycle, and furthermore, the above two modes are a long sequence and a short sequence, respectively. It is divided into Furthermore, the initial mode short sequence and normal mode long sequence each have two states: EVEN and ODD.

In the initial mode, the microcomputer 1-4 is connected to the musical tone generator 1-5.
When a command is given to generate a new musical tone, the musical tone generating section 1
This is a mode for initializing various registers, etc. for the channel specified by the microcomputer 1-4 in -5.It starts with a long sequence, and after performing a short sequence twice, it enters the normal mode. The first of the two short sequences in this initial mode is ODD.

The second time will be the EVEN short sequence. After this initial mode ends, the mode shifts to normal mode, where one long sequence comes after six short sequences.

In this embodiment, two independent waveforms and two independent envelopes are multiplied together for each channel, and it also has a fine pitch adjustment function. In order to perform arithmetic processing for eight channels in a time-sharing manner, a large number of arithmetic steps are required. Therefore, short sequences are those that must be computed in short cycles, and long sequences are those that are infrequently computed, that is, those that can be computed in long cycles.

By inserting long sequences between short sequences, calculation efficiency is improved.

Figure 1 (C) shows the timing diagram of the short sequence and long sequence. As shown in Figure 1 (C), the short sequence consists of 11 time slots (0) to (10), and the long sequence (11)～(
19) consists of 9 time slots, each time slot is 250 ns, and is divided into 4 and divided into ψ1.
The entire system operates with a non-overlapping two-phase clock of ψ3.

What is the relationship between short sequences and long sequences?

Every time the short sequence is repeated eight times from channel 0 to channel 7, a long sequence for one channel is inserted. Therefore, 1 For example, the short sequence on channel 3 is 1 every 97 timeslots of 11X8+9.
The long sequence will appear once every 776 timeslots (97×8). In addition, there are two long sequences in normal mode: EVEN and ODD.
Because there are two states? The system operates on a cycle of 1552 time slots of 76x2.

Next, individual calculation sequences will be explained based on Tables 5 and 6. As mentioned above, the musical tone generator 1-5
Since this starts from the initial mode long sequence when a new key is pressed, we will explain each time slot starting from the initial mode long sequence.

+ (13) PDD + PHI) → PDR (1
5) O→ TRI (16) O→ TR2 (17) O-* ZRI (18) O→ ZR2 The meaning of time slot (13) is to add the contents of the register PDD and the contents of the register PRO. This means that it is stored in a register called PDR. Time slots (15) to (18) are TRI.

This means writing O to the registers TR2, ZRI, and ZR2.

Data Bank Mishiku 12) wTD −+ HAD 4 HAD
(14) HAD 4 C0NT 4 C0NT
, DIFI(16)~(17) HAD 4 STE
4 EARI What these mean is that if the data on the left end (for example, time slot (14)) is HAD
The data C0NT written in the center is read out from the data bank 1-6 using the address (data) as an address, and is stored in the register C0NT and DIFI with the name at the right end.

(1) PDR+ JD L, B, ; O→ER
2/1(3) ORG +OCT + 1-* VB2
−eΔvAR(4) D, B, + EARI→EA
R2(6)0 →IIIRI (8) O-4ER1 (9) O-4WE2 (10) O-+ IIEI, 0-4ER2/1 in llR2 time slot (1) is ER2 at the first time of the shift sequence, that is, ODD, 2nd time i.e. E
At the time of VEN, it means writing O to a register called ERI. Again, 8. This means that the PDR+JD operation result is not stored in a register, but is sent to a multiplier (described later) via an L path (described later). In time slot (3), it means that the calculation result is stored four times in the register WE2, then decoded and stored in ΔWAR. 0, B in time slot (4),
means to send a value obtained by a data bank reading unit (described later) to an adder via a D bus (described later) via a register or the like.

The above C and B mean that the result obtained in the addition section is input directly to the multiplication section without going through the register, and in this case, the PDlt obtained in time slot (1)
+ means the calculation result of JD.

- One tabankomishi 1) IIAD → ΔSTf! →A, B.

(3) ~ (4) EARI/2 → El/2 → ΔTl/
2. ΔEl/2゜ΔZl/2 (6) to (7) HAD 4 STW/ΔSTw −
+ STW/υAR where A of time slot (1)
, B means that the value obtained by reading the data bank is input directly to the A input of the adder via a register or the like. In addition, STV/ΔS+1−+STw/vAR of time slots (6) to (7) is such that at the first time of the short sequence, that is, 000, the data STv is read out and stored in the register STV, and at the second time, that is, EVEN, the data is ΔSTw. Read data and WA
This means that it is stored in a register called R.

Next, the normal mode will be explained.

In the normal mode short sequence table 6, the parts marked with a red mark are those whose calculations are performed only in the short sequence that starts after the note clock is generated, and the flag that controls this operation is set to the calculation request flag CLRQ. I'll call you.

迦Jl (1) 1IE2 + WE! 1 4
L,B.

(2) STV + WAR-+D, B, ,
B, B.

(3) ZRI + ΔZl 4ZR1(
4) DIFI + C, B, → D
,B.

(5) ERI + ΔEl + Ci −4E
RI(6) ZR2+ ΔZ2 →ZR2(
7) MAR+ ΔIt! AR4VAR*(8)
ER2+ ΔE2 + Ci −+ ER2(9)
FR+ CDR-4CDR Fist Here, the time slot (1), B, means that the calculation result is directly input to the multiplication section without going through the register. Time slot (
2) Nori, B, B, B similarly means that the calculation result is directly input to the B input of the data bank reading section and addition section. C, B in time slot (4),
means that the calculation result of the adder is directly input without going through a register, and in this case, the calculation result of STV + wAR in time slot (2) is input. Also, 0. B.

means that the calculation result is directly input to the data bank reading section. Ci in time slots (5) and (8) means adding the carry of operations in time slots (3) and (6), respectively.

Mi 1ri (1) ~ (3) VH2+ ER24VE2m (4
) ~ (6) C, B, X CN → (DAC) (
7) ~(9) WRI X ERI −+ VE
1*Here, C, B of time slots (4) to (6),
means that the output of the adder is directly input to the multiplier without going through a register or the like. In this case, the timeslot (
This corresponds to the calculation result of VH2+wEI in 1). Also(
DAC) indicates that this calculation result is input to a DAC (OA converter; described later).

Data Bank Beautiful 4) ~(5) C, B, -+ 11 →
WR1*(7) ~(8) C, B, + +1
1 → VR2*Here, time slots (4) to (5
) means that the calculation result of the adder is directly input to the data bank reading unit and used as the address of data bank 1-6, and in this case, 5TII + of time slot (2) in the adder. This corresponds to the calculation result of vAR. Similarly, time slots (7) to (8) C and B are also equal to time slot (4) DIFI + (STw+M
This corresponds to the operation result of AR).

(13)ΔTl/2 +TRI/2 →TRI/
2(14) PDR+ JD
-) L, B.

(15) ΔEARI/2 + EARI/2 +
Ci → EARI/2 (16) PDD + PE
D-4PDRHere, time slot (14), B, is the calculation result of the adder, that is, P
This means that the value of DR+JD is input directly to the multiplication section without going through a register. Ci in time slot (15) means a carry resulting from the operation in time slot (13).

Rice plate (16) to (18) CN + C, B, → FR Here, C, B means that the calculation result in the addition section is directly input to the multiplication section without going through a register, and in this case, The calculation result of PDR+JD in the adder time slot (14) is input.

Look at the data bank.

(14) ~ (15) EAR2/1→E2/1→ Δ
T2/1°AE2/1. AZ2/1 Here, 2/1 means 2 at the odd numbered time, that is, 000 (for example, R2 for R2/1), and 2 at the even numbered time, that is, E
At VEN, it means 1 (E1), and EVE
N, ODD means reading another data and storing it in another register.

FIG. 2 is a detailed diagram of the musical tone generator 1-5 in FIG. 1(A). First, the functions of each block will be briefly explained using this figure. 2-1 is a master clock, and here the one with f = 8.00096 MHz is used.

2-2 is a sequencer (hereinafter referred to as SEQ) which divides the frequency of the clock signal generated by the master clock 2-1.

Sequence signal (hereinafter referred to as S) in the entire musical tone generating section 1-5
It generates a Q-fold signal) and various control signals. 2-3 is a microcomputer interface unit (hereinafter referred to as UCIF), which transfers various data shown in Table 1 to the microcomputer 1-4.
Although this data is sent out asynchronously with the musical tone generator t-S, this circuit takes in this data and synchronizes the SQ multiplied signal generated by SEQ. Furthermore, a flag INr for instructing mode switching between the initial mode and the normal mode is generated by the flag Kon.

2-4 is a comparison register section (hereinafter referred to as CDR);
The 8 channels of the register CDI shown in the calculation sequence are compared with the 10-bit branch signal obtained by successively dividing the master clock, and note clocks for 8 channels and calculation request flag CLRQ are generated.

Reference numeral 2-5 denotes a random access memory section (hereinafter referred to as memory) which stores the results of various calculations performed within the musical tone generating section 1-5. 2-6 is a part of a full adder (hereinafter referred to as FA), which includes a 16-bit full adder for adding various data. 2-7 is a multiplication part (hereinafter referred to as MPLY), (12 bits of 2's complement) X (absolute value 10 bits)
It has a multiplier that performs calculations. 2-8 is a digital-to-analog converter (hereinafter referred to as DAC).

Digital musical tone data output from MPLY2-7 is converted into analog musical tone data. 2-9 is an analog buffer memory section (hereinafter referred to as ABM), and DAC2-
Musical tone data generated at machine cycle intervals from 8 is C.
The function and structure of the ABM 2-9, which performs the conversion to pitch synchronization using the note clock generated by the DR 2-4, are similar to the analog buffer memory disclosed in Japanese Patent Application Laid-Open No. 59-214091. 2-10 is an input/output circuit unit (hereinafter referred to as I10), which sends an address signal to the data bank 1-6, reads out waveform data and envelope data corresponding to the address signal, and reads out the data as necessary. 2-11 is a matrix switch unit (hereinafter referred to as MS) which performs data conversion of the stored data, and a horizontal path line (HA) connected to IJCIF 2-3, CDR 2-4, and memory 2-5.

JIB, HC, HD, HE, HL paths) and F
This is a circuit that connects the vertical path lines (A, B, C, D, and L buses) connected to A2-6, Aply2-7, and Ilo2-10 according to the SQ multiplication signal. . These circuits execute the operation sequences shown in Tables 5 and 6.

Next, individual blocks will be explained.

FIG. 4 is a detailed diagram of 5EQ2-2 in FIG. 2.

4-1 is a counter which divides the frequency of the master clock and generates various timing signals shown in FIG. 1(C).
TS is a signal representing the time slot in Figure 1 (C), CI (C is a channel code,
This is a signal representing the channel number in (c). E
v is a signal representing 00 units and EVEN in the calculation sequence, EV=O is ODD, EV=1 is EVEN
means. 4-2 is SQROM (sequence ROM
). A signal TS representing a time slot and a flag INI are input to the address input of the SQROM 4-2, and various control commands for each time slot are generated based on these inputs. 4-3 is logic/7'
- The output from the SQROM 4-2 is further controlled by various flags, calculation request flag CLRQ, etc., and according to the instructions of the SQ double signal performance information, effect switch 1-3, etc.

It generates a signal (abbreviated as SQ in the figure) that instructs how each functional block should operate for each time slot.

FIG. 5 is a detailed diagram of LICIF2-3. In FIG. 5, 5-1 is a latch, which latches A/DOs O to 7 given by the microcomputer 1-4 in FIG. 1 by ALE. Since the relationship between A/D O-7 and ALE is as shown in FIG. 1(b), the addresses shown in Table 1 are latched in latch 5-1. 5-2 is a latch, which latches A/DO to 7 given from the microcomputer 1-4 by a pin. The relationship between A/D O~7 and Toshi is the first
As shown in Figure (B), the latch 5-2 has the first
The data shown in the table is latched. 5-3 is a latch, which is controlled by 萱 and latches the output of latch 5-1. The reason why the address is latched in two stages in this way is that ALE periodically becomes 1'' regardless of everyone, and by latching the address in two stages in this way, it is possible for the station to write new data. Latch 5- until done
3. Addresses and data are stored in the latches 5-2, respectively. 5-4 is 1 word 8 bit RA
A is an address input, OE is an output control terminal, and the data terminal is connected to the HE bus. Here, when 0E=1, the data at the address given by the six inputs is output from the D terminal. Also, WE is a write control terminal, which writes the data given to the D terminal when IIH=1 to the address given by the A input, OB, 1
111! is controlled by the SQ multiplication signal. RAM5
-4 shows various data (NOD, PDD) shown in Table 1.
, RLD-VOL-DMP-SQL, TAB
-PH, VLD) and control data C0NT (
Write from data bank. (Details will be described later), data PDR of the pitch data register is stored for each eight channels. 5-5 is a selector, and microcomputer 1-
The address specified by 4 and the address specified by the SQ multiplication signal.

It selectively outputs another SQ multiplied signal and applies it to the A input of the RAM 5-4. 5-6 is a signal processor, +
It is connected to the 111' bus, takes in data on the bus, and generates various flag signals. In addition, release data RLI sent from microcontroller 1-4) 1 according to the 4 bits
Generate 6 types of release envelope data and
Send E-Bas. 5-7 is the gate.

In response to the SQ multiplication signal, the output of the latch 5-2, that is, the data from the microcomputer 1-4, is sent onto the IIE bus.

Next, the operation of UCIF2-3 will be explained.

Assume that the data shown in Table 1 is given from the microcomputer 1-4 at the timing shown in FIG. 1 (b).

Assuming that address 05□1 data is 891, ie, instructs channel 5 to press F#1, the address is first latched into latch 5-1 by the ALE signal.

Next, the data is latched into the latch 5-2 by the ■ signal, and at the same time, the address is latched into the latch 5-3.
Then, at a predetermined timing, the selector 5-5 activates the latch 5-.
3 output is selected, gates 5-7 are opened at the same time, and R
A write signal is given to the WH of AM5-4. This write signal gives the HE bus the data latched in the latch 5-2, that is, the data that the microcomputer 1-4 attempted to write, that is, 8916, and the six inputs of the RAM 5-4 receive 05□, which is the output of the latch 5-3. is given, so
Data 89□6 is written to address 05 of RAM 5-4. In this way, the various data shown in Table 1 are RA! 1I5-4.

As shown in Table 1, flags such as the VOL 7 lag and PE flag are written in the RAM 5-4, and these flags are sent to the signal processor 5-6 via the HE bus, where they are processed. It is used after it is latched.

FIG. 6 is a detailed diagram of CDR2-4. Reference numeral 6-1 is a 10-bit branching unit that receives a master clock as an input.

6-2 is a RAM with a comparator (hereinafter referred to as CDRAM), which has 8 words with 1 word being 13 bits. A comparator is provided for the upper 10 bits of each word, and a comparison is made with the frequency division data input from the terminal T by the frequency divider 6-1. When all 10 bits match, a match signal is sent from the terminal C. is output. OE, wE, A.

The function of D is the same as that of the RAM 5-4 described above. 6-3 is a decoder, and the relationships among the A input, EN input, and D output are as shown in Table 8. 6-4 to 6-11 are RS latches, and when a positive pulse is applied to the S input, the Q output becomes °'
1”, when a positive pulse is applied to the R input, the Q output becomes t%O.
”. RS latch 6-4 is channel O, RS latch 6-5 is channel 1, etc. Match pulse is given to S. 6-12 is a selector, which is given to N input. One signal is selected from among the 8 signals by the 3 bits of the channel code CHC and outputted from D.
A latch 6-13 latches the SQ multiplied signal and therefore the output of the selector 6-12. 6-14 is a <ND gate.

Next, the operation of CDR2-4 shown in FIG. 6 will be explained. A divider 6-1 divides the master clock and provides a 10-bit divided output to the T input of the CDRAM 6-2.

Each word of the CDRAM 6-2 contains an arbitrary value, and every time the upper 10 bits of these values match the output value of the frequency divider 6-1, a match pulse is output from the C terminal.

Since COO, that is, a signal representing a channel is input to the N input of the CDRAM 5-2, each word corresponds to a respective channel, so a coincidence pulse is generated for each channel. Since each of these match pulses is input to the RS latches 6-4 to 6-11, the Q output of the RS latch corresponding to the channel where the match pulse is generated is set to 1''.RS latches 6-4 to 6-11. 6-11
One of the Q outputs is sequentially selected by the selector 6-12 according to the channel code CHC, and the latch 6-13
latched to. Since the output of latch 6-13 is given to <ND gate 6-14, currently selector 6-12
If the Q output of the RS latch selected by is '1', <
The SQ multiplied signal applied to the ND gate 6-14 causes the corresponding channel of the D output of the decoder 6-3 to become ``1'', and the Q output of the RS latch is reset to 0''.

FIG. 7 is a detailed diagram of the memory 2-5. Is it in Figure 7? -1~? -4 is RAM Te tomorrow, OE, W [! ,
The functions of A and D are the same as those of the RAM 5-4 described above. Here, RAM7-1 nitwAR, IEARI,
Δz1. AEI, %lE1. EARz.

ΔZ2. Ag3 (7) Each cash register is RAs7-2
Niha wR2, ZRI.

ΔTl, FR, AIIIAR, ZR2, Ar1 (7)
Each register.

RAM7-3 Ni4:1ER1, TRI, DIFI,
Dlll, ER2, TR2, STw.

Are the TAB' and IIAD registers RAM? −
In 4, the registers NOD' and WE2°VLD' each store 8 channels worth of data. In addition, NOD'
, TAB', and VLD' are the RAM5-4 memory cell N00. TAB, VLD17) data is written. 7-5 is a ROM of 10 bits per word and 13 words, in which note coefficients CN in the operation sequences shown in Tables 5 and 6 are stored.

Here, Q' is an output, A is an address input, and OE is an output control terminal, and when 0E=1, the contents of the ROM are output to Q.
When 0E=O, Q=high impedance. The values of note coefficient CN are as shown in Table 7. In addition, R
OM? The 10-bit output of -5 is connected to the lower 10 bits of the HD bus. 7-6 is a signal processor, R
A circuit that reads NO (note data) and 0CT (octave data) from NOD' stored in AM7-4 and generates pitch detune data PED based on these data and the PH flag, and reads data in register 'dE2. A decoding circuit is provided for decoding.

FIG. 8 is a detailed diagram of FA2-6. In Figure 8,
8-1 to 8-8 are latches, and ψ1.5EQ2-2 is generated. It operates with the φ3 signal. 8-9 is an adder, which adds the value given to the A input and the value given to the S input (
(both 16 bits) and the value given to the carry input Ci are added and output from C and Co. Co is a carry output resulting from the operation. 8-10°8-11 is a bit processing circuit, and latches 8-1.8-11 are bit processing circuits. This circuit performs bit manipulation of the output from the latch 8-2.

8-12 is a logic gate, which operates to forcibly set the output of the latch 8-6 to 1" or 'O" according to the SQ multiplication signal, or to output it as is; 8-13
is a RAM, and its size is 1 word with 9 bits.
It belongs to Ward. The functions of A, D, WE, and OE are the same as those of the RAM 5-4 described above. The D output 9 bits are connected to the lower 9 bits of the C bus.

RAM8-13 is a phase register for phase matching (described later), and performs phase management of individual waveform data read addresses (MAR) of 12 notes.

FIG. 9(a) is a detailed diagram of MPLY2-7. In FIG. 9, 9-1 to 9-9 are latches. Here, bits 7 to 9 of the L bus are stored in latch 9-3.
Bits 9 to 12 of the L bus are connected to bit 5. 9-10 is an encoder. The relationship between input and output is shown in Table 9. 9-11 is a shifter, which shifts the 16-bit signal inputted from ① according to the control signal inputted to C, and outputs it from 0.

The contents of the shift are shown in Table 10. 9-12
is a bit processing circuit, and according to the SQ multiplication signal, the latch 9-3
The decoder 9-13 performs bit processing on the signal outputted by the decoder, and the relationship between the input A and the output is as shown in Table 11. A selector 9-14 selects the 16 signals inputted to A if C=1 and B if C=O according to the SQ multiplied signal inputted to C, and outputs them from Y. Note that the lower 11 bits of the six inputs are connected to GND (ground potential) (that is, n Q n is given). 9-15 shifts a 14-bit signal input from the chic device in accordance with the control signal input to C and outputs it from O. The details of the shift are shown in Table 12. 9-16 is a multiplier that performs normal 12-bit x 10-bit operations in which the A input is 12 bits in complement representation, the B input is the absolute value lθ bit, and the output is 14 bits in two's complement representation. A 22-bit result is obtained, but the 14-bit output of the thermal multiplier 9-16 is 22 bits.
These are the upper 14 bits of the bits. Therefore 1 multiplier 9
The input/output relationship at -16 is as shown in the following equation.

Note that the multiplier 9-16 in MPLY2-7 uses a method of 1 or less in order to further simplify the circuit.

When constructing a normal multiplier, a multiplier with 12 bits of 2's complement value x 10 bits of absolute value can obtain an accurate 22-bit operation result using 116 adder cells.

However, in this system, only the upper 14 bits of the 22 bits originally obtained are used. That is, since the output of the lower 8 bits is not used, in this embodiment, the adder cells for the lower 7 bit calculation are all omitted, so that the calculation error due to the omission of the adder cell does not affect the LSB of the upper 14 bits. Therefore, in this multiplier 9-16, the adder cell 28 for low-order bit operations is omitted, and the configuration is as shown in FIG. 9(b).

In FIG. 9(b), similar cells are abbreviated within broken lines. Also, each block is a full adder.

The inputs are A, B, Ci (carry human power), and the outputs are sum S and carry Co.

FIG. 10 is a detailed view of Ilo 2-10. In FIG. 10, 10-1 to 10-8 are latches. here,
Latch 1O-3 is a latch with a set, and the input of the latch is D.
Connected to bits 7 to 9 of the bus. 10-
9 is a shifter selector which switches between A input and B input using C input and performs 1-bit shifting of 6 inputs.

10-10 is a bit processing circuit, which forcibly sets the lower three bits to '1' or '0' in accordance with the SQ multiplication signal. 10-11 is a decoder, and the relationship between input and output is as shown in Table 13. Decoder 10
-11's A input has bit 12 of the output of latch 10-7.
~Bit 15 is given. 10-12 is a selector which selects either the signal given to A or B according to the C input and outputs it from Y.

10-13 is a shifter which shifts the input from the machine according to the input from the control terminal C and outputs it from 0.

A noise circuit 10-14 mixes noise into the input data according to the noise flag NA.

FIG. 11(a) is a detailed diagram of MS+12-11. The part surrounded by a circle is the switch, specifically shown in Figure 11 (
As shown in b), it is composed of an Nch MO5FtET, and when the SQ multiplied signal becomes 1'', the MOSFET is turned on and the vertical line and horizontal line become conductive and data is transferred.In this MSl++2-11 In order to increase the speed, data is transferred after precharging all path lines with the ψ1 signal for each time slot immediately before data transfer.This is because the switch is Nch
This is to prevent the transferred data from dropping by the threshold voltage of the '11' level power tqosFEr since it is composed of MOSFETs.
FIG. 11 shows an example of a switch pattern used in MSV2-11, in which the intersections surrounded by circles are connected via switches. In this example, for convenience, an 8-bit Raku bus will be explained. Figure 11 (c)
is one in which bn and an (n=0 to 7) are connected by a switch. In FIG. 11(d), four values bO to b3 and 0'' are written to the vertical bus using switches.

Figure 11 (e) shows bO to b3 as a O-a 3 he, c
4 to c7 are written to a4 to a7, thereby making it possible to mix data appearing separately on two sets of buses and transfer it to another bus. Figure 11(f) shows a configuration in which the bit positions are converted and transferred from bus to bus. By arranging switches in this way, the positions of the upper and lower 4 bits of data on the horizontal bus can be changed. and transfer it to the vertical bus. Figures 11 (G) to 11 (S) are examples of circuits for setting constants to the bus, and Figure 11 (G) shows all n
The circuit for setting Q", Figure 11 (H) shows 1010 on the bus.
1010, that is, a circuit for setting AAIG. this is,
a7, which is the part without a switch. a5゜a3. al
is 1" by precharging just before this switch opens.
This is because what is written is retained as is.

In Figure 11 (S), the value of the constant is changed by the flag TO; if TO=O, 0016 is written to the bus, and if TO=1! EB1° is written to the bus. Data transfer from any bus to any other bus is possible by selectively opening and closing the switches shown in Figures 11(c) to 11(s) on MSW2-11 depending on the application. For example, from IIA bus to A bus, from HB bus to B bus, C
5 when you want to transfer data from the bus to the IC bus at the same time.
All you have to do is turn on 5117.5V13 at the same time.Also, if you want to transfer the C bus data to L bus and D bus, you can turn on S28.5W29゜51130.
Data is transferred along the C bus→HL bus→L bus and D bus routes.

Note that in the MS 112-11, data transfer is performed at the timing shown in FIG. That is,
The vertical and horizontal pass lines are precharged in the interval ψ1=1, data is transferred in the interval from the falling edge of ψ1 to the falling edge of ψ3, and is latched at the falling edge of ψ3. Here, the section from the fall of φ3 to the rise of ψ1 is a margin for stably performing the latch operation.

Next, data banks 1-6 will be explained. Data banks 1-6 store four types of data. They are (1) header address data, (2) header data,
(3) waveform data, and (4) envelope data.

Here, the header address data is 8-bit data that indicates in which address the header data is stored, and the header data represents the address where the waveform data and envelope data are stored and their attributes. The above four types of 0-order data, which are 8-byte data, will be explained in more detail.

(1) Header address data (HAD) This data indicates the address of header data using note data assigned to each tablet, each octave, and each three keys as an address. The storage location of the header address data is as shown in Table 14, where bits 9 to 5 are tablet data TAB, bits 4 to 2 are octave data ocr, bits 1 to 0 are the upper two bits of note data ND, All remaining bits are ′
11". Here, the 10 bits consisting of TAB, OCT, and ND are called TD, and each of them is the first
Needless to say, this is what is shown in the table. The address of the header data based on the header address data is shown in Table 15, where the header address data is entered in bits 10 to 3, the upper bits are all '1', and the lower 3 bits are ooo to 111. Enter the data.

(2) Header data (HD) Header data is 8 words of data with 8 bits per word stored at the addresses shown in Table 15.
The contents of each word are as shown in Table 16. 16th
In the table, C0NT is control data and represents the attributes of the waveform data and envelope data indicated by this header data. El' is one of two types of envelope data. The start address of the other envelope data E2' is given by STE+ΔSTE. 11.12 are two types of waveform data, w
The start address of l is given by STV+ΔSTV.

Note that C0NT has the structure as shown in Table 17, and its meaning is as follows.

Plo: A flag indicating whether the musical tone based on this ladder data has a piano-type envelope or an organ-type envelope.

If Plo = 1, it means that it is a piano type.

ORG: 3-bit information indicating to which range the musical tone data originally belonged.

The correspondence between ORG and range is as shown in Table 18. Therefore, it is also information indicating how many samples the waveform data actually has for one period.

v8: Indicates whether the waveform data has 12-bit precision or 8-bit precision. If v8=1, it is 8-bit precision. When w8=1, 4 bits of II are placed in the lower part of the waveform data.
OIP is added to maintain the amplitude level of the waveform.

PCM: PCM=1 indicates that the rising edge of waveform data v1 is PCN.

NA: A 2-bit signal used when superimposing a noise signal on a musical tone signal.

(3) Waveform data (111, 112) As mentioned above, the tone generator 1-5 uses two types of waveform data: 12-bit data and 8-bit data. Considering commercially available ROMs, most of them have 8 bits per word or less, and ROMs with 12 bits per word are rare.

Therefore, in the present invention, waveforms are stored in the ROM as follows. That is: for 8 bits, STV and ΔS
Words are stored sequentially from the address determined by the TV, but in the case of waveform data of 12 bits per word, as shown in Figure 12, the upper 8 bits are STw + ΔST.
It is stored sequentially starting from the address indicated by W, but
For the lower 4 bits, the value of STw+ΔSTv is shifted to the right by 1 bit and 2 words are sequentially stored in the lower 4 bits and the upper 4 bits from the address where 1 is placed in MSH. For example, if the top 8 waveform data at address 0444□6
The location of the lower 4 bits is the upper 4 bits of address 1222□, which means address 0445□6.
For address 1222. , the lower 4 bits of .

In this way, waveform data is efficiently stored in the ROM. That is, if the address is 0000□, ~FFFF1
If it is a ROM up to 6, the address oooo1
The upper 8 bits of 12-bit waveform data are stored in ~7FFFts, and addresses 5oooi, ~BFFF1.
The lower 4 bits of each are stored in . address co
oo1. ~FFFF0. Although 12-bit waveform data cannot be stored in the ROM, by storing 8-bit waveform data or envelope data (described later), the ROM can be used with almost no waste.

This example shows the case where the waveform data is 12 bits, but if the waveform data is 10 bits, the address of the upper 8 bits is shifted to the right by 2 bits and the upper 2 bits are 1 bit.
It is recommended to store the lower 2 bits of 4 words of 2 bits at the address where .

For example, the upper 8 bits of the address are 1222. , then the lower two bits are bit 4. of address C4881. It will be stored in bit 5. If you do this, if the ROM address is 0000□ as shown above,
~FFFF1. If so, put the upper 8 bits of the waveform data at address oooo1. ~BFFF1. and lower 2
The bits are stored in addresses CFFF1s-DFFF□6, and various data can be stored efficiently.

(4) Envelope data (El', E2')
Envelope data consists of 1 word with 16 bits,
The data format is as shown in Table 19. 6 is data that determines the update interval of the envelope address. S is the slope of the envelope (increase or decrease)
This is a flag that indicates. 2 is a flag indicating the magnitude of the slope of the envelope, and DATA is its magnitude. 1st
The data shown in Table 9 is stored in the data bank according to the addresses determined by STE and ΔSTE shown in Table 16.

Since the data bank is configured as described above, it is possible to change the timbre for each of the three adjacent keys, while on the other hand, if the same octave has the same header address data, the waveform data can be changed. The same tone color can be obtained without increasing the envelope data or header data. Also.

Since arbitrary waveform data and envelope data can be specified in each header data, it is possible to generate various musical tones even with a small amount of waveform data and envelope data by combining them.

Next, the initial processing when a key is pressed in the musical sound generating section 1-5, the method of generating a note clock, the method of generating an envelope, and the method of generating a waveform will be described.

(1) Initial Processing In the initial processing, various registers are initialized when a musical tone is generated by pressing a key. Since the operation sequence is started from the long sequence in the initial mode by pressing the key, the PDR is initialized in time slot 13 in the adding section. To describe this operation in more detail, the PDD is read from the RAM 5-4 in FIG. 5 and data is loaded onto the HE path. At the same time, PED is given to the HD bus from the signal processor 7-6 in FIG.
In the figure (a), 5W21 and 51117 are turned on and the PD
D takes the A bus and PED takes the B bus. This data is the 8th
The calculation results are added at FA2-6 as shown in the figure and placed on the C bus. This calculation result is sent to HE via 51123.
It is stored in register PDR in RAM5-4. In addition, in this calculation, PDD, PED
is transferred to FA2-6 one time slot before the time slot in which the PDD + PED calculation is actually performed.
Furthermore, the calculation result is stored in the PDR one time slot after the PDD+PED calculation is performed. The following addition operations are all the same: 0, then TRI, TR2, ZRI in time slots (15) to (18)
, ZR2 ``O'' is written, this operation is TR.
Regarding the case where 60" is written to I, MSV2-11 in FIG. 11 (A) is written in time slot (15).
L: Oite 5V33 and 5w13 are turned on. 5V3
3 has the configuration as shown in FIG. Register TRI in RAM?-3 shown in the figure is set to "Q7".
1 is written.

On the other hand, the data bank reading section performs a first-order operation. The following description will focus on FIG. 10.

Header address data HAD is read by VRD composed of TAB, ND, and OCT. In addition, in the initial mode that performs this initial processing,
The latch 10-3 is set to 111 by the SQ multiplication signal. This data is for shifter 1 in Ilo 2-10.
The data is converted into the format shown in Table 15 by D bus 5V15.0-13. R via HC bus
AM? -3 is stored in register HAD. At the same time as this operation, the header address data HAD read from the data bank is latched one after another by the latch 10-8 and latch 10-6, and the shifter selector 10-9 converts the data into the format shown in Table 15. is converted and latched into latch 10-4. In response to the output of the latch 10-4, first, the bit processing circuit 10-10 gives 000 to the lower three bits, and the control data C0NT is read out from the data bank 1-6, and then sent to the latch 10-4 via the latch 10-8. -7 is latched into the upper 8 bits. The control data C0NT is assigned to selectors 10-12. Shifter 10-13, noise circuit 10-14, latch 10-2
The data is stored in the register C0NT of the RAM 5-4 from the D bus via the D bus. On the other hand, since the upper 4 bits of latch 10-7 are connected to decoder 10-11, 16-bit data can be obtained according to the truth table shown in Table 14. However, at this time, the C input of the decoder 10-11 is '1'.

Selectors 10-12 select this decoder output,
Shifters 10-13 shift the signal to the right by 6 bits and output it.

Now, considering the output of the shifter 10-13, the data input from the latch 10-7 to the decoder 10-11 is 3 bits of Plo and ORG. Since the C input of the decoder 10-11 is now "P1", the output of the decoder 10-11 is determined only by the OR03 bit.

Therefore, the output of decoder 10-11 is converted to 6 by shifter 10-13.
The values shifted to the right by bits become the values shown in Table 18. This value is given to the D bus via the noise circuit 10-14 and the latch 10-2, and is 51115 in MSV2-11.
is stored in the register DIFI of the RAM 7-3.

Next, in response to the output of the latch 10-4, the bit processing circuit 10
-10 is given to the lower 3 bits, 0015 and 010 are given, and the upper and lower 8 bits of the header data STH are read. The value of this 5TIE is selector 10-12° shifter 10-13, noise circuit 10-14, latch 10
-2 to the D bus, and in MSv2-11, it is stored in register EARL of RAM7-1 via 8w5.

Next, enter the short sequence. The short sequence is executed twice. PDR and JD in timeslot (1)
is added, where JD is a constant and MSW2-1
1 by turning on 5W32. 5
Td32 has a configuration as shown in FIG. 11 (H), and JD=45B. The result of this addition is multiplied by the note coefficient CN to obtain FR.

Describing this series of daily calculations in detail, PDR + JD is calculated in time slot (1), and the result is given to the C bus in time slot (2) as described above.
::,::TeMSW2-11 Ni 5v28.5W2
9 is on.

Data is transferred in the order of C bus→HL bus→L bus, and is latched into latch 9-1 of MPLY2-7 in FIG. 9(a). In the next time slot (3), the seventh
The value of CN corresponding to the note data NO is read out from the ROM 7-5 in the figure and provided to the HD bus. This value is MS
It is applied to the L bus via 5% 119 in V2-11 and latched into latch 9-3 of MPLY2-7. The output of latch 9-1 is transmitted through shifter 9-11 to latch 9-1.
2, the output of latch 9-3 is sent to latch 9-4 via the bit processing circuit and latched. Therefore, the value of PDR+JD is latched in the latch 9-2, and the value of CN is latched in the latch 9-4.Then, the multiplier 9-16
The product of R+JD) and CN is calculated and sent to latch 9-8 via shifter 9-15, where it is latched. In this series of operations, the shifter 9-11, the bit processing circuit 9-12 . Shifter 9-15 operates to pass data.

That is, 61'' is given to the C input of the encoder 9-10.The value of the latch 9-8 is input from the L bus to MSW2-11.
It is stored in the register FR of nAM7-z via 8w9 of nAM7-z. Therefore, in time slot (2), ORG+
OCT+1 is calculated. In this operation, the +1 operation is performed by logic gate 8-12 in FA2-6 of FIG. That is, if the logic gate 8-12 forcibly outputs 1'' in the corresponding time slot, the latch 8-5 latches the gate 1'', giving the Ci large input °°1'' to the adder. The meaning of the calculation is as follows: ORG indicates the value (temporarily set as N) indicating to which range the waveform data originally belongs, in a form obtained by taking the inverse logic of the octave data OCT. It is.

Tables 18 and 22 show the relationship between OCT, ORG, and the number of waveform samples. Therefore, ORG+1 represents -N. In other words.

ORG + OCT + 1 = OCT -N, which indicates the difference between the range of the musical tone signal that is currently being generated and the original range of the waveform data that is actually being used, that is, the amount of octave shift. It is a value. In other words, it indicates how many octaves higher the original waveform should be read out. This value is temporarily stored in the register IE2 of the RAM 7-4, and then the signal processor 7-6
Decoded in RAM7-2 (7) L/Jister A
Stored in IIAR. The values of ΔWAR with respect to the values of ORG+OCT+1 are as shown in Table 20.

Below, EAR2 in time slot (4), EAR in time slot (6),
(8).

(9), (10) TEVR1, ERI, IE2. V
Initial settings are made for the EI and vR2 registers.

On the other hand, the data bank reading section reads the header address data HAD stored in the RAM 7-3 in the long sequence described above, and latches it into the latch 10-4 via the D bus → latch 10-1 → shifter selector 10-9. The bit processing circuit 10-10 inputs 001 to the lower 3 bits and reads the header data ΔSTE from the data bank. This value is transferred from the latch 10-7 to the selector 10-12.
→ Shifter 10-13 → Noise circuit 10-14 → Latch 1
0-2 to the D path, and SV40. It is input to the A bus via SII+30 and added to EAR1 at FA2-6. Then R.A.
5TE stored in register EARI of l'17-1
(start address of envelope data El') is read out, D bus → latch 10-1 → shifter selector 1
It is latched by latch 10-4 via pins 0-9. The output of the latch 10-4 is turned low by the bit processing circuit 10-10.
0'' is input to SB, then II I El, and the 19th
Read the 2-byte envelope data as shown in the table. This 16-bit value is latched into latch 10-7. According to the output of latch 1O-7, ΔTl in the first short sequence.

ΔEl, ΔZl, ΔT2 in the second short sequence
゜ΔE2. Δ22. generates the value of First, decoder 1
The upper 4 bits of latch error 7 are input to 0-11, and the ΔT values shown in Table 19 are input to the upper 4 bits of latch 10-7. Therefore decoder 1
0-11 decodes the 6 pieces according to Table 13 and outputs them to selectors 10-12. In the selector 10-12, C=1 at this time, selecting the S input and shifting the shifter 10-12.
Output to 13. This selector 10-12 output is applied to the D bus via the latch 10-2 without any bit manipulation being performed in the shifter 10-13 or the noise circuit 10-14, and is applied to the D bus in 9M5W2-11. H
It is stored in the register ΔT1 of the RAM 7-2 via the B bus.

ΔEl, ΔZl, ΔE2. AZ2 is the shifter 10-1 according to Z, S, and DATA of the root roller shown in Table 19.
At step 3, bit manipulation is performed and stored in each register.

The kind of bit manipulation that is performed is as shown in FIG. Table 19 shows that the data format differs depending on the value of Z.

Next, in the same way as when reading ΔSTE from the data bank 1-6, the value of the register HAD is read from the RAM 7-3 and latched into the latch 10-4.
srw from data bank 1-6 by giving 1009 then 101° in the first initial mode and 1109 then 111 in the second initial mode to the lower three bits of header address data HAD at 0.

Read ΔSTV and save STW to RAM7-3 (7) L
/Register Tv.

ΔSTI in RAM? -1 is stored in register MAR.

The above completes the initial setting of all registers.

(2) Note clock generation method First, the principle of the note clock generation method used in the tone generator 1-5 will be explained with reference to FIG.

In FIG. 3, 3-1 is a divider which divides the frequency of the master clock input to terminal CK and outputs a 10-bit frequency divided output from Q. 3-2 is a comparator.

Compare A input and S input, and when A=B, Q
3-3 is a flip-flop, which takes in the signal given to the S input at the rising edge of the CK large input and outputs it from the Q. 3-4 is an adder, which connects the A input and S input. Output the sum from C.

3-5 is a constant circuit that inputs a constant M to the S input of the adder 3-4. 3-6 is an RS latch, and when a positive pulse is input to the S input, Q=1, and when a positive pulse is input to the R input, Q=O. 3-7 is a delay circuit which delays the input signal and outputs the delayed signal.

3-8 is a <ND gate.

Next, the operation shown in FIG. 3 will be explained. First, RS latch 3-6
If the Q output of is °'0'', <ND gate 3-
Since the output of 8 is always 60'', flip-flop 3-
The Q output of 3 is constant. On the other hand, the frequency divider is divided by the master clock from 000□6 to 3FF1. repeat 10
Outputs the Q of the bit. If the output of flip-flop 3-3 is N, then naturally 000□6≦N≦3F
Since F□6, the Q output of frequency divider 3-1 will always be N at some point.
There is a moment when the Q output of the comparator 3-2 outputs a coincidence pulse.

Then, since this coincidence pulse is input to the S input of the RS latch 3-6, the Q output of the RS latch 3-6 becomes 1'', and a write pulse is output from the ND gate 3-8.

The C input of the adder 3-4 is connected to the S input of the flip-flop 3-3.
Since the output is given, the value of N+M is written.

At the same time, the write pulse is delayed by the delay circuit 3-7 and then sets the Q output of the RS latch 3-6 to 0". Therefore, the Q output of the flip-flop 3-3 becomes constant again, but the value It changes from N to N+M.Therefore, next time the Q output of the frequency divider 3-1 becomes N+M, a matching pulse will be generated.By repeating this, the comparator 3-2 will The output value of frequency generator 3-1 is N, N+M, N+2M
...Generates a pulse when someone yells. In other words, a coincidence pulse is generated every time the frequency divider 3-1 counts the master clock M times. Also, N 10nM>3FF1. In the case, the output of the adder 3-4 is N0nM-3FFl after overflow,
Therefore, it goes without saying that a coincidence pulse is generated when the master clock is counted M times. That is, by using the coincidence pulse of the comparator 3-2 as a note clock, and varying the constant M, note clocks with various periods can be obtained, and the frequency thereof is 10M (frequency of the master clock).

In addition, the Q output of SR latch 3-6 is the calculation request flag C.
Corresponds to LRQ.

The above is the principle of the note clock generation method according to the present invention.

Next, details of the calculation sequence for note clock generation in the musical tone generator 1-5 shown in FIG. 1 will be explained.

When a key is pressed on the keyboard 1-1 and the microcomputer 1-4 instructs the musical tone generator 1-5 to generate a musical tone, the calculation sequence starts from the initial mode long sequence as described above. First, at time slot (13), PDD + PED → PDR... (2-1) Then, the short sequence starts at time slot (1)
...(6) POR+ JD → L, B, ...
...(2-2) C, B, XCN 4 FR...
- The calculation (2-3) is performed. Next, the mode becomes normal mode, and FR+ CDR-+ FR... (2-4) in time slot (9) of the short sequence, P in time slots (14) to (18) of the long sequence.
DR1JD −+ L, B, ・・・・・・
(2-5) C, B, X CN →FR...
・('z-6)PDD +PED+PDI'l
......The calculations (2-7) are performed. Here, POD is the PDD shown in Table 1, that is, pitch detune data, and PED is the pitch extent data described above. JD is a constant and is set to a value of 11151° (45B in hexadecimal). The note coefficient CN is a value determined by the assigned pitch name, and the relationship between the pitch name and CN is shown in Table 7. As mentioned in the explanation of Tables 5 and 6, operations (2-2), (2-3)
and operations (2-5) and (2-6) can be expressed as shown below.

(PDR+ JD) X CN -+ FR...
・(2-8) Here, since PDR is PDD + PED, calculation (2-8) is (PDD + PED +
JD)
Accumulate in R. As mentioned above, this accumulation is performed once every note clock occurrence. Therefore, if the initial value of CDH is N, the value of CDH is N, N+FR.

It changes as N+2XFR,... The value of the upper 10 bits of this CDH is compared with the 10-bit branch signal obtained by sequentially dividing the master clock, and a matching pulse is generated, so in reality, N N + FR
N−) two λX FR,,,10,and. Comparison 8'8'8' is performed, and the upper 10 bits of CDH are shown in Figure 3 F.
This corresponds to the flip-flop 3-3 of R., and the value M of the constant circuit 3-5 in FIG. Therefore, the above (2-1) ~ (
By performing the calculation 2-7), a note clock with a constant period is obtained, and its frequency is (master clock frequency) beef tallow.

(3) Waveform generation method The waveform generation method shown in the musical tone generation section 1-5 of FIG. 1 can be roughly divided into the following five steps. That is: (1) Address generation Generates an address for reading waveform data from the data bank 1-6.

(2) Waveform reading The waveform data specified by the above address is read from the data bank 1-6, and bit processing is performed according to the control data C0NT.

■ Envelope multiplication ■ Two-wave mixing ■　CN multiplication Each step will be explained in detail below.

■ STV of eight data by initial setting by pressing the address generation key.
(12 start addresses), ΔSTw (number of till words), DIFI (number of samples included in one waveform)
is stored in register ST%l, wAR, DIFI,
Further, the register ΔvAR is determined by the calculation. Address generation is performed in normal mode based on these data, but PCM is added to the waveform data in the following processing.
When there is a section (PCM section 1) and when there is no section (PCM=O)
Since the address generation is different in the case where there is a PCM part and when there is a PC
The case where M is not present will be explained separately.

5T in time slot (2) as shown in Table 6.
Find the sum of III and wAR, use this sum to read waveform 1 from data bank 1-6, and at time slot (4) add DIFI to the above sum, that is, S
Waveform 2 is being read from data banks 1-6 using the TV + wAR + DIFI (7) value. here,
STV is the start address of waveform 2, and register WAR
contains the negative number of ΔSTV, that is, the number of words included in waveform 1 as an initial value, and Δv
The AR is accumulated, so the value of STV + vAR is
The value increases sequentially from the first address of waveform 1 for each value of ΔvAR. Further, since the value of ST+VAR+DIF1 is obtained by adding DIFI to this value, it becomes a value that increases every ΔwAR from the start address of waveform 2.

Here, since ΔWAR is a value representing the readout of the waveform, addresses for waveform 1 and waveform 2 can be generated by making it 1 or more.

Further, in the main sound generation section 1-5, phase matching is performed when there is no PCM section, the solo flag 5QL=O, and no octave shift is performed. The method of phase matching is to store 9 bits of data whose address is the homophone name in RAM8-13 as an operation result in the register WAR in the first time slot (7) when the operation sequence changes from the initial mode to the normal mode. R.A.
The output of M8-13 is 9 bits, but since the C bus is precharged, u 1 yt is included in the upper 7 bits of the 16 bits mentioned above. The calculation results for the second and subsequent time slots (7) are stored in register l1lAR as shown in Table 6, and are also stored in RAM8-
13 is updated to a register (phase register) whose address is the homophone name. By doing this, even if a tone with the same note name has already been generated in another channel, the register l1lAR in that channel
Since the value of is applied to the register MAR of the channel from which a musical tone is to be generated via the RAM 8-13, it is possible to match the phase between these two channels.

Here, the calculation of time slot (7) WAR + ΔWAR
Let's talk about.

When AR+ΔAR≧O, the calculation result is 1512□ on the C bus, regardless of the range. (FFOO, @) is given. If there is no octave shift, Δ1IAR=
1, the value of register IIAR is repeated every 512 times.

As described above, the register %lAR of each of the plurality of channels that generate the same note is always the same, so the phases of the waveforms of the same note generated by different plurality of channels completely match, and phase matching is realized.

Next, the calculation STW + W in time slot (2)
AR will be explained in more detail.

Data is read from register ST%l of RAM7-3.

The HC bus shown in MS2-11, 5VI1.
Latch 8 of FA2-6 is activated by clock ψ3 via A bus.
-1 is latched. At the same time, RAM7-1 register w
The value of AR is latched into latch 8-2 of FA2-6 by clock ψ3 via HA bus SV2 and B bus.

The output of the latch 8-1 is latched into the latch 8-3 by the clock ψ1 without undergoing any bit processing in the bit processing circuit 8-10. On the other hand, the output of latch 8-2 is
After the bit processing circuit 8-11 receives ORG as an input and performs bit processing as shown in Table 21, it is latched into the latch 8-4 at clock φ1. Adder 8-9 adds the outputs of latch 8-3 and latch 8-4, and adds the output of latch 8-3 and latch 8-4.
7. It is applied to the C bus via latch 8-8. By performing the bit processing described above in the bit processing circuit 8-11, even though the register wAR changes at a period of 512, it changes at a period corresponding to each octave1. ,0RG=5,
When 0CT=2, there is no octave shift and ΔυAR=1 as described in the initial processing section. Also, from Table 21, bits 7.8 of register WAR are always 1, so the calculation result of time slot (2) is tentatively ST
When V' = O, -10, -9, ...-1, -1
28, -127, . . . -1, -128 . . . and repeats with a cycle of 128. Also.

In the case of 0RG=4.0CT=5, there is a two-octave shift and ΔVAR=4. Also, according to Table 21, bits 6, 7, and 8 of register wAR are always 1, so similarly -40,...-8, -4, -64, -60, -56...
...-4, -64, ... and so on, repeating in 16 cycles.

When 0CT=2, the repetition period is 128, and OCT,
When = 5, the repetition period is 16, which indicates that the desired waveform points are obtained according to Table 22.

Also, when 0RG = 4, 0CT = 5 (7), the fact that the register MAR increments by 4 means that the data of 64 waveform samples is incremented by 1 every 4 samples, as shown in Table 18.
This shows that the octave of the original waveform data can be raised by two octaves by obtaining the data point by point.

The address generation when there is a PCM section is different from the case where there is no PCM section except for the calculation in time slot (2) which is the same.

In time slot (2), the calculation of STR+wAR is performed. That is: Data is read from the register STV of the RAM 7-3 and latched into the latch 8-1 of the FA 2-6 by the clock ψ3 via the IC bus, 5w11, and the A bus. at the same time.

RAM? -1 (L/VAR+7) is latched into the latch 8-2 of the FA 2-6 via the HA bus s12 and the B bus. Here, the output of the latch 8-1 is the bit processing circuit 8-10, and the output of the latch 8-2 is the bit processing circuit 8-10.
-11, but both outputs are sent to latch 8-3 and latch 8-4 without being subjected to bit processing, and are added by adder 8-9.

Now, considering the value of register wAR, PCM
If there is no part, a negative number of the number of samples included in the waveform-period is written to the register wAR as an initial value.
If there is a PCM section, the negative number of all samples of the waveform used as the PCM section is written as the initial value of register IIAH. Therefore, the calculation result of time slot (2) is a value that is sequentially increased by ΔWAR from the PCM section head address of waveform 1 in data bank 1-6.

The end of the PCM section is detected by detecting that WAR+ΔWAR≧0 in the calculation in time slot (7), and the PC
Address generation after the M section is completed is exactly the same as in the case without the PCM section, and bit processing is performed by the bit processing circuit 8-11.

Note that although the address calculation in the tone generator 1-5 uses 16 bits, it is naturally possible that a 16-bit address signal may not be sufficient. Therefore, the main musical tone generating section 1-5
The address space can be expanded using the upper three bits of tablet data TAB.
The latch 10-3 in Ilo 2-10 is a latch for address space expansion, and the upper three bits of the tablet data TAR are latched into the latch 10-3. That is: When the key is pressed to enter the initial mode, RAM5-4
The tablet data stored in is stored in register TAB' of RAM 7-3 via MS 112-11. Next, when entering normal mode, RAM? The value of register TAB' of -3 is read and latched into latch 10-3 in Ilo 2-10 via MSll 12-11. In this way, internal operations can access a 19-bit address space even though it is a 16-bit one.

■ Waveform reading Waveform reading is performed based on the addresses performed in time slots (2) and (4). Time slot (
The calculation result of 2) is C path, 51128, HL Babasu S30. It is latched into latch 10-1 of Ilo 2-10 via the D bus. First, the output of the latch 10-1 is latched into the latch 10-5 via the shifter selector 1O-9, the latch 1O-4, and the bit processing circuit 10-10, and the output is latched into the data bank 1-6 along with the data from the latch 10-3. Upon reading, the output of data bank 1-6 is latched into latch 10-8. Next, the output of the latch 10-1 is shifted to the right by one bit by the shifter selector 10-9, and 1" is added to the MSB, which is latched by the latch l0-4. The output of the latch 10-4 is transferred to the bit processing circuit 10. -1
0 to latch 10-5, and latch 10-
Data bank 1-6 is read out along with the data by data bank 10-7, and the output of data bank 1-6 is latched into latch 10-7. At this time, since the output of latch 1o-8 is given to the upper 8 bits of latch 10-7, they are latched together with the previous value of data bank 1-6. Here, the data latched in the lower 8 bits of latch 10-7 is the lower 4 bits of the 12-bit waveform, as described in the data bank section.
Bits correspond to 2 words. The output of latch 1o-7 is applied to shifter 10-13 via selector 10-12, and the upper 8 bits are shifted to the right by 4 bits.

If the LSB of the output of the latch 10-1 is O, the lower 8 bits are also shifted to the right by 4 bits, and if the LSB is 1, the lower 4 bits are output from the shifter 10-13 without being shifted.

Here, w8=1 in the control data C0NT
That is, if an 8-bit waveform is specified, the shifter 10-
13 outputs the lower 4 bits as 91Q#. The output of the shifter 10-13 is given to the D bus via the noise circuit 10-14 and the latch 10-2, and MSW2-11
is stored in the register VRI of the RAM 7-3.

This value is the waveform data of waveform 1.

The same principle applies to the address obtained by time slot (4). However, if NA=00 in the control data C0NT, a noise signal is added in the noise circuit 10-14.
When <N=01, bit 9 is replaced with a noise signal, when NA=IO, bit 10 is replaced with a noise signal, and when NA=11, bits 9 and 10 are replaced with a noise signal. In this way, the noise signal is superimposed without using an adder. Is this the waveform data of waveform 2 in RAM? -2 is stored in register WR2.

■ Envelope multiplication Waveform 1. Two types of waveform data of waveform 2 have been obtained, and this waveform data is subjected to envelope multiplication. The envelope for waveform 1 is stored in RAM7-
The envelope for waveform 2 is stored in register ERI of RAM 7-3, and the envelope for waveform 2 is stored in register ER2 of RAM 7-3. here,
Speaking of envelopes.

The envelope is expressed as a 13-hit floating point number with 4 bits for the exponent and 9 bits for the mantissa. Envelope multiplication is performed twice for each channel, but each operation is similar, so the WRI in time slots (7) to (9)
The calculation of XERI will be explained.

RAM7-3NOL/JIXJERI (7) data is MSV
2-11, it is latched by latch 9-3 and latch 9-5 of MPLY2-7. Here, the latch 9-3 latches the lower 10 bits of the register ERI, and the latch 9-5 latches the bits 9-12 of the register ERI. Next is RAM? -3 register vRI (7) data is MSV
rMPLY2-7 is latched to f9-1 via pin 2-11. The output of the latch 9-3 is the bit processing circuit 9-
At 12, its MSB is set to '1' and the latch 9-
It is latched to 4. That is, the hypothetical portion of the envelope is latched in the latch 9-4. The output of latch 9-1 is latched into latch 9-2 via shifter 9-11. At this time, the C input of encoder 9-10 receives 1
is given, and 000 is given to the C input of shifter 9-11.
01 is given. Therefore, shifter 9-11 is latch 9-1.
12 bits of waveform data of waveform 1 read from data bank 1-6 are sent to latch 9-2. Multiplier 9-16 connects latch 9-2 and latch 9-4
The 14 bits of the product are latched in the latch 9-7 and sent to the shifter 9-15.

On the other hand, the exponent part of the envelope is latched in the latch 9-5, decoded by the degoder 9-13 via the latch 9-6, and then sent to the shifter 9-13 via the selector 9-14.
15 as a control signal. Therefore, latch 9-7
The output of is shifted by the exponent part of the envelope and latched by latch 9-8. In this way, the fixed-point waveform data and the floating-point envelope are multiplied. The output of latch 9-8 is MSW 2 from L bus.
-11, and is stored in the register VEI of the RAM 7-1. Can you multiply the waveform data of waveform 2 and the envelope in the same way?RAM? -4 is stored in register vE2.

■ Two-wave mixing As described above, register %lE1. The waveform was stored in vEz. In this step, the sum of VEI and 1IE2 is calculated. The calculation in time slot (1) corresponds to this.

■ Two-wave mixing is performed in the CN multiplication time slot (1), but in the one tone generation section 1-5, the ABM 2-9 and the filter 1-7
Depending on the characteristics of the note, the sound pressure level generated may differ depending on the note name. CN multiplication is used to correct this. Here, note coefficient CN is used as a coefficient for correction.
is used as is. The calculation result of VB2 + WEI in time slot (1) is 5112 from the C bus.
8. HL Babasu 51129, Lbacus MPL
It is latched by latch 9-1 of Y2-7. On the other hand, memory 2
The note coefficient CN is read from the ROM 7-5 of -5 in accordance with the note data ND, and is latched into the latch 9-3 of MPLY2-7 via the HD bus 5V24 and the L bus.

Here, VEI-IE2 is 16-bit data, but the A input of multiplier 9-16 is 12-bit, so MPL
In Y2-7, the following processing is performed. That is, the upper five bits of latch 9-1 are input to encoder 9-1o, and encoder 9-10 outputs data as shown in Table 9 from both terminals A and 8. In other words, the actual number of bits of data in the latch 9-1 is determined, and according to this result, the shifter 9-11 moves the data from the latch 9-1 to 1 bit.
Extract 2 bits. For example, if the value of latch 9-1 is 3A
In the case of 261°, this data is actually 15-bit data, so shifter 9-11 transfers bit 1 of latch 9-1.
The 12 bits below 4 are taken out, and the output of shifter 9-11 is 7441. In this way, 11E2 + I
The real part of EI is multiplied by the note coefficient, and the shifter 9-15 restores the original number of bits.

Latch with latch 9-9.

As described above, data with a large number of bits is multiplied using a multiplier with a small number of bits.

The value obtained in this way is output to DAC2-8, and A
The signal is corrected to a predetermined period in BM2-9 and output as a musical tone signal.

By the way, in the main musical tone generating section 1-5, the CN multiplication can be switched to the VLD multiplication using the flag VOL in Table 1 under the instruction of the microcomputer as described above.

That is, in the long sequence, the register VLD 8 bits of RAM5-6 are transferred to the RA via MSW2-11.
It is sent to register LVD' of M7-4. M when sending
A bit shift is performed in SW2-11, and the 8-bit data is shifted to the left by 2 bits, and 0 is added to the lower 2 bits.
is added and converted to IO bit data. As a result, the number of bits in VLD becomes the same as the number of bits in CN. Whether the value of VB2-IJEI is multiplied by the value of ROM7-5 or the value of register VLD' is determined by the flag VOL in Table 1. If VOL=O, ROM
7-5 sends HD bus data, and if VOL=1, is it RAM? -4 sends HD bus data.

With the above configuration, it is possible to change the level of the musical tone signal output from the musical tone generating section 1-5 by the microcomputer 1-4, and apply amplitude modulation by sequentially changing the values of VLD in Table 1. becomes possible.

V based on at least one of the speed and pressure of pressing the keyboard.
When an LD is created, a touch response function is realized.

The touch response function is a function that changes the volume, tone, etc. depending on the speed and strength of the keyboard operation.0For example, on a piano, when you press a key strongly, not only does the volume become louder, but the tone also becomes brighter, whereas when you press a key weakly, the tone becomes brighter. Then, not only is the volume low, but the tone is also muffled. The volume and tone can change freely depending on the strength of the keystroke, but in the case of a piano, even if you change the strength with which you press the key after the key is struck, you cannot change the sound quality, which is already attenuating. In this way, the piano's touch response function is based only on the strength of the keystroke.
Such a function is particularly called initial touch control. Percussion instruments generally fall into this category.

On the other hand, the trumpet's sustained sound quality can be changed depending on the strength of the breath, so this sound can also be imitated and played using the keyboard of an electronic musical instrument.

While a trumpet sound is generated by pressing a key, it is necessary to change the volume and tone by increasing or decreasing the strength of the key pressing. This kind of function is particularly called aftertouch control, and it generally applies to one-string instruments and wind instruments.

In the embodiment of the present invention, as described above, by performing VLD multiplication using the VOL flag, the volume can be controlled independently for each channel.

As an example of application, the strength of keystrokes is measured and V is adjusted according to the strength.
By creating the LD value and transferring it from the microcontroller,
The volume of each sound changes according to the different VLD transferred for each keystroke.

As mentioned above, when the microcomputer transfers the VLD, if the tablet data is switched and transferred according to the VLD value, the musical tone generator of this embodiment can change the volume and tone according to the VLD value. This is clear from the functional explanation given below.

This tone color switching will be explained using an example in which the VLD is 8 bits.

Table 23 shows an example of the range of VLD values and the corresponding strengths and weaknesses and tablet names.

Each time the VLD decreases by 1 bit, the volume decreases by 1/2, or 6 dB, and this is assigned to each dynamic name of the musical term. Also, since the strength of FF requires a gorgeous tone, waveform data rich in harmonics is assigned to Tablet O, and at a volume lower than MP, a muffled tone is required, so waveform data close to a sine wave is assigned to Tablet 3. , prepare multiple types of waveform data in a data bank.

In this way, depending on the strength of the keystroke, the tone can be switched in four ways within the VLD numerical range, and at the same time the 8-bit VL
Depending on D, 256 different volume levels can be specified.

The above was the initial touch control, but similarly, the VL changes moment by moment depending on the amount of pressure on the key after the key is pressed.
When the microcomputer sends D and tablet data that changes moment by moment according to the value of VLD, the musical tone generating section of this embodiment changes the tone and volume moment by moment according to the change in key pressing pressure after the key is pressed. can be done.

The above is aftertouch control.

(4) Envelope generation method The envelope generation method in the musical sound generation section 1-5 can be divided into the following three steps. That is.

■ Address generation ■ Read envelope data ■ Envelope calculation Each step will be explained in detail below.

■ STE of header data is set by initial setting by pressing the address generation key.
(start address of envelope data El'),
Registers EARI, EAR2, TRI, T based on ΔSTE (number of words of envelope data El')
R2°ΔTl and ΔT2 are initially set. Address calculations are performed based on these data. Address calculations are performed in a long sequence of calculations because the calculation frequency may be low. Furthermore, to.

Envelope data El at odd numbered times of long sequence
′ address operation is performed on the envelope data E at even numbered times.
2' address calculation is being performed.

In the odd-numbered long sequence, ΔTl + TRI → TRI at time slot (13)
...(4-1) ΔEARI + EARI +Ci 4 EARI in time slot (15)
. . . The calculation (4-2) is performed and the data bank 1-6 is read using the value of EARI. Ci in time slot (15) corresponds to the overflow caused by the accumulation of ΔT1 performed in time slot (13). Here, calculation (4-1) will be explained in detail.

First, the value of the register ΔT1 of the RAM7-2 is transferred to the FA2-6(7) latch 8 via the HB bus MS++12-11.
-H;-Latch sale. At the same time, the value of the register TRI in the RAM 7-3 is latched via the HC bus and the MS 112-11. latch 8
-1 output is bit 3 by bit processing circuit 8-10.
is forced to II OIP (the reason for setting bit 3 to '0' will be explained later) and is latched by latch 8-3. The bit processing circuit 8-11 does not perform processing such as bit conversion.The outputs of the latch 8-3 and the latch 8-4 are latched by the latch 8-4.
9 and C through latch 8-7 and latch 8-8.
Give busni, l'1sv2-11 through TeRAM7-:
M) Store the addition result in L/sister TRI. If an overflow occurs in the addition result, adder 8
1" is output from Co of -9. This output is latched to 8
It is latched at -6 and used in the calculation of time slot 15. However, this applies when the waveform data does not have a PCM section, and when the waveform data has a PCM section (flag PCM = 1), the register TRI is forcibly set to 0'' as the operation result until the PCM section is read. is input.Therefore, since no overflow occurs due to the accumulation of ΔT1, the value of EARL is not updated until the P side is finished reading.

As mentioned in the initial processing section, ΔT1 is the value of the D output when C=0 in Table 13, and the register T old is 1.
Since it is a 6-bit register, for example ΔT1=400
01. Then, when operation (4-1) is performed four times, register TRI overflows, and C1 of operation (4-2) =
The address becomes 1 and the address is updated. Here, the operation (4
-1) and (4-2) are performed once every two long sequences. As shown in FIG. 1(C), a long sequence on the same channel appears in a period of 388 time slots, that is, since one time slot is 250 ns, a period of 97 μs appears. Therefore, calculations (4-1) and (4-2) are performed every 194 μs, and ΔT1=4000. ．． In this case, the address will be updated in 776 μS.

By the way, since the envelope data is composed of 2 bytes, when updating the address, it must be updated in increments of 2 bytes. In time slot (15), the address is updated as follows.

First, Δ11! ARI is a value determined by ΔT1, and ΔTl≠00081. When ΔEARL:0000
．． ．． , and when ΔTl = 0008□6, ΔEA
RI = FFEB, , = -211°. This operation is performed at 51131 in MSV2-11.
5W31 is as shown in Figure 11, and Δ
It is controlled by a flag TO indicating the value of bit 3 of Tl. Now suppose ΔT1≠0008. ．． Then, 5V31
oooo to the A bus, but from the register EARI of RAM7-1, HA bus X, N5w2-11 (7) SW
2 via B bus 4: EARI(7) value is provided.

These values are FA2-6 latch 8-1゜latch 8-2
latched to. The output of latch 8-1 is sent to latch 8-3 via bit processing circuit 8-10.

Here, data conversion is not performed in the bit processing circuit 8-10. At the same time, the output of the latch 8-2 is given to the bit processing circuit 8-11, and the LS of the data
B is forcibly set to 1" and sent to the latch 8-4. In other words, 1 is added in advance by the bit processing circuit 8-11. Also, the arithmetic operation ( 4
-1) is latched into latch 8-5. Therefore, latch 8-3. Latch 8-4 and latch 8-
When the value of 5 is added, the value of latch 8-5 becomes u 1 t
t, 2" will be added to the value of EAR1. On the other hand, if the value of latch 8-5 is 0", the value of EARL will remain incremented by 1, but as described in the initial processing section. As mentioned above, since nQIgN199 is forcibly given to the LSB in Ilo 2-10, no inconvenience occurs.

By the way, ΔTl = 00081. In the case of ΔEA
RI becomes FFEBl, (-21,.), therefore EA
21□ from the RI value. The envelope data 10 words before will be read. This causes the addresses of the envelope data to loop, making it possible to generate a repeating envelope like a mandolin. Earlier, in operation (4-1), it was stated that bit 3 is set to '0' in bit processing circuit 8-10, but the reason for this is that bit 3 is the bit that sets ΔEARL = FFEB, and this operation register T when performing
This is to avoid adding oooal to RI.

Ar2°TR2 at the even numbered times of the long sequence,
The calculations of ΔEAR2 and EAR2 are performed in the same manner.

Note that since calculations regarding EARL and EAR2 are performed completely independently, waveform 1. It goes without saying that a completely different envelope signal can be generated for waveform 2. Furthermore, since it is easy to vary the repetition period of EAR1 or EAR2, various effects can be obtained.

■ Reading envelope data Envelope data is read in a long sequence, and the envelope data of waveform 1 is read out at even numbered times.
The envelope data of waveform 2 is read out at odd-numbered times.

The method of reading envelope data based on the values of registers EARI and EAR2 is exactly the same as described in the initial processing section, and the format conversion of the data read from data bank 1-6 is performed in l102-10. While register ΔTl.

Ar1. AZI, AZ2. It is stored in ΔEl and ΔE2.

■ Envelope calculation By reading the envelope data, Δ21°ΔZ2
．． Data is stored in ΔEl and ΔE2, and ERI, ER2, ZRI, and ZR2 are stored by initial processing.
An initial value is given. Perform envelope calculations according to these values.

The basics of envelope calculation are the time slots (3
), (5), (6), (8), calculate the envelope of waveform l by time slots (3) and (5), and calculate the envelope of waveform 2 by time slots (6) and (8). do. Here, time slot (5).

CL in (8) is an overflow caused by the calculation in time slots (3) and (6), but how does the overflow that occurs in time slots (3) and (6) flow into time slots (5) and Added in (8) is the time slot (13) of address generation.

This is the same as described in (15). The values of ERI and ER2 obtained in this way are envelope data.

By the way, the envelope calculation differs depending on the various modes. What are the various modes?

1) When the waveform has PCM and when it does not.

(PCM = l10) 2) In the case of a piano-shaped envelope and in the case of an organ-shaped envelope. (Plo = l10) 3) When the damper flag is turned on and when it is turned off. (DMP = l
10) There are three types. The various cases will be explained below.

PCM part 0 and P10=0 Initial setting is 0 for ERI, ER2, ZRI, and ZR2.
”, and when the key is pressed, registers ΔEl, Δ
The envelope is calculated according to the values of E2°ΔZl and Δz2. When the key is released, timeslot (3), (
5).

(6), (8) (7) AZI, AEI, AZ2.
AE2 (7) value.

Release data is generated from the signal processor 5-6 of the UCIF 2-3, and is sent to registers ΔZl, ΔEl, ΔZ2. ΔE2
used instead of the value of

Note that in this mode, the damper flag DMP does not affect the calculation at all.

PCM=O or P10=1 The initial settings are ERI, ER2, ZRI, and ZR2.
o"i' ant, when the key is pressed, register ΔEl
, ΔE2゜ΔZl, calculate the envelope according to the values of Δz2. When the key is released, the damper flag DMP=1
In the case of , registers ΔEl, ΔE2 . Δz1. Δ
Calculate the envelope according to the value of z2, and when the damper flag DMP=O(7), PcM=o and P10=o
The same is true for .

PCM section 1 or P10=0 Initial setting is EA1=IFFF1. , ER2=O
, ZR1=O.

ZR2=O. The key is pressed and waveform 1 is PC
The initial values are held while reading the M part, and when the PCM part is read, the registers ΔEl, ΔE2゜ΔZl, Δ
An envelope calculation is performed according to the value of z2. When the key is released, calculations are performed based on the release data by the signal processor 5-6 of the UCIF 2-3, regardless of whether waveform 1 is reading the PCM section or not.

That is, the result is a case where PCM=O and P10=O.

Note that in this mode, the calculation is not affected at all by the damper flag DMP.

PCM=1 and P10=1 Initial settings are ER1=IFFF, 6. ER2=O,
ZR1=O.

ZR2=O. If damper flag DMP=O,
Once a key is pressed, calculations are performed regardless of the timing of key release. That is, when waveform 1 reads out the PCM section, registers HR1, ER2, ZRI, and ZR2 hold their initial values, and when the PCM section is read out, registers ΔEl, ΔE2, . Calculation is started according to the values of ΔZl and Δz2. When damper flag DMP=1, PCM=
1 and P10=O.

As described above, envelope signals can be freely generated according to various modes. Also, ΔEl, Δ
Z1 and ΔE2. Δz2 can be set completely independently, and its data is ΔTl, ΔT as shown in the address generation section.
Since the data is updated at a time determined by 2, various musical tones can be generated in conjunction with the two types of waveform data described above.

(Effects of the Invention) As described above, the present invention provides the following advantages: Let Ai and Bi be the addresses where the upper M bits and lower (NM) bits of the first word of data are stored in the storage device, respectively. , Bi == Yutaka+N2 and・Ai M However, [ ] is a Gaussian symbol, and represents the integer part of the numerical value in [ ].

It has a storage device in which the above data is stored in the relationship, and the above address Bi is the above address Ai, Ωogz N
:y (However, [ is a Gaussian symbol.) By having an address generator that creates an address by shifting it to the right by a bit and adding 1 to at least one bit including the most significant bit, the efficiency of ROM usage is improved. However, it is possible to provide an information processing device having more extensive data with a smaller memory area.

Table 2 Table 7 X: Don’t care X: Don’t care Table 14 (Top 2 bit) Table 15 Table 19 1: Bit without bit processing

[Brief Description of the Drawings] Figure 1 (A) is a block diagram of an embodiment of the information processing device according to the present invention, Figure 1 (B) is a timing diagram of data transfer by a microcomputer, and Figure 1 (C) is a block diagram of an embodiment of the information processing device according to the present invention. FIG. 2 is a diagram showing the calculation time slots used in the present invention. FIG. 2 is a configuration diagram of the musical tone generating section 1-5 in the present invention. FIG. Figure 4 is a detailed diagram of 5EQ2-2 in musical tone generator 1-5, Figure 5 is a detailed diagram of UCIF2-3, Figure 6 is a detailed diagram of CDR2-4, and Figure 7 is a detailed diagram of memory 2.
Detailed view of -5, Figure 8 is the same < Detailed view of FA2-6,
Figure 9 (a) is also a detailed diagram of MPLY2-7, and Figure 9 (b) is the multiplier 9-1 used in MPLY2-7.
6 and FIG. 10 are detailed diagrams of Il in the musical tone generating section 1-5.
o Detailed view of 2-10, Figure 11 (a) is the same <MSV
2-11+71 Detailed drawing □, Figure 11 (B) ~ Figure 11 (
1) is a pattern diagram of the switch used in MS+12-11, Figure 11 (N) is a timing diagram of data transfer □ in MS+12-11, Figure 12 is a diagram showing the data format in data bank 1-6, FIG. 13 is a diagram showing the data format of envelope data in the data bank 1-6, and FIG. 14 is a block diagram of a conventional information processing device. 1-1: Keyboard, l-2: Tablet, 1-3・
...Effect switch, ■-4...Microcomputer, 1-5...
・Musical sound generation section, 1-6 data bank, 1-7... Filter, 2-1... Master clock, 2-2... Sequencer (SEQ), 2-3... Microcomputer interface section (UCIF ), 2-4... Comparison register section (C
DR), 2-5...Memory, 2-6...Full adder part (FA), 2-7...Multiplication unit (MPLY), 2-8
...Digital analog converter (DAC), 2
-9...Analog buffer memory section (ABM), 2-
1O... Input/output circuit section (Ilo), 2-11... Matrix switch section (MSV). Patent applicant Matsushita Electric Industrial Co., Ltd. Figure 1 (A) (υ) A/D-C7 B? ”-'l- Figure 2 Length Figure 4 Q Figure 8 Figure 11 FA Ml'LT L Figure 11 ())
+) Figure 12 Figure 13 Zlo's confrontation 2119

Claims (1)

[Claims] When storing a plurality of words of data, each word consisting of N bits, in a storage device having a total number of words W, each word consisting of M bits,
Under the condition that the relationship between M and N is M<N≦3/2M, the upper M bits and lower (NM) bits of the data of the i-th word of the above data are the addresses stored in the above storage device. Let Ai and Bi be respectively, then Bi=[W/2
+(N-M)/M·Ai] However, [] is a Gauss symbol, and represents the integer part of the numerical value in []. The above address Bi has a storage device in which the above data is stored, and the above address Bi shifts the above address Ai to the right by [log_2N/(NM)] (where [ ] is a Gaussian symbol) bits. An information processing device comprising an address generator that generates an address by adding 1 to at least one bit including the most significant bit.