JPS612472A - Picture recorder - Google Patents

Abstract

PURPOSE:To prevent previously the fitled device from defects such as the storage of unnecessary pictures and misarrangement of pictures by reading out stored picture data, executing picture processing for finding out one picture element by averaging plural picture elements, and displaying a synthesized picture compressed by a picture processing means on a display device. CONSTITUTION:Addresses in a plural-picture storage part 3 are read out in the order of (1,1)-(2M,2), (1,2)-(2M,2)...(1,2N)-(2M,2N). At that time, change-over switches S1, S2 are selectively turned to contacts S1b, S2b by a controller 9 and the output of the storage part 3 is inputted to an adder 13. The adder 13 adds two picture elements continously inputted to the adder 13 by providing the adder 13 with the latch of one picture element. In addition, two line memories 16, 17 are alternately used. Consequently, synthesized pictures H1-H4 obtained by adding and averaging each four picture elements in one group are displayed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image recording device having a function of selectively displaying a plurality of pieces of image data stored in a storage unit on a display device.

A conventional multi-format camera is a so-called CRT photographing device, in which an image arrangement is programmed when recording multiple images, and each image is processed by CR according to the program.
The images are output one by one to the T, and are photographed as hard copies using film via a lens optical system. In this case, since multiple images are recorded one by one, for example, one
Once an individual image is recorded, it is impossible to change it. In addition, there are many disadvantages in use, such as the inability to change the image arrangement midway and the fact that it is difficult to determine what kind of image has been recorded without copying the notes.

Figure 1 shows an example in which four frames of images F1 to F4 are arranged on one /\- copy, but with conventional equipment, image F1 is first output to a CRT and photographed, and then image F2 is captured on the same copy. Four frames of images F1 to F4 are sequentially recorded by outputting the ChT and photographing them. Therefore, for example, if you realize that another image should be recorded at image F2 after shooting image F2, or
If you realize that should be arranged at the position of image F3,
Shooting would have to be redone and the hard copy would be wasted. Furthermore, a multi-format camera may not only arrange the images in FIG. 1 but also arrange six frames of images F1 to F6 as shown in FIG. 2, for example. If the number of frames differs, the size of the recorded image must also be changed, and even if you finish shooting with the arrangement shown in Figure 1 and realize that you should have used the arrangement shown in Figure 2, you cannot change it. The shooting had to be done again.

In addition, in FIG. 2, when shooting images F1, F2, and F3, it is interrupted, and when shooting is restarted next time, images F1,
There was a drawback that it was impossible to tell what was recorded in F2 and F3. Furthermore, multiple images can be processed at the same time using the same CR.
If the image is displayed in T and photographed, the above-mentioned drawbacks will be solved, but the number of pixels in the C3'tT screen will be insufficient and the quality of the recorded image will deteriorate.

An object of the present invention is to provide an image recording apparatus that eliminates the drawbacks of these conventional apparatuses, compresses stored image data, and displays the image arrangement to be recorded on a display means. is an image recording device that has a multiple image storage unit that stores multiple image data, reads out the image data stored in the multiple image storage unit, and records the multiple images on one hard copy, The image processing apparatus includes means for reading the stored image data and performing image processing to obtain one pixel by averaging a plurality of pixels, and a display means for displaying a composite image compressed by the image processing means on a display device. It is characterized by:

The present invention will be explained in detail based on the embodiment shown in FIG. 3 and below.

FIG. 3 is a block diagram of the present invention, and is an embodiment in which an analog image signal is digitized, stored in a digital memory, and then converted into an analog signal again and recorded on a film with a laser beam. Analog image signal V is sent to A/D via amplifier 1.
digitized by converter 2 and stored in multiple image storage unit 3
is memorized. FIG. 4 shows the memory configuration of this multiple image storage unit 3. In this case, based on the example of FIG.
)~(M,N), image F2 is (N+1.1)~ of G2
(2M, N), image F3 is (1, N+1) to (M
, 2N), image F4 is (N+1 , N+1) to (
2M and 2N), respectively. For this purpose, X address counter 4 and Y address counter 5 are
is controlled by a clock pulse generator 6, a multiplexer 7, a frame counter 8, and a controller 9. When writing an image, the output c1 of the clock pulse generator 6 is selected by the multiplexer 7 under the control of the controller 9. The X address counter 4 and the Y address counter 5 output 1 to M and 1 to N, respectively, when writing the image F1, and write the data of the image F1 in the storage area G1 as shown in FIG. When writing the image F2, the X address counter 4 is controlled by the frame counter 8 and outputs N+1 to 2M, and the Y address counter 5 outputs INN to write the image F2 in the area G2. That is, the X address counter 4 and the Y address counter 5 can be implemented as preset counters controlled by the frame counter 8, and the images F3 and F4 can be similarly written to the areas G3 and G4, respectively.

The controller 9 is controlled by a selection means (not shown).
When displaying only a frame on the display device, the pixels at the address are read out from the multiple image storage unit 3 in the same way as when writing, and the changeover switch S1 controlled by the controller 9 is pressed.
G2 contact Sla, S2a, D/A converter 10
, and displayed on a display device such as a CRT 12 via an amplifier 11. That is, by setting a frame image number in the frame counter 8, one desired frame of the image can be displayed.

When displaying multiple images on the C-RT 12, the output C1 of the clock pulse generator 6 is controlled by the controller 9.
The clock signal C2, which is faster than the clock signal C2, is selected by the multiplexer 7 and drives the X address counter 4 and the Y address counter 5. The X address counter 4 and the Y address counter 5 are 2M and 2N base counters, respectively, and store the addresses of the multiple image storage unit 3 from (1', 1) to (2N, 1).
, (1,2) ~ (2M, 2), --- (1,2N) ~
Read in the order of (2M, 2N).

At this time, the controller 9 selects the contacts Slb and S2b of the changeover switches S1 and S2, respectively, and the output of the multiple image storage section 3 is input to the adder 13.

This adder 13 adds two consecutively input pixels, but this can be realized by providing the adder 13 with a latch for one pixel. The first line (1, 1) to (2M, 1) of the multiple image storage unit 3 is stored in the adder 1.
3 is (1,1) + (2,1), (3,1) + (4,1
), . . . (2M-1,1)+(2M,1), and the addition results are stored in the line memory 14. Next line (1, 2) of multiple image storage unit 3
The adder 13 similarly adds . Add to. That is, the output of the adder 13 (1, 2) + (
2, 2) and the output of the line memory 14 (1, 1) + ('2
．． 1) is added by the adder 15, and by further shifting, the lower 2 bits are discarded, and the contact S of the changeover switch S3 is
The calculation result is stored in the line memory 16 via 3a.

This calculation is (1,1) + (2,1) + (1,2) + (2
, 2), it becomes 1/4 by cutting off the lower 2 bits, so it becomes the average value of 2.2=4 pixels.

Similarly, the output of adder 13 (3, 2) + (4, 2)
and the output of the line memory 14 (3, 1) + (4, 1),
・Φ・, (2M-1,2)+(2M,2) and (2M
-1,1)+(2M,1) and shift are performed, and the calculation result is stored in the line memory 16. When calculating the third and fourth lines of the multiple image storage section 3, the contact S3b of the switch S3 is selected, and the calculation results are stored in the line memory 17 similar to the line memory 16. Further, at this time, the contact S4a of the changeover switch S4 is selected, and the line memory 16 is read out and displayed on the CRT 12 via the D/A converter io and the amplifier 11. 3
When the calculation results for the 5th and 4th lines are stored in the line memory 17, the switches S3 and S4 are inverted, and the calculation results for the 5th and 6th lines are stored in the line memory 17.
6, while the line memory 17 is read out and displayed.

By using the two line memories 16 and 17 alternately in this way, there is no time delay, and the composite images H1 to H4, which are weighted averages of each group of four pixels, are displayed on the CRT 12 and correspond to the images F1 to F4 in Fig. 1. will be displayed.

In this way, in order to perform recording after the image arrangement has been confirmed by the display image of the CRT 12, the signal C3 synchronized with the recording device by the output of the clock pulse generator 6 is selected by the controller 9 and the multiplexer 7, and the
Address counter 4 and Y address counter 5 are (1, 1
) ~ (2M, 1), (1, 2) ~ (2M, 2)... (
Addresses are output in the order of 1,2N) to (2)1.2N) and the image data in the multiple image storage section 3 is read out. The output of the multiple image storage unit 3 is passed through a D/A converter 18 and an amplifier 19 to form a time-series composite image signal, and the output is sent to an acousto-optic element (A1
0 element) 20 is driven. The output light of the laser oscillator 21 is deflected by a mirror 22 and then modulated in brightness by an acousto-optic element 20, and then reflected by a rotating polygon mirror 23 into a silver halide film 24.
Scan the top in a straight line. The film 24 is moved by a sub-scanning system (not shown) in a direction perpendicular to the linear scanning by the rotating polygon mirror 23, and as shown in FIG. 3, images corresponding to FIG.
J4 is recorded.

FIGS. 5 and 6 are 6-frame images F1 to F1 shown in FIG.
This is another example in which F6 is arranged. Figure 5 is the 4th
Corresponding to the figure, the multiple image storage section 3 in FIG. 3 has a storage capacity for 6 frames, that is, 2M.3N. Note that the case where an image for one frame or four frames is displayed on the CRT 12 is the same as in the previous embodiment.

In addition, when displaying an image for 6 frames on the CRT 12, the outputs of the X address counter 4 and Y address counter 5 are (1, 1) to (2M, 1), (1, 2) to (2M
,2),@Fist・,(1,3!1) ~(2%, 3M)
This can be realized by adding a line memory 25, an adder 26, and a divider 27 as shown in FIG. The process up to the output of the adder 15 is the same as in the previous embodiment,
The adder 15 outputs the result of addition of four pixels. That is, the address (1, 1) + (2, 1) + (1, 2) + of the multiple image storage unit 3 is for two lines of the multiple image storage unit 3.
(2,2), (3,,1)÷(4,1,)+(3,
2) + (4, 2), ・11 contest (2 to 1, 1) + (2M,
The adder 15 outputs the addition result of the contents of 1)+(2M-1,2)+(2M,2). In this embodiment, this is stored in a line memory 25 similar to the line memory 14.

next.

The third line of the multiple image storage unit 3 is added by the adder 15, and the result is (1,3)÷(2,3), (3,3)+(4,3
), ...(2M-1,3)+(2M,3) are obtained, and this and the output of the line memory 25 are respectively added to the adder 26.
When added, the output of the adder 26 is (1, 1) + (
2,1)+(1,2)+(2,2)+(1,3)+(2
,3) , (3,1)+(4,1)+(3,2)+(
4,2)+(3,3)+(4,3), fist・,(2
M-1,1)+(2M,1)+(2t1.2)+(2M
, 2)+(2M-1,3)+(2M,3) and 2#3=6
The pixel addition result is obtained. This is divided into 1 by the divider 27.
By dividing by /6, the average value of 6 pixels is obtained.

This calculation result is then used in the line memory 1 shown in FIG.
6. Similarly, a composite image obtained by averaging the six pixels of one group is displayed on the CRT 12. In addition, if accuracy of display brightness is not required, the divider 2
Even if the lower 2 bits are truncated without using 7 and the number is reduced to 1/4, there is no problem in using it.

Also, in this example, M is treated as an even number and N is treated as a multiple of 3, but if M and N are not divisible by 2.3,
Even if you ignore the extra pixels, there is almost no problem since they are at the edges of the image.

FIG. 7 shows still another embodiment, and is a configuration example in which pixels in the X direction, which is the row direction, are averaged, and pixels in the Y direction, which is the column direction, are displayed intermittently. This corresponds to the adder 13, line memory 14, and adder 15 in FIG. The image data read from the multiple image storage section 3 is transferred to the latch 13a and the addition circuit 1 via the changeover switch S1.
CR via adder 13 and latch 28 consisting of
It is sent out at T12. The adder 13 performs addition for one pixel using a chip 13a and an adder circuit 13b, and the latch 28 is a latch for one pixel similar to the latch 13a, and is designed to control timing.

FIG. 8 is a timing chart of the contents of each part a to d in FIG. is added. Since the example shown in FIG. 7 is the addition of two pixels, averaging is performed by switching the lower one bit of the output of the latch 28, as in the example shown in FIG. Furthermore, as can be seen by comparing the signals a and d, the X address counter 4 is driven by a clock that is twice as fast as the clock output C1.

In addition, the Y address counter 5 is also driven by a clock that is twice as fast as when displaying only one frame, and when the lower 1 bit of the output of the Y address counter 5 is invalidated, addresses in the Y direction are selected intermittently, and the CRT 12 For example, (1,1)+(2,1),・@(2M-1,
1) + (2M, 1) , (1, 3) + (2, 3), --
--(2M-1,3)+(2M,3), -----(
1,2N-1)+(2,2N-1), number, -(
The average of 2%-1,2N-1)÷(2M,2N-1) is displayed.

According to this embodiment, as is clear from comparing FIGS. 3 and 7, the line memory 14 and adder 15 in FIG.
, the line memories 16 and 17, and the changeover switches S3 and S4 can be omitted, making it possible to greatly simplify the hardware configuration.

As explained above, according to the image recording device according to the present invention, by combining and displaying a plurality of images, it is possible to prevent defects such as recording unnecessary images or erroneous image arrangement. I can do it. Furthermore, it becomes obvious at a glance what kind of image is recorded on one hard copy.

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram when 4-frame images are arranged on one hard copy, Figure 2 is an explanatory diagram when 6-frame images are arranged on one hard copy, and Figure 3 and the following are illustrations of the book. An embodiment of the image recording device according to the invention is shown, FIG. 3 is a block circuit diagram thereof, FIG. 4 is an explanatory diagram of a state in which four frames of images are stored in a multiple image storage unit, and FIG. 5 is an explanatory diagram of a state in which four frames of images are stored in a multiple image storage unit. 6 is a block circuit diagram of another embodiment, FIG. 7 is a block circuit diagram of still another embodiment, and FIG. 8 is a timing chart thereof. be. 2 is an A/D converter, 3 is a multiple image storage unit, 4 is an X address counter, 5 is a Y address counter, 8 is a frame counter, IO is a D/A converter, 12 is a CR
T, 13.15.26 is an adder, 13a and 28 are latches, 13b is an addition circuit, 14.16.17.25 is a line memory, 20 is an acousto-optic element, 21 is a laser oscillator,
23 is a rotating polygon mirror, 24 is a film, and 27 is a divider. Patent applicant Canon Co., Ltd. Figure 4 Figure 5 Figure 6

Claims (1)

[Scope of Claims] 1. It has a multiple image storage unit that stores multiple image data, reads out the image data stored in the multiple image storage unit, and records the multiple images on one hard copy. an image recording device that reads the stored image data and performs image processing to obtain one pixel by averaging a plurality of pixels; and displaying a composite image compressed by the image processing means on a display device. An image recording device comprising a display means. 2. The image recording apparatus according to claim 1, further comprising a storage section for temporarily storing the results of the image processing. 3. The image recording apparatus according to claim 1, further comprising a selection means for reading the stored image data and selecting whether or not to perform the image processing when displaying on the display device. 4. The image recording apparatus according to claim 1, wherein the averaging image processing is performed in the row direction of the image data array, and the compression is performed by extracting pixels in the column direction. 5. The image recording apparatus according to claim 1, wherein recording on the hard copy is performed using a laser beam.