JPS61245684A - Scanning line duplexing and interpolating system - Google Patents

Abstract

PURPOSE:To generate no distortion at the boundary of a reproducing image and to prevent the extension of a line flicker and an image and the generation of a stripe pattern by generating two specified intermediate values and using that of a smaller absolute value as an interpolating value. CONSTITUTION:When a video signal by the interlaced scanning of 2-to-1 is brought to a system conversion to a video signal by a sequential scanning, a sampled value in the optional time of a sampled value obtained by sampling the video signal, and the sampled value of one horizontal scanning period before of a sampled value y1 are denoted as y1, y0, respectively. Also, with respect to the sampled value y1, the sampled value of ((1 field period)+(1/2 horizontal scanning period)) before, and the sampled value of ((1 field period)-(1/2 horizontal scanning period)) after are denoted as x0 and x1, respectively. The smaller value of the intermediate value of the sampled values x0, y0 and x1 and the intermediate value of x0, y1 and x1 is used as an interpolating value Z and a scanning line duplexing interpolation is executed.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a video signal processing method in a television receiver or the like, and in particular, to converting a 2:1 interlaced scanning video signal into a sequential scanning video signal. The present invention relates to a scanning line doubling interpolation method used in this case.

(Conventional example) It is well known that the transmission and reception of chill vision images is carried out according to a specific standard television system. The interlaced scanning method has been adopted as a scanning standard, and has the characteristic that it can reproduce an image with a large number of images per second as an image with a large number of images per second. The interlaced scanning system widely adopted in the television systems currently in practical use is mainly the two-clam-one interlaced scanning system.

By the way, the image reproduced by the standard television system, which has adopted the interlaced scanning method as the scanning standard, has long been considered to be satisfactory for practical purposes41.
．． However, as the performance of various parts of television receivers improved, the demand for improved image quality of reproduced images also became stronger, and as a means of meeting this demand, video signals based on the interlaced scanning method were developed. Converting the image into a video signal according to a progressive scanning method, for example, 60 fields per second, 30 images per second, 2:1 interlaced scanning,
A video signal capable of producing a reproduced image with 525 scanning lines constituting one image (262.5 scanning lines constituting one field) is transmitted in a period of 1/60 second. Attempts have been made to convert the format into a video signal so as to produce 525 reproduced images.

FIG. 6 is a block diagram showing an example configuration of a conventional scanning line doubling interpolation method used when converting a video signal based on 2:1 interlaced scanning into a video signal based on progressive scanning. In the figure, 19 is an input terminal for the video signal being processed, and in the illustrated example, the luminance signal and the chrominance signal share a band within the band of the luminance signal with respect to the input terminal 19. It is assumed that a multiplexed color television video signal (for example, an NTSC color television video signal) is supplied.

The color television video signal supplied to the input terminal 19 is separated into a luminance signal (■) and a carrier color signal C by a YC separation circuit 20, and the luminance signal Y is sent to a scanning line doubling circuit 2.
1, and the carrier color signal C is supplied to a demodulator 22.

The demodulator 22 outputs two color difference signals (R-Y) and (B-Y) from the carrier color signal C.
) is supplied to the scanning line doubling circuit 23, and also.

The color difference signal (B-Y) is supplied to the scanning line doubling circuit 24. The above-mentioned scanning line doubling circuit 21 converts the luminance signal Y according to the 2:1 interlaced scanning method applied thereto into a luminance signal Y2 according to the progressive scanning method and outputs it. The doubling circuit 23 converts the color difference signal (R-Y) according to the 2:1 interlaced scanning method applied thereto into
The method is converted into a color difference signal (R-y) 2 according to the progressive scanning method and outputted, and the scanning line doubling circuit 24 converts the color difference signal (R-y) according to the 2:1 interlaced scanning method given thereto. R-y) is converted into a color difference signal (R-y) according to the progressive scanning method.
Y) Convert the format to 2 and output.

Now, the color difference signal (R-Y) according to the 2:1 interlaced scanning method
the scanning line doubling circuit 23, which converts the signal into a color difference signal (R-Y) 2 according to the progressive scanning method and outputs the converted signal;
The above-mentioned scanning line doubling circuit 24 converts the color difference signal (B-Y) according to the 2:1 interlaced scanning method into the color difference signal (B-Y) 2 according to the progressive scanning method and outputs the converted color signal. Since the frequency band (in the vertical direction) of is relatively narrow, as shown in (,a) of FIG. A configuration in which a signal of a new scanning line to be inserted between the two horizontal scanning lines described above can be created by using the value zy=(y o + y 1)/2 as an interpolated value, that is, , an interpolation signal can be generated by a method conversion using a doubling interpolation method using intra-field processing.

On the other hand, the scanning line doubling circuit 21 converts the luminance signal Y according to the 2:1 interlaced scanning method into the luminance signal Y2 according to the progressive scanning method and outputs the converted signal.

Method conversion using the doubling interpolation method using intra-field processing explained with reference to (a) in FIG. 7, or the doubling interpolation method using inter-frame processing shown in (, b) of FIG. A device configured to be able to create an interpolated signal by using the following method is used.

The above-mentioned doubling interpolation method using interframe processing means that one frame period (1 in the figure) is as shown in FIG. 7(b).
2 adjacent units separated by a period of 130 seconds)
Average value Zx of two signals xo and xi = (xo+xl)/2
In this method, a signal for a new scanning line to be inserted between two horizontal scanning lines is created by using the interpolation value as an interpolation value.

Now, the mode of interpolation of the video signal in the case of the above-mentioned conventional doubling interpolation method and the locations of problems will be explained with reference to FIGS. 8 to 11 as follows.

α1. shown in FIG. 8(a). α2. α3. α4
. . . is the video signal before double fhi interpolation Jt, that is, the already mentioned luminance I and Y1 color difference signals (R-/),
(B-Y), etc. Existence of image information in the name 1 tree scanning period (III period) arranged on the time axis [1. This is the part where α1. α2. α3. The portions between the portions indicated by α4... are portions where the horizontal synchronization signal is supposed to exist.

In addition, (d) of FIG. 8 shows the above-mentioned α1. α2. α3. Image information α1' is obtained by time-axis compressing the information of each part of α4, . . . into 172 pieces.

α2', α3'..., interpolated signal β12, etc. shown in FIG. 8(c). β23. A schematic diagram of a scanning line doubled signal in which the image information of each part of β34... is time-axis compressed to 1/2 and the image information is sequentially and alternately arranged along the time axis. It is.

Next, we will discuss the differences between scanning line doubling interpolation by intra-field processing and scanning line doubling interpolation by interframe processing applied in the case of the conventional doubling interpolation method, and the distortion that occurs in each case. This will be explained with reference to FIGS. 9 to 11.

The figures shown in FIGS. 9(a) to 9(c), respectively, are 2
The position of the pixel generated by the video signal (original signal) before double interpolation and the position where the interpolated pixel should be placed are indicated by white circles, and the positions where the interpolated pixel should be placed are indicated by black circles. The marks are respectively displayed on a time-perpendicular two-dimensional space plane, and the vertical lines in the rain connect each pixel position within the same field.

Each pixel is assumed to be sampled, and its value is assumed to be a value of 0 or more; however, for the sake of convenience, the analog value itself is used as the numerical value, rather than a binary number. .

In the figure, the numerical value displayed inside the white circle indicating the position of the pixel represents the numerical value (sample value) of the pixel, and
In the illustrated example, the numerical value of the pixels within the area surrounded by the dotted line is 1, and the numerical value of the pixels outside the area is O.

(In addition, the meaning of the white circle mark and the numerical value shown in the figure =7- in the explanation about Figure 9, and the meaning of the vertical line in the figure,
For details on how to set the area, see Figures 5, 10, and 11.
The same applies to each case in the figure).

Figure 9 (a) shows an example of a still image where part of the screen is bright, and Figure 9 (b) is an example of a moving image where part of the screen is brightened for a moment. , (c
) is an example of a video in which bright areas move from the top to the bottom of the screen.

The drawings shown in FIG. 10(a) and FIG. 11(a) show the arrangement of pixels generated by a still image video signal (H signal) before double interpolation. This drawing corresponds to FIG. 9(a), and the drawings shown in FIG. 10(b) and FIG. 11(b) have a part of the screen brightened for a moment. This drawing corresponds to (b) of FIG. 9, showing the arrangement of pixels generated by the video signal (original signal) before the video signal of the moving image is doubled and interpolated. (c) of Figure 1O and Figure 11
The drawing shown in (c) of the figure shows the arrangement of pixels caused by the video signal of a moving image in which the bright part moves from the top to the bottom of the screen.
).

And (a) to (c) in Fig. 10 are the same as (a) in Fig. 9.
The interpolated pixels based on the interpolated values obtained by performing intra-field processing on the video signals shown in ~(c) are shown in Figure 9().
It is a diagram showing the state inserted at the positions of the black circles in a) to (c), and (,) to (c) of FIG.
Regarding the video signals shown in (a) to (C) of the figure,
9 is a diagram showing a state in which interpolated pixels based on interpolated values obtained by performing interframe processing are inserted at the positions of black circles in (a) to (e) of FIG. 9. FIG.

First, interpolated pixels based on interpolated values obtained by performing intra-field processing on a video signal that produces a pixel arrangement as shown in (,) to (C) in Fig. 9 are
In the case of a video in which part of the screen is brightened for a moment in the figures shown in (,) to (e) of Figure 10, which respectively show the state inserted at the position of the black circle mark in (c). In the case of (b) in Figure 10, which shows
By inserting interpolated pixels based on the interpolated values obtained by performing intra-field processing at the positions of the black circles in (b) of the figure, interpolation is performed without any distortion in the area surrounded by the dotted line. It is clear that

However, the interpolated pixels based on the interpolated values obtained by performing intra-field processing on the still image video signal that produces the pixel arrangement shown in FIG. 9(a) are as shown in FIG.
If you look at the diagram shown in (,) in Figure 10, which shows the black circle inserted at the position of the black circle in By inserting the interpolation pixel, the boundary with the 0 part) changes to the boundary shown by the dashed-dotted line in (a) of Figure 10, and the pixel value moves downwards by -L for each field. , line flicker becomes noticeable at the boundary of the area.

In addition, in-field processing is applied to a video signal that produces a pixel arrangement as shown in FIG. Looking at the time shown in FIG. 10 (c), which shows that the interpolated pixel based on the interpolated value obtained in [7] is inserted at the position of the black circle in FIG. 9 (c), The boundary of the area surrounded by the dotted line before interpolation (pixel value is 1)
By inserting interpolated pixels, the boundary between the 0 part and the 0 part changes to a boundary as shown by the dashed-dotted line in Fig. 10(c), and 11 in one vertical direction is expanded compared to the original image. It turns out that it becomes visible.

Next, the interpolated pixels based on the interpolated values obtained by performing interframe processing on the video signal that produces the pixel arrangement shown in FIG. 9 (a) to (c) are shown in FIG. 9 (,). ~(
In the figures shown in (a) to (c') of Fig. 11, which respectively show the state inserted at the position of the black circle mark in c), the pixel as shown in (a) of Fig. 9 In Fig. 11 (
In case a), the interpolated pixel is inserted at the position of the black circle in (a) of Figure 9 based on the interpolated value obtained by performing interframe processing on the position of the black circle in (a) of Figure 9. It is clear that interpolation is performed without causing any distortion in the area surrounded by the dotted line.

However, in the case of (b) in Figure 11, which shows a video where part of the screen is brightened for a moment, interframe processing is applied to the position of the black circle in (b) of Figure 9. The first image shows that the interpolated pixel based on the interpolated value thus obtained is inserted at the position of the black circle in FIG. 9(b).
Looking at (b) in Figure 1, the boundary of the area surrounded by the dotted line before interpolation (the boundary between the part with a pixel value of 1 and the part with a pixel value of O) between the beginning part of the image and the end part of the image. It can be seen that by inserting interpolation pixels, the boundary changes to a boundary as indicated by the dashed-dotted line in FIG.

In addition, interframe processing is applied to a video signal that produces a pixel arrangement as shown in FIG. If we look at (c) in Figure 11, which shows that the interpolated pixels based on the interpolated values obtained in this way have been inserted at the positions of the black circles in (c) in Figure 9, we can see that
As in the case of (c) in Figure 0, the boundary of the area surrounded by the dotted line before interpolation (the boundary between the part with a pixel value of 1 and the part with a pixel value of O) is changed to (c) in Figure 11 by inserting interpolated pixels. It can be seen that the boundary changes to look like the dashed-dotted line in , and the width in the vertical direction appears to be wider than the original image.

(Problems to be Solved by the Invention) As described above, in the conventional scanning line doubling interpolation method,
Application of this method caused distortion at the boundaries of the reproduced image, resulting in line flicker, image spreading, and striped patterns, so a solution was needed.

(Means for Solving the Problems) The present invention is a means for sampling a video signal based on 2:1 interlaced scanning when converting a video signal based on 2:1 interlaced scanning into a video signal based on progressive scanning. , the sample value obtained by the sampling means at an arbitrary time is yl, the sample value 1 horizontal scanning period before the sample value y1 is yo, and the sample value y1 is Let the sample value before "(1 field period) + (1/2 horizontal scanning period)" be XO for the sample value y1, and furthermore, let r (1 field period) - (1 a first intermediate value generation means for obtaining a sample value representing an intermediate value for each of the above sample values x0, x1, y0, with the sample value after 2 horizontal scanning periods) as x1; sample value x
o, The present invention provides a scanning line doubling interpolation method comprising a sample value obtained by a value generating means and means for determining the smaller absolute value as an interpolated value.

(Example) Hereinafter, with reference to the attached drawings, the scanning line doubling M of the present invention will be explained.
The specific contents of the rI method will be explained in detail.

FIG. 1 is a block diagram of an embodiment of the scanning line doubling interpolation method of the present invention, and FIGS. 2 and 3 are block diagrams of the scanning line doubling interpolation method shown in FIG. FIG. 4 is a block diagram showing an example of the configuration of the constituent parts, and FIG. 4 is a diagram used to explain the configuration principle of the scanning line doubling interpolation method of the present invention.

First, the principle of construction of the scanning line doubling interpolation method of the present invention will be explained with reference to FIG. In FIG. 4, yl is a sample value at an arbitrary time, yo is a sample value one horizontal scanning period before the sample value y1, and xo is [(1 field period) + (1/2 horizontal scanning period)'' previous sample value, xl is the sample value after 11 field periods - (1/2 horizontal scanning period) with respect to the sample value y1, and Sample value (pixel value)
xo, 'x 1 , yo, and yl are arranged in a time-perpendicular two-dimensional space. For convenience, the above sample values are assumed to be positive values including 0 (corresponding to the fact that when sampling a video signal and converting it from analog to digital, positive logic sampling and quantization is generally performed) )
.

Furthermore, Z shown at the center of the four sample values xo, xi, yo, and yl arranged in the time-vertical two-dimensional space is the horizontal scanning line from which the sample value yo was obtained. This is an interpolated value that should be placed at an intermediate position between the sample value y1 and the horizontal scanning line from which the sample value y1 was obtained.

In the scanning line doubling interpolation method of the present invention, the sample value processing described above is used. , yo, xi, and X Or 3” *
Scanning line doubling interpolation is performed by using the smaller value of x1 as the interpolated value 2, and the interpolated value 2 is calculated by calculating the following equation. It will be done.

Z = MIN (MID(xo, y o, x 1)
;MID(xo, y 1. x l)) However, MI
N(p+ q) is a formula to obtain the smaller of P'y q, and MID(p t' q + r) is P+ '
This is a formula for obtaining an intermediate value between I and r.

The principle of the scanning line doubling interpolation method of the present invention described above is applied to a video signal that produces the arrangement of pixels as shown by (,) to (c) in FIG.
The results of double interpolation are shown in (,) to (c) in Figure 5.
).

As in Soren, (,) in Figure 9 shows an example of a still image where part of the screen is bright, and (b) in Figure 9 is an example of a moving image where part of the screen is brightened for a moment. And furthermore,
FIG. 9(c') is an example of a moving image in which a bright part moves from the top to the bottom of the screen.

The drawing shown in (a') of FIG. 5 is a diagram in which the image signal (original signal) of a still image before being subjected to doubling interpolation by the scanning line doubling interpolation method of the present invention is used. This drawing corresponds to FIG. 9(a) showing the arrangement of pixels, and the drawing shown in FIG. 5(b) shows a part of the screen brightened for a moment. FIG. 9 shows the arrangement of pixels generated by the video signal (original signal) before the video signal of the moving image is subjected to double interpolation by the scanning line doubling interpolation method of the present invention. This is a drawing corresponding to b), and the drawing shown in Fig. 9 is a diagram corresponding to (c) of FIG. 9 showing the arrangement of pixels generated by a video signal (original signal) before being subjected to doubling interpolation by the scanning line doubling interpolation method of the invention.

As can be seen from (a) to (C) in FIG. 5, according to the scanning line doubling supplementary method of the present invention, the original signal to which scanning line doubling interpolation is to be performed is a still image. Even if the original signal to which scanning line doubling interpolation is to be performed is a video signal of a moving image in which a part of the screen is made brighter for a moment, or scanning line doubling Even if the original signal to be interpolated is a video signal of a moving image in which bright areas move downward from the screen, in both cases the original pixel arrangement (Figure 9) (a) to (c) of
According to the scanning line doubling interpolation method of the present invention, the interpolation processing is performed accurately in the area having the same boundary line as the boundary line of the area in ). (c) and FIGS. 11(a) to (c).
The drawbacks of the conventional example described above can be satisfactorily solved.

In the block diagram of FIG. 1 showing an embodiment of the scanning line doubling interpolation method of the present invention, 1 to 3 are delay circuits each configured to have a predetermined delay time. The delay circuit 1 is supplied with a video signal x1, which is subjected to scanning doubling interpolation, via a line Ql. Further, the video signal x1 is supplied to an intermediate value extraction circuit 4 and an intermediate value extraction circuit 5.

The delay times in the delay circuit 1 and the delay circuit 3 described above are each "(1 field period) - (1/2 horizontal scanning period)", and the delay time in the delay circuit 2 is 11 horizontal scanning periods. (IH)J.

As mentioned above, the video signal x1 supplied from the line Q1 to the delay circuit 1 is
-(1/2 horizontal scanning period)" is made into the signal y1 and is supplied to the delay circuit 2, and the line Q
2 to the intermediate value extraction circuit 5.

The delay circuit 2 outputs an output signal yo obtained by adding a delay of one horizontal scanning period IH to the signal yt input thereto, supplies it to the delay circuit 3 and the delay circuit 7, and also outputs the output signal yo through the line Q3. and is applied to the intermediate value extraction circuit 4.

In the delay circuit 3 described above, the signal yo input thereto is r (1 field period) - (1/2 horizontal scanning period).
The signal xO, which has been delayed by the amount of time, is outputted via the line Q4, and the output signal xO is supplied to the intermediate value extraction circuit 4 and the intermediate value extraction circuit 5.

The two intermediate value extraction circuits 4 and 5 are each configured to be able to output a signal having an intermediate value of the three input signals supplied to them, and Examples of configurations 4 and 5 are illustrated in FIG.

In FIG. 2, U, V, W are the three input terminals to which the three input signals supplied to the intermediate value extraction circuit 4.5 are applied individually, and Q is the output of the intermediate value signal. It's a signal. When the intermediate value extraction circuit shown in FIG. 2 described above is used as the intermediate value extraction circuit 4,
Its input terminal U is supplied with a signal x1, its input terminal ■ is supplied with a signal yo, and its input terminal W is supplied with a signal xo.On the other hand, as shown in FIG. When the intermediate value extraction circuit 5 is used as the intermediate value extraction circuit 5, the signal x1 is supplied to its input terminal U, the signal y1 is supplied to its input terminal The signal xO is supplied to W.

The intermediate value extraction circuit shown in FIG. 2 is used as either of the two intermediate value extraction circuits 4 and 5 as described above, and it is Since the same intermediate value extraction operation is performed even when used as the intermediate value extraction circuit 5 or as the intermediate value extraction circuit 5, the configuration and operation of the intermediate value extraction circuit shown in FIG. 2 will be described below. In the description, it is assumed that the signals supplied to the three input terminals U, V, and W described above are the signals U, V, and W, respectively. Therefore, when the intermediate value extraction circuit shown in FIG.
When the intermediate value extraction circuit corresponding to nYo and XO and shown in FIG. 2 is used as the intermediate value extraction circuit 5, the three input signals U in the following explanation are
.

It is sufficient to consider that v and w correspond to the three input signals xi, yl, and xo, respectively.

In the intermediate value extraction circuit shown in FIG. 2, blocks 11, 12, 1 are used as its constituent circuits.
3 are two-manpower maximum value extraction circuits. For example, the two-manpower maximum value extraction circuit shown in FIG.
) can be used.

In the two-person maximum value extraction circuit illustrated in FIG. 3(a), 19 is a comparator, and 20 is a switch circuit. A and B are supplied.

When the two input signals supplied to the comparator 19 described above are A and B, when the two input signals A and B are A)B, a signal of logic 1 is output as a comparison and output signal. Furthermore, when the two input signals A and B are A(B and A=H), a logic 0 signal can be output as the comparison output signal. The comparison output signal from the device 19 is
It is supplied to the switch circuit 20 as its switching control signal.

As mentioned above, the switch circuit 20 to which the switching control signal is supplied from the comparator 19 outputs the signal A when the switching control signal applied thereto is of logic 1; If the received switching control signal is of logic O, the circuit is configured to output signal B.

In the two-man powered maximum value extraction circuits 11 to 13 as described above, the two-man powered maximum value extraction circuit 11 is given signals U and V as two input signals A and B thereto, and also,
The two-manual maximum value extraction circuit 12 receives the signal ■ as its two input signals A and B.

W is given to it, and the two-manual maximum value extraction circuit 13 receives the two input signals A and B as described above.
Signals output from the maximum value extraction circuits 11 and 12 of human power are supplied respectively.

Therefore, the two-manpower maximum value extraction circuit 13 outputs the maximum signal among the three input signals U, V, and W sent to the intermediate value extraction circuit, and the output signal is output from the three-manpower subtraction circuit 13. 18 as one of its subtracted signals.

In the intermediate value extraction circuit shown in FIG. 2, blocks 14, 15, 1 are used as its constituent circuits.
6 are two-manpower minimum value extraction circuits, and the two-manpower minimum value extraction circuit i is, for example, shown in FIG. 3 (b).
) can be used.

In the two-man minimum value extraction circuit illustrated in FIG. 3(b), 21 is a comparator and 22 is a switch circuit. A and B are supplied.

The above-mentioned comparator 21 compares and outputs a logic 1 signal as an output signal when the two input signals A and B are A<H. In addition, when the two input signals A and B are A)B and A=B, a logic O signal is output as a comparison output signal. The comparison output signal from the comparator 21 is supplied to the switch circuit 22 as its switching control signal.

As described above, the switch circuit 22 to which the switching control signal is supplied from the comparator 21 outputs the signal A when the switching control signal applied thereto is of logic 1; If the received switching control signal is of logic O, signal B is output.

In the two-man powered minimum value extraction circuits 14 to 16 as described above, the two-man powered minimum value extraction circuit 14 is supplied with signals U and V as two input signals A and B thereto, and also,
The two-manual minimum value extraction circuit 15 receives a signal V as its two input signals A and B.

W is given □, and furthermore, a two-manpower minimum value extraction circuit 16
The two input signals A and B therefor are supplied with the signals respectively output from the two-manual minimum value extraction circuits 14 and 15 described above.

Therefore, from the two-man minimum value extraction circuit 16, U, V
, W is output, and that output signal is supplied to the three-man subtraction circuit 18 as the other one of its subtraction signals.

In the intermediate value extraction circuit shown in FIG.
This is a human-powered addition circuit, and in this three-person addition circuit 17, three input signals U are supplied to the intermediate value extraction circuit.
, V, and W are added.

Furthermore, in the intermediate value extraction circuit shown in FIG.
The block 18 used as its constituent circuit is 3
This is a human-powered subtraction circuit, and in this three-man-powered subtraction circuit 18, the two-man powered subtraction circuit 18 shown in block 13 described above is extracted from the output signal from the three-man powered addition circuit 17, which is supplied as a signal to be subtracted. The output signal from the maximum value extraction circuit 13, that is, the maximum value signal among the three input signals U, V, and W supplied to the intermediate value extraction circuit, and the two The output signal from the manual minimum value extraction circuit 16, ie, the minimum value signal of the three input signals U, V, and W supplied to the intermediate value extraction circuit, is subtracted.

Therefore, the output signal Q sent from the three-man powered subtraction circuit 18 to the output terminal Q is as follows: Q = U + V + W - MAX (U, V, W) -, MIN (U
, V, W), and this output signal Q is the intermediate value among the three input signals U, V, and W supplied to the intermediate value extraction circuit shown in FIG. It is something that takes a value, that is, an intermediate value.

Therefore, the intermediate value extraction circuit 4 is the intermediate value extraction circuit 4.
In the case of three input signals U to it.

V, W are x 1. yo, xo, the signal supplied from the intermediate value extraction circuit 4 to the minimum value extraction circuit 6 via the line Q5 is the intermediate value signal of the above-mentioned signals X'r'IO, XO. , When the intermediate value extraction circuit 5 is the intermediate value extraction circuit 5, the three input signals cy, v, w are x1. y1. Because xo,
From the intermediate value extraction circuit 5 to the minimum value extraction circuit 6 via the line p6
The signal supplied to x1. y].

This is a signal with an intermediate value within xo.

As the above-mentioned minimum value extraction circuit 6, one having the configuration already described with reference to FIG. 3(b) can be used.
The smaller of the two input signals is applied to the first memory device 8 .

Therefore, the output signal 2 from the above-mentioned minimum value extraction circuit 6 is an interpolated signal (interpolated value) as shown by the following formula.

As the first memory device 8, for example, (
As shown in C), there are two line memories (IH
A configuration in which delay circuits 23 and 24 are connected in parallel can be used. In the first memory device 8 described above, one of the line memories, for example, the line memory 23 (24)
When signal 2 is being written to the other line memory, for example, line memory 24 (23), the signal Z written l horizontal scanning period ago is read out during 172 horizontal scanning periods. The two line memories 23 and 24 are configured to be able to sequentially and alternately perform operations such as the following in each horizontal scanning period.

On the other hand, the signal yo output from the delay circuit 2 described above is
On the other hand, the delay circuit 7 provides the required time delay, that is,
After the intermediate value extraction circuit described above is given a time delay equal to the time delay caused to the signal to be processed during signal processing in the intermediate value extraction circuits 4 and 5 and the minimum value extraction circuit 6,
is written in the second memory device 9.

The second memory device 9 has the same configuration as the first memory device 8 described above, and the two line memories 23 and 24 used in its configuration are one of the line memories, For example, when the signal yo is written to the line memory 23 (24), the signal yo written one horizontal scanning period ago is 1/ The two line memories 23 and 24 are arranged to sequentially and alternately perform operations such as reading out data during two horizontal scanning periods every one horizontal scanning period.

The interpolated signal Z read out from the first memory device M8 and compressed in time axis to 1/2 and the second memory device w
The signal yo read from 9 and compressed to 1/2 on the time axis is supplied to the switching circuit 10,
Interpolated signals 2 and 9 are the interpolated signals whose time axis has been compressed to 1/2 and the signal yo whose time axis has been compressed to 1/2 on the time axis.
are sequentially and alternately switched by the switching circuit 10, and from the switching circuit 10, the interpolated signal Z compressed to 172 on the time axis as described above, and the
The signal in which the time-axis compressed signal yo and the signal yo are sequentially arranged alternately ((d) in FIG. 8) is 4! XQ1
will be sent to.

(a) to (d) of FIG. 8 are schematic diagrams explaining the arrangement of the signal V1pVOpZ and the output signal from the switching circuit 10 on the time axis, and (a) of FIG. So, ■
In the rain, image information α1. is arranged for each horizontal scanning period (IH). α2. It is shown as α3... 8th
(b) in the figure is the signal yO, which means that the signal y1 described above is 1.
This signal is delayed by a horizontal scanning period I].

Next, (C) of FIG. 8 is the interpolation signal 2, and the image information β12 in the figure is the image information α1. The image information β23 corresponds to the image information α2. Further, image information β34 corresponds to image information α3. Image information β12. β34.
β34... are arranged in t order on the time axis.

FIG. 8(d) shows the image information α1. α2. α3・
...The image information α1'', α2', α3', etc. (original video signal) whose time axis has been compressed to 1/2, and the image information β12, β34, β34, etc. described above are 1/2 Image information β12', β34', β34', etc., compressed in time axis
(interpolated signals) are sequentially and alternately arranged on the time axis every 1/2 horizontal scanning period (in Fig. 8, illustration of time delays caused during signal processing is omitted). ).゛The signal output from line Q7 as described above has the scanning lines doubled by the scanning line doubling interpolation method of the present invention, and the signal complies with the scanning standard of 2:1 interlaced scanning. The video signal is format-converted into a video signal that conforms to the progressive scanning scanning standard.

In the embodiments described so far, the sample values X O+ It was supposed to be carried out by
In carrying out the scanning line doubling interpolation method of the present invention, it is of course possible to use negative logic sample data. All you have to do is take the value and convert negative logic to positive logic.

In the description of the embodiment, the signals targeted by the scanning line doubling interpolation method of the present invention were luminance signals and color difference signals, but the signals targeted by the scanning line doubling interpolation method of the present invention It goes without saying that the signal content does not matter as long as the signal used is a video signal that conforms to the 2:1 interlaced scanning standard.

(Effects) As is clear from the above detailed explanation, the scanning line doubling interpolation method of the present invention converts a video signal conforming to the scanning standard of 2:1 interlaced scanning into a video signal conforming to the scanning standard of progressive scanning. When converting, a means for sampling the video signal according to the scanning standard of 2:1 interlaced scanning is used, and a sample value at an arbitrary time among the sample values obtained by the above-mentioned sampling means is
Let l be the sample value 1 horizontal scanning period before the sample value y1, and let yo be the sample value 1 horizontal scanning period before the sample value y1, and further, ``(1 field period) + (1/2 horizontal scanning period)'' before the sample value y1. Let the sample value of
, xl, yo;
A second intermediate value generation means for obtaining a sample value indicating an intermediate value between them for i and yl, a sample value obtained by the first intermediate value generation means described above, and a second intermediate value generation means described above. According to the scanning line doubling interpolation method of the present invention, scanning line doubling interpolation is performed. Even if the original signal to be processed is a video signal of a still image, or the original signal to be subjected to scanning line doubling interpolation is a video signal of a moving image in which a part of the screen is made bright for a moment. In either case, the original signal to be subjected to scanning line doubling interpolation is a video signal of a moving image in which the bright part moves from the top to the bottom of the screen. As shown in Figure 5 (a) to (c), the original pixel array (accurate interpolation in the area with the same boundary line as the area boundary line in Figure 9 (,) to (c)) According to the scanning line doubling interpolation method of the present invention, see FIGS. 10(a) to 11(c) and 11(a) to 11(c) for the conventional example described above. The drawbacks of the conventional example explained above can be satisfactorily solved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the scanning line doubling interpolation method of the present invention, FIGS. 2 and 3 are block diagrams of an example of the configuration of component parts, and FIG. 4 is a scanning line doubling interpolation method of the present invention. Figure 6 is a block diagram of an example of the conventional scanning line doubling interpolation system.
The figure is a diagram for explaining the configuration principle and operating principle of the conventional scanning line doubling interpolation method. Part 8 is a diagram showing the arrangement of signals on the time axis. FIG. 2 is a pixel arrangement 1its diagram for explaining scanning line doubling interpolation. 1.2, 3, 7...delay circuit, 4. Death: Intermediate value extraction circuit, 6, 14 to 16: Minimum value extraction circuit for 2 signals,
8.9...1st. Second memory device, A>B:C:A A≦B:C=A A<B:C=A

Claims (1)

[Claims] When converting a video signal based on 2:1 interlaced scanning into a video signal based on progressive scanning, a means for sampling the video signal based on 2:1 interlaced scanning, and an arbitrary value in the sample value obtained by the sampling means. The sample value at time y1 is set as y1, the sample value one horizontal scanning period before the sample value y1 is y0, and
The sample value before "field period) + (1/2 horizontal scanning period)" is set as x0, and furthermore, the sample value after "(1 field period) - (1/2 horizontal scanning period)" for the sample value y1 is Assuming that the sample value is x1, each of the sample values x0, x1,
a first intermediate value generating means for obtaining a sample value representing an intermediate value of y0; and each sample value x0, x1, y1 described above.
a second intermediate value generation means for obtaining a sample value indicating an intermediate value between them; a sample value obtained by the first intermediate value generation means described above; and a sample obtained by the second intermediate value generation means described above. scanning line doubling interpolation method consisting of a means for setting the smaller absolute value of the