JPS61240496A - Dynamic type differential amplifier - Google Patents

Abstract

PURPOSE:To prevent the transient random movement of a differential amplifier transistor at time of impressing activation command signal by taking care not to directly connect the bit line and dummy bit line with the differential amplifier. CONSTITUTION:When the word line 16 is selected, only the voltage of the dummy bit line 9 drops with the voltage of the detection node B dropping faster than the voltage of the detection node C, outputting signal Sout to the output circuit 22. At the time of the activating command signal phiA shifting to a higher level, for instance, even if the FET 38 for the differential amplifier goes ON quicker than the FET 37 and node C begins to drop faster than node B, since nodes B, C and lines 8, 9 are not directly connected, the voltages of detection nodes B, C are not fedback to the bit line 8 and dummy bit line 9 and the gate voltage of FET 37 is still kept higher than the gate voltage of FET 38. In due time, the voltage of node C again rises exceeding the voltage of node B and the output circuit 22 correctly reflects the information of memory cell 10 to output the output signal Sout.

Description

[Detailed description of the invention] <Field of application> The great invention is a dynamic differential amplifier, in particular, when reading information from a semiconductor memory device, the voltage of a bit line connected to a memory cell is compared with a reference voltage. death.

The present invention relates to a dynamic differential amplifier that discriminates binary information stored in the memory cell.

<Prior Art> FIG. 1 is a diagram showing the configuration of a conventional differential amplifier 1 integrally integrated with a semiconductor memory device.
, each source is at a common node A.

Each drain is connected to a sensing node B, C, respectively, and each gate is cross-connected to a sensing node C, H, respectively.
A pair of N-channel field effect transistors for differential amplification (
(hereinafter referred to as N-type FET) 2.3 and the reference voltage source Vdd
A pair of N-type FE74.5 for precharging interposed between (5V) and M/-)'B and C, and a pair of discharge intervening between the common node and the ground voltage Vss. It is composed of N-type FETs 6 and 7. Detection node B
, C are connected to a bit line 8 and a dummy bit line 9, respectively, and the bit line 8 is connected to a plurality of memory cells 1.
0.11 is connected, while the dummy bit! i9 has
A dummy cell 12 is connected. The configuration of each memory cell will be explained below, taking memory cell 10.11 as an example.

The memory cell 10 is composed of an N-type FET 13 for storing information "0", and the N-type FET 13 has an oxide film thickened, for example, so that a channel is formed when a gate voltage is applied. On the other hand, the memory cell 11 is composed of an N-type FET 14 for storing information "1", and the FET 14 has a thick oxide film, for example, so that a channel is not formed even when a gate voltage is applied.

The gates of FET13 and 14 mentioned above are word! 115.1
6, and the word lines 15 and 16 are connected to other word lines (not shown) and a dummy word line 17.
Also, they are respectively connected to a plurality of output terminals of the address decoder 18.

The address decoder 18 decodes the address signal SAD applied from the outside and selects one of the large word lines 15, 16.
. . , the dummy word 117 is always selected. On the other hand, the dummy cell is composed of an N-type FET 19 for generating a reference voltage, and the channel dimensions of the FET 19 are as follows:
FE whose channel conductance is for storing information “0”
It is set to be approximately 1/2 of that of T13.

The aforementioned detection nodes B and C are connected to the output circuit 22 via a pair of data @20.21, and this output circuit 2
2 compares the voltages of detection nodes B and C and outputs the result as an output signal 5out. Next, we will explain the channel dimensions of N-type FET 6.7, so that the channel conductance of FET 6 is smaller than that of FET 7. That is, the channel width of FET 6 is selected to be smaller than that of FET 7 while making the conductivity and channel length of the inversion layer formed in each channel equal. In response to the clock pulse CL, each gate of these FETs 6.7 sequentially controls the control signals ΦP,
(The timing generation circuit 23 that outputs 6A1 and ebA2
is connected to the output terminal for control signal 6A1 and the output terminal for control signal +6A2, respectively, and another output terminal for control signal tbp of this timing generation circuit 23,
The gates of N-type FETs 4.5 are commonly connected.

The operation of the dynamic differential amplifier having such a configuration will be explained below with reference to the timing chart shown in FIG.

First, a case will be described in which an external device, for example, a microprocessor, accesses the memory cell IO in which information "0" is stored. In this case, the semiconductor storage device starts a read cycle in response to an external access request, and first, the timing generation circuit 23 shifts the precharge command signal 6p, which is one of the control signals, from a low level to a high level. (time t1), N-type FET 4.5 is turned on, sensing nodes B and C, bit line 8, and dummy bit line 9. Furthermore, the data lines 20 and 21 are also precharged to approximately the ground potential Vdd (5V). Here, at the common node A, its charge is discharged during the preceding read cycle and it becomes approximately the ground potential VSS, so
As the detection nodes B and C shift to the reference potential Vdd, the N-type FET 2.3 is turned on, and the common node A is also precharged to approximately the reference potential Vdd.

In this way, each node A, B, C and bit line 8
After the dummy bit ta9 and the data line 20.21 are precharged, the precharge command signal 6p goes low (at time t2), and the detection nodes B and C become floating and high. Subsequently, the address signal SAD, which has already been applied from the microprocessor to the address terminal of the semiconductor memory device, is applied to the address decoder 18.
The selection signal S115W is applied to the word line 15 and the dummy word line 17, so these go high (time t3), and the word line 15 and dummy word line 17 go high. When transitioning to level, N-type FETs 13 and 19 are respectively turned on,
Charges on bit line 8 and dummy bit line 9 are discharged. As a result, the voltages at detection nodes B and C begin to gradually decrease (time t4), but as already explained, the voltages at FET1
Since the Chan tree conductance of FET 19 is larger than that of FET 19, the voltage drop rate of the detection node B is larger than the voltage drop rate of the detection node C.

In this way, the voltage difference between detection nodes B and C is set to a predetermined value (approximately 0.
05V), the first activation signal φA1, which is one other than the control signal, shifts from low level to high level, and at time t5), the voltage of the common node A begins to fall.

As already mentioned, the channel width of N-type FET6 is N
*Since it is narrower than that of FET7, the discharge of charge from common node A is small, and therefore the voltage drop rate of common node A is small. Therefore, during this time, as the voltage of common node A drops, N-type FE72.3 gradually transitions to the on state, but since the voltage drop rate of the common node A is small, the voltage drop rate of each sensing node B and C connected to the large bit line stray capacitance and the dummy bit line stray capacitance, respectively. Therefore, even if the stray capacitance of the bit line 8 is larger than that of the dummy bit line due to manufacturing variations, and the source resistance of the N-type FET 3 is smaller than that of the N-type FET 2, as a result, the N-type The charge discharging ability of FET2 is greater than that of N-type FET3,
Despite being small, even if the time constant of bit line 8 becomes thicker than the time constant of dummy bit line 9, the voltage of sensing node C rarely falls by overtaking the voltage of sensing node 1B. In other words, since the N-type FET 3 does not suddenly discharge the charge of the detection node C,
The voltage difference between sensing nodes B and C is amplified while the voltage at sensing node C remains higher than the voltage at sensing node B.
To accurately reflect the storage information of the storage cell 10.

In this way, the voltage difference between sensing nodes B and C is gradually amplified, and when there is no longer any risk of voltage reversal reduction occurring at sensing nodes B and C, the remaining control signal It’s true! As the s2 activation signal 6A2 moves to a high level at time 0), the NffeFET 7 is turned on in response to this, so the charge discharge speed increases dramatically and the voltage difference between the detection nodes B and C is rapidly amplified. Ru. However,
Based on the amplified voltage difference between detection nodes B and C, the output circuit 22 converts the information stored in the memory cell 10 to "0".
It determines this and sends an output signal 5out, which indicates information "0", to the microprocessor.

On the other hand, when the memory cell 11 storing information "1" is accessed, word i! 16 goes to high level, no channel is formed in FET 14, so the voltage at sensing node B becomes higher than the voltage at sensing node C, and after a slight voltage difference is generated, it is amplified, and based on this, information is output. An output signal S out representing "l" is output.

<Problems with the Prior Art> In the conventional dynamic differential amplifier having the above configuration, the bit line 8 and the dummy bit line 9 are directly connected to the detection nodes B and C. Two N-type FETs 6.7, large and small, with different channel widths are used as discharge transistors.
．． 7, the first and second activation signals small AI and φA2 are sequentially applied from the timing generation circuit 22 with a certain time difference between them. Even if there is a difference in the charge discharging ability of the FET 2.3 or a difference in stray capacitance between the bit line and the dummy bit line, the sensing nodes B and C are connected according to the information stored in the memory cell 10.11. It was possible to amplify voltage differences accurately. However, in order to do this, it is necessary to provide a discharge transistor consisting of two N-type FETs, a large one and a small one.
In order to sequentially activate ET6 and 7 with a certain time difference, 2
two activation signals 6A1. Since ΦA2 is required, there is a problem in that not only the configuration of the differential amplifier becomes complicated, but also the configuration of the timing generation circuit z3.

Furthermore, since the bit line 8 and the dummy bit line 9 are directly connected to the detection nodes B and C.

Precharging must be performed accurately so that the bit line 8 and the dummy beat*9 have equal voltages, and if there is a significant difference in channel conductance between the N-types 4 and 5 for precharging, Even if the channel conductance of the FET 13 is set to approximately twice that of the N-type FET 19, the voltage on the bit line 8 may become lower than the voltage on the dummy bit line, and the state of the memory cell 10 may be lower than that of the bit line. There was also a problem that the voltage difference between the voltage of the dummy bit line 8 and the dummy bit line 9 was not reflected correctly.

Such a problem also occurs when there is an imbalance between the stray capacitance of the bit line 8 and that of the dummy bit line 9.

In addition, since the bit & I 8 and the dummy bit line 9 are directly driven by a sliding amplifier, a large load on the sliding amplifier not only causes a decrease in its operating speed, but also reduces access time. , there was also the problem that extra power consumption was required to charge the load.

Means and operation for solving the problems> The present invention has been made in view of the above problems, and the first invention of the present application is as follows:
After precharging the sensing node and the bit line to a positive voltage using a precharging transistor, the bit line is held at a positive voltage based on the binary information stored in the memory cell, or a second positive voltage is applied. As a result, the bit line voltage is applied to one gate of a pair of differential amplification transistors, and the intermediate voltage from the reference voltage source (between the first positive voltage and the second positive voltage) is applied to the gate of one of the pair of differential amplification transistors. By applying a voltage) to the other gate of the pair of differential amplification transistors and grounding the common node in response to an activation signal, the difference in channel conductance of the pair of differential amplification transistors is utilized. generates a voltage difference at a pair of sensing nodes by amplifying the voltage difference between the bit line voltage and the intermediate voltage, and compares the amplified voltages at the sensing nodes in an output circuit to produce an output signal representing the result. The gist of this is to output the following.

Further, a second invention related to the first invention is a discharge transistor, a sensing node, and a pin [l &
After discharging the bit line to the ground voltage, the bit line is held at the ground voltage or at a first positive voltage based on the binary information stored in the memory cell, thereby causing the bit line to discharge to the ground voltage. The voltage on the positive line is applied to one gate of the pair of differential amplification transistors, and the intermediate voltage from the reference voltage source (the intermediate voltage between the ground voltage and the first positive voltage) is applied to the gate of the pair of differential amplification transistors. and connects the common node to a positive voltage source in response to an activation signal to form current paths with different conductances between the common node and the pair of sensing nodes, and utilizes the difference in conductance. to respectively shift the pair of detection nodes to a voltage obtained by amplifying the voltage difference between the voltage of the bit line and the intermediate voltage,
The gist is that the output circuit compares the voltage difference between the pair of detection nodes and outputs an output signal representing the comparison result.

<Embodiment> FIG. 3 is a diagram showing the configuration of an embodiment of the first invention, and in the figure, the same components as those of the conventional example are given only the same reference numerals, and the explanation thereof will be omitted. In FIG. 3, differential amplifier 3
1 is a pair of P-channel field effect transistors (hereinafter referred to as P
It has a precharging transistor composed of P-type FETs 32, 33, 34, and 35 (referred to as P-type FETs), and the gates of these P-type FETs 32 and 35 are connected to a timing generation circuit 36.
is connected to the output terminal for precharge command signal φp, but the gates of other FETs 33 and 34 are connected to the detection node C
, H. N-type FETs 37 and 38 for differential amplification are interposed between the detection nodes B and C and the common node A, and each gate of the FETs 37 and 38 is connected to the bit line 8 and the dummy bit line 9, respectively. There is. P-type FETs 39.40 for precharging are also connected to the bit line 8 and dummy bit line 9, respectively.
0 gates are all connected to the output terminal for the precharge command signal tbp of the timing generation circuit 36. A discharge N-type FET 41 is provided between the common node A and the ground potential Was, and the FE7
The gate of 41 is connected to the small output terminal for the activation command signal φA of the timing generation circuit 36.

The aforementioned dummy bit line 9, N type FET 19 and P type F
ET 40 constitutes a reference voltage source 42 as a whole.

Next, the operation of the embodiment of the first invention will be explained as follows with reference to the timing chart of FIG.

First, when an external device, such as a microprocessor, accesses the memory cell 10 in which information "0" is stored, the semiconductor memory device starts reading in response to an access request from the outside. , timing generation circuit 36 shifts precharge command signal 7bp to low level, turning on FETs 32,35,39,40.

As a result, the detection nodes B and C, the bit line 8, and even the dummy bit line 9 are precharged to approximately the reference voltage Vdd. At this time, since common node A has been discharged to approximately the ground potential Vss during the previous read cycle, FETs 37 and 38 are also gradually turned on as the voltages of common nodes B, C, bit lines 8, and dummy bit lines 9 rise. Therefore, the common node A is also precharged to approximately the reference potential Vdd (time tl), the bit line 8 and the dummy bit line 9
．． Furthermore, when the precharging of each node A, B, and C is completed, the precharge command signal φp shifts to high level again.

Bit line 8, dummy bit line 9. and each node A, B
, C become floating high (time t2). Here, the address signal Sad applied from the microprocessor is decoded by the address signal Da 18, and the selection signal Sv is applied to the word line 15 and the dummy word @17.
, Swd are supplied, the voltages on word line 15 and dummy word line 17 go to high level, and FET 13.19
turns on (time t3).

Then, the bit line 8 is grounded through the FET 13 which is in the on state, and its charge begins to be discharged, but the channel conductance of the FET 19 becomes approximately 1/1 that of the FET 13.
2, the voltage drop rate of the dummy bit line 9 is approximately 1/2 of the voltage drop rate of the bit line 8. Here, when the activation command signal φA shifts to a high level (time t4), the FET 41 is turned on, and as a result, the common node A begins to gradually fall toward the ground potential, and the common node A and the bit line When the voltage difference between FET 8 and dummy bit line 9 exceeds the threshold of FET 37.
7.38 is also turned on one after another. However, FET37.3 is proportional to the voltage difference between bit line 8 and dummy bit line 9.
Since the channel conductance of g is determined, the charge stored at sensing node C is drained faster than the charge stored at sensing node B, and therefore the voltage at sensing node C drops faster than that at sensing node B. do. As a result, the gate voltage of the FET 33 connected to the detection node C exceeds the threshold value earlier than that of the FET 34, so at that point the reference voltage Vdd is applied to the detection node B, and the voltage of the detection node B is increases (time t5),
Therefore, the voltage difference between the sensing nodes B and C increases from this point on, and based on this voltage difference, the output circuit 22 outputs an output signal S ovt representing information "0".

On the other hand, when the word line 16 is selected by the address signal SAD, the voltage on the bit line 8 does not drop and only that on the dummy bit line 9 drops, so that the channel conductance of the FET 37 is higher than that of the FET 38. growing. As a result, the voltage at the sensing node B changes to the voltage at the sensing node C.
The output circuit 22 detects this and outputs an output signal S out representing information "1".

Next, an example of the operation when the memory cell 10 is accessed is shown in the case where the stray capacitance of the bit line 8 is larger than that of the dummy bit line 9, and the source resistance of the FET 38 is smaller than the source resistance of the FET 37. explain.

Due to the difference in source resistance of FETs 37 and 38, when the activation command signal φA goes to a high level, FET 38 turns on before FET 37, and as a result, the voltage at the sensing node C becomes earlier than the voltage at the sensing node B. Even if the voltage at sensing nodes B, C starts to drop, the voltage at sensing nodes B, C is not directly connected to the bit line 8 and dummy bit line 9. Never returned.

Therefore, the gate voltage of FET 37 remains higher than the gate voltage of FET 38, and the difference in these gate voltages is magnified by the difference in channel conductance of FET 13 and FET 19, so that the charge draining capability of FET 37 is Eventually, the voltage at the sensing node C exceeds the voltage at the sensing node B, overtaking that of the FET 38, and rises again. Therefore, the output circuit 22
is the output signal S o that correctly reflects the information of the memory cell 10
It will be output as uT. Furthermore, even if the voltages of the detection nodes B and C are not strictly equal when the charge is completed and the voltage of the detection node C is slightly lower than the voltage of the detection node B, the information in the memory cell 10 is is accurately reflected in the output signal S auT.

The same thing holds true even if there is simply a difference between the stray capacitance value of the bit line 8 and that of the dummy bit, and if these bit lines 8 and dummy bit lines 9 are directly If it is connected to an amplifier and serves as a load for it, if the load at detection node #B is heavier than that at detection node C, it will tend to accelerate the malfunction of the differential amplifier. In the above configuration, since the bit line 8 and the dummy bit line 9 do not serve as a load on the differential amplifier, such malfunctions are avoided.

Next, the configuration of an embodiment of the second invention will be explained based on FIG. 5. In FIG. 5, the same components as in FIG. 3 are given the same reference numerals and their explanations are omitted. In FIG. A P-type FET 62 for current charging is interposed between the two, and the gate of the FE 762 is connected to the activation command FA signal terminal of the timing generation circuit 63. A pair of differential amplification P-type FETs 43 and 44 are connected in parallel between the common node A and the detection nodes B and C, and between the detection nodes B and C and the ground voltage (V as). , discharge transistors each consisting of a pair of N-type FETs 45, 46, 47, and 48 are provided. N type F
The gates of ET45.48 are connected to the discharge command signal small p output terminal of the timing generation circuit 63, and the gates of N-type FET46.47 are connected to the detection nodes C, B.
are cross-connected to.

Memory cells 49, 50... connected to bit line 8
are composed of N-type FETs 51 and 52, respectively, and the FETs 51 are connected to the reference voltage source Vdd when the gate voltage is applied.
and the bit line 8 so that a current path can be formed between the bit line 8 and the bit line 8.
For example, although the oxide film is formed thin,
For example, the oxide layer 52 is formed to have a thick oxide film thickness so that no current path is formed even when the gate voltage is applied. Further, the gates of FETs 51 and 52 are connected to word lines 15 and 16, respectively. On the other hand, the dummy cell 53 connected to the dummy bit line 9 is also composed of an FET 54 that can form a current path between the reference voltage source Vdd and the dummy bit line 9 when a gate voltage is applied. Compared to that, about 1/
The dimensions of each channel are determined to be 2.

Bit line 8 and dummy bit line 9 and ground voltage (V s
s) are connected with N-type FETs for discharge.
55-56 are connected, and these N type FE755-
The gate of 56 is connected to the output terminal for discharge command signal φp. The aforementioned dummy bit line 9FET54
．． 56 constitutes a reference voltage source 57 as a whole.

Next, the operation of the differential amplifier 61 shown in FIG. 5 will be explained with reference to the timing chart of FIG. 6 as follows.

First, when there is an access request to the memory cell 49 that stores information rQJ, in response to the access request from the outside, the discharge command signal ebp changes from a low level to a high level, and the N-type FET45.48.55
．． 56 is turned on (time t1), so that bit I
The charges of i8, dummy bit line 9, and detection nodes B and C are discharged, and if the potential of common node A becomes
When the positive voltage is greater than or equal to the value that ensures the threshold of the FETs 43 and 44, the FETs 43 and 44 are turned on, and the charge stored in the sensing node A is also discharged through these FETs. After the charges on each node A, B, C, bit line 8, and dummy bit line 9 are discharged, the discharge command signal φp again shifts to a low level (time t2), and each FET 45, 48, . Turn off 55.56.

After that, based on the address signal SAD that has already been applied, the address decoder 18 supplies selection signals Sw and Svt to the word line 15 and dummy word line 17, respectively, and turns on the FETs 51 and 54 (at the time t3
), as a result, the reference voltage source Vdd is supplied to the bit line 8 and the dummy bit line 9, so that the bit line 8 and the dummy bit line ()! ! The voltage on the bit line 8 gradually increases, but since the channel conductance of the FET 51 is about twice that of the FE, T 54, the voltage on the bit line 8 increases faster than that on the dummy bit line 9. Here, the activation command When signal 5 transitions from high level to low level and FET 62 is turned on, common node A is connected to reference voltage source Vdd, and the voltage at common node A begins to rise (time t4).

When the voltage at common node A becomes higher than the voltage at bit line 8 and dummy bit line 9 by the threshold voltage of FET 43.44, FET 43.44 turns on and sense node B
, C begins to rise rapidly. As already mentioned, the voltage on the bit line 8 is kept higher than the voltage on the dummy bit line 9 due to the difference in channel conductance between the FET 51 and the FET 54, so that the voltage difference between the source and gate of the FET 44 is equal to the voltage difference between the source and gate of the FET 43. As a result, the channel conductance of FET 44 becomes larger than that of FET 43. Therefore, the voltage at sensing node C will be higher than the voltage at sensing node B. From then on, bit! ! Since the voltage difference between 8 and dummy bit line 9 increases over time, the voltage difference between detection node B
, C increases and the difference between them increases. thus,
When the voltage at the detection node C exceeds the threshold of the FET 46,
Since the FET 46 is turned on and a current path is formed between the detection node B and the ground potential Vss, the voltage of the detection node B decreases (time t5) and finally reaches approximately the ground potential Vss (time ◯). .

Then, when the voltage difference between the detection nodes B and C increases sufficiently, the output circuit 22 determines the information stored in the accessed memory cell 49 as "0" based on the voltage difference between the detection nodes B and C. and an output signal S ou representing the discrimination result
Output T.

On the other hand, when the memory cell 50 is accessed, no current path is formed between the reference voltage source Vdd and the bit line 8, and even if the voltage on the dummy bit line 9 gradually increases, , the voltage of the bit line 8 remains at the ground potential Vss. As a result, FETs 43 and 44 are turned on, but FETs 43 and 44 are turned on.
Since the source-gate voltage difference of FET 44 is larger than the source-gate voltage difference of FET 44, the channel conductance of FET 43 increases, and the voltage at sensing node B becomes higher than the voltage at sensing node C. Therefore, the output circuit 22 determines that the information stored in the memory cell 50 is "1" based on the voltage difference between the detection nodes B and C, and outputs an output signal 5outT representing the determination result.

Further, the drain resistance of FET43 is changed to FET44.
An example of the operation when the memory cell 49 is accessed will be described in the case where the stray capacitance of the bit line 8 is larger than the drain resistance of the dummy bit line 9 and the stray capacitance of the bit line 8 is smaller than that of the dummy bit line 9. In this case, as in the embodiment of the first invention, if F
Even if ET43 is turned on before FET44 and the voltage of sensing node B becomes higher than the voltage of sensing node C, the voltages of sensing nodes B and C will be higher than that of bit line 8 and dummy bit line 9.
Since the bit line 8 voltage is not fed back to the dummy bit line 9, the voltage on the bit line 8 is still kept higher than the voltage on the dummy bit line 9, and the voltage difference therebetween increases. As a result, the channel conductance of the FET 44 eventually becomes larger than that of the FET 43, and the voltage at the sensing node C becomes higher than the voltage at the sensing node B. Therefore, the output circuit 22 outputs the information "0".
Since the output signal S out that represents "" can be output, erroneous determination will not be made. Also, due to the discharge, the detection nodes B and C do not strictly reach the ground voltage, and the detection node C is slightly correct. Even if it is a voltage, the information in the memory cell 49 is accurately reflected in the output signal S for the same reason as mentioned above.
It is reflected in outT.

Effect> As explained below, the first invention and the second invention of the present application each connect a bit line and a reference voltage source to a pair of differential amplification transistors, and connect a pair of sensing nodes to the sensing node. It is connected to an output circuit that compares the voltages of and outputs an output signal representing the result, but there is no connection relationship between the bit line and reference voltage source and the pair of sensing nodes. The conductance of a pair of differential amplification transistors is determined only by the voltage difference between the bit line and the reference voltage source, so that the differential amplification transistors do not operate blindly transiently when an activation command signal is applied, and the discharge transistor There is no need to provide a plurality of them, and only one activation command signal is required, which has the effect of simplifying the structure of the differential amplifier and the structure of the timing generation circuit.

Furthermore, since the bit line and the reference voltage source are each cut off from the sensing node, the increasing voltage difference between the bit line and the reference voltage source can be avoided without precharging or discharging the sensing node to strictly equal voltages. Based on this, the information of the accessed storage element is accurately reflected on the sensing node, so manufacturing errors in the precharge transistor or discharge transistor will not have a decisive effect on the function of the differential amplifier, and the product will be It also has the effect of improving your stride.

In addition, since the bit line and dummy bit line are not directly connected to the differential amplifier, even if there is a difference between the stray capacitance of the bit line and that of the dummy bit line,
This does not interfere with the operation of the differential amplifier, thereby further enhancing the above-mentioned effect of improving yield.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventional differential amplifier, and Figure 2 is a circuit diagram showing a conventional differential amplifier.
Fig. 3 is a circuit diagram showing an embodiment of the first invention of the present application, Fig. 4 is a timing chart of the circuit of Fig. 3, and Fig. 5 is a circuit diagram showing an embodiment of the second invention of the present application. The circuit diagram shown in FIG. 6 is a timing chart of the circuit shown in FIG. 8・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・Bit line 9・・・・・・・・・・・・
・・・・・・・・・・・・・・・・・・・・・ Dummy bit line 1O111,48,50・・・・・・・・・・
・・・・・・Memory cell 22・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・・・・Output circuit 32
-35 , 39.40・・・・・・・・・・・・
Precharge transistor 37.38.43.33・・・・・・・・・・・・・・・
・Differential amplification transistor 41・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・Discharge transistor 42.57・・・・・・・・・・・・・・・・・・・・・
...Reference voltage source 45-48.55.5B...
・・・・・・・・・・・・Discharge transistor 82・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・Transistor A for current charging・・・・・・・・・・・・・・・・・・・・・・・・
......Common nodes B, C...
・・・・・・・・・・・・・・・・・・Detection node Figure 2 Figure 4 ↑ Figure 6

Claims (2)

[Claims] (1) A pair of detection nodes B and C, a common node A, a bit line 8, and a precharging transistor 3 that precharges the detection nodes B and C and the bit line 8 to a positive voltage.
2 to 35, 39, and 40, storage cells that are connected to the bit line 8 and maintain the bit line at a first positive voltage or shift it to a second positive voltage based on the stored binary information. 10, 11, a reference voltage source 42 that generates an intermediate voltage between the first positive voltage and the second positive voltage as a reference voltage, and a current path formed between the sensing node and the common node to connect the bit line. A pair of differential amplification transistors 37, 3 that determine the voltage of each detection node according to the voltage difference between the voltage and the intermediate voltage.
8, and a discharge transistor 41 that grounds a common node and activates a differential amplification transistor in response to an activation command signal, wherein the bit line and the reference voltage source are connected to each other as a pair. are connected to the gates of the differential amplification transistors, and an output circuit 22 is connected to each of the detection nodes, which compares the voltage difference between the detection nodes and outputs an output signal representing the comparison result. Characteristic dynamic differential amplifier. (2) A discharge transistor 45 for discharging the pair of detection nodes B and C, the common node A, the bit line 8, the detection node and the bit line to the ground voltage.
48, 55, 56, and memory cells 49, 5 connected to the bit line 8 and holding the bit line at ground voltage or shifting it to a first positive voltage based on the stored binary information.
0 and the ground voltage or the first positive voltage, and a reference voltage 57 that forms a current path between the sensing node and the common node to generate an intermediate voltage between the bit line voltage and the ground voltage or the first positive voltage. A pair of differential amplification transistors 43 and 44 determine the voltage of each detection node according to the voltage difference between them, and the common node and the bit line are connected to a positive voltage source in response to an activation command signal. In the dynamic differential amplifier, the bit line and the reference voltage source are respectively connected to the gates of the pair of differential amplification transistors, and the respective detection transistors are connected to the gates of the pair of differential amplification transistors. A dynamic differential amplifier characterized in that an output circuit 22 is connected to the nodes to compare voltage differences between the detection nodes and output an output signal representing the comparison result.