JPS61239747A - Digital data communication equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Back of the Invention II] The present invention relates to a digital device of the type used in a loop communication device, and in particular includes a local processor and an 0-cal bus, and includes a host computer in the data communication loop. Concerning building an adapter to connect.

A Token Ring Local Area Network is an inter-ring data communications device.

It has the function of transferring data through multiple stations connected to a unidirectional signal path. Each station includes a host processor with memory and various peripherals;
Functioning as an independent work station. Access to the token ring is controlled by token passing, where free or busy Φ tokens are transferred around the ring from one station to the next. An early token ring example is U.S. Patent No. 13.597.54, issued to Farmer and Newhall and assigned to Bell Telephone Laboratories.
It is shown in No.9. further improved. The so-called Munich Ring was described in the International Telecommunications Conference Report (January 1981)
January.

It originated from IBM's developments reported in Section A, page 2.2.1 to Section A, page 2.2.6).

The standard protocol for these communication methods is IEEE
' has been announced as an 802.5 token ring proposal.

The present invention relates to the construction of an adapter that connects between a host processor and a single wire ring when used in a local area network device. This adapter must operate relatively independently of the host central processing unit (CPU);
Interface processing by the PU functionality is required to be minimal. Since this adapter must be compatible with a variety of different types of host CPUs, a special adapter had to be manufactured for each different type of work station. It is anticipated that entire office buildings or manufacturing facilities will be permanently connected to implement this type of loop communication between computer terminals, word processors, telephones, mass data storage stations, and the like.

Therefore, adapters need to be relatively low-cost, reliable and require little maintenance, small and consume little power, and, first and foremost, are used to interface a variety of disparate devices. It is necessary, of course, to operate at a data transfer rate compatible with the host CPU and the 11IIIA path.

The main object of the present invention is to provide an improved data communication system;
More specifically, an improved communications adapter for connecting a host processor device to a token passing communications loop is provided. Another object of the invention is to have a host system independent processing and ill 1111 ffi;
and to provide an improved communications adapter that operates with a variety of different host systems. It is a further object of the present invention to provide a low cost, low power, reliable and multi-functional communication adapter for Token Ring Area Network systems and the like.

Yet another object of the invention is to provide a local bus structure for interfacing two different processor devices.

Features considered novel features of the invention are set forth in the appended claims. but.

The invention itself may be better understood by reference to the following detailed description taken in conjunction with the accompanying drawings.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS Referring to FIG. 1, a token ring type communication loop is shown. Multiple nodes or stations 10
are connected to each other by a unidirectional signal path 11. A host processor unit 112 is connected to each station 10. Each of these host processor units 12 may be a computer work station having a CPU, keyboard, disk memory, cathode ray tube (CRT) display, and printer. The signals on unidirectional signal path 11 are as follows: As explained in , this token
The ring...propagates unidirectionally as indicated by the arrows, either bit series or byte series, depending on the needs of the area network system. The purpose of this communication loop is to obtain high-speed communication in the processor unit H11.

There is no central station or mask station in the communication loop; instead, the nine communication loops operate on an appositional basis.

The communication loop in Figure 111 is connected to one office building, I! Interconnecting stations 10 in a joint building or university
local area network, unidirectional signal path 1
1 is less than a few kilometers long.

When twisted pair wires are used for this unidirectional signal path 11, a data transfer rate of about 1 to 10 Hb/s is possible, and 100 to 200 stations can be connected to one communication loop.

Granting access to the communication loop of FIG. 1 uses a form of control based on token passing. A unique bit thief called a token is passed from one station to the next. If one station does not have data to send, it passes the token as is to the next station. Other station 10
A station that has data to transmit to a station waits until it receives a token, changes the token from "free" to "busy," and transmits the data to be transmitted. After this transmission, when the sending station receives a message of the data in question on its input,
It determines that the data has circulated through the communication loop ψ and resends a free token.

The communication loop in Figure 1 is IEEE 802.54g! for Token Ring Local Area Networks!
operate in accordance with the standards. This type of device is described in 18M Systems Journal, Volume 22, Issues 1 and 2, 1983.
18M Systems Journal Research and Development, No. 27, No. 5, September 1983, pp. 481-62. The 496th negative is also explained by N, C, and Stroll.

Each station 10 has a unidirectional signal path 11 connected to its human power 13.
It receives data from its output 14h1 and transmits data. This data is sent out on twisted pair wires in differential Manchester code format. This data consists of consecutive 8-bit groups, or 8-bit bytes, as shown in FIGS. 1a and 1b. Free tokens as shown in Figure 1a.

1 bit byte start delimiter - 12 bit byte long physical control field followed by 1 bit byte 1...
Consists of the ending delimiter. The physical control field is
The priority code to obtain the priority of access permission, and 1. It consists of a "token" which becomes 0 when it is empty. Since the start delimiter and end delimiter contain bits that violate code conventions in the Manchester code, the delimiters cannot occur in the address or data fields.

The data frame consists of a start delimiter and a 2-bit byte physical control field, which in this case contains a busy token, as shown in FIG. 1a. The next field is the destination address, which is 6 bytes long. One communication loop requires only one byte for up to 256 stations 10, but protocols for a large number of unique addresses are provided. Following this is a 6-byte source address field, representing the address of the transmitting station. Next is the information field (data), which is a variable length field depending on the number of data bytes to be sent. The average message is perhaps 200 or 300 bytes of ASCII code, but 1000 bytes can be sent within one frame. This data is followed by a 4-bit byte of frame check thief, which includes a CRC code to check for address and data errors. The receiving station performs this frame check thief check. This frame is a thing I
It is completed by the end delimiter of the IIv4 field bit byte.

This physical IIJIlI field consists of a number of bits that are modified by the receiving station as the frame passes through to indicate that the address has been identified, that the frame is occupied, and that an error has been detected in the transmitted data. It's showing a lot.

A transmitting station does not insert a free token into a communication loop until it receives the beginning of a transmitted frame back at its input. The transmitting station transmits a free token as soon as it identifies the starting delimiter-2 physical control field, the destination address, and the source address. Capture the rest of the transmitted frame. Each station 10, except the transmitting station and the receiving station, simply passes the frame through.

The frame will not be occupied. station 10
can perform the following operations on the data stream: That is.

(a) If the destination address does not belong to the station, retransmit without copying the data or fields.

(b) If the destination address is that of the station in question, retransmit and copy the data frame.

(C) The station changes the state of one bit in the received data (eg, the token or object II till 1ml field) before retransmitting.

(d) One station starts transmitting data to another station.

(e) After the message has gone around the communication loop.

Eliminate or eliminate message frames sent by a source station from the nine communication loops before that station. The source station retransmits the free token after passing the lil start delimiter-1 physical control field (containing the busy token), the destination address, and the source address.

Referring to FIG. 2, each station 10.

It has a ring interface 15 that converts the signal at the input 13 to a voltage level for internal processing and reproduces the zero-clock signal φS from the communication loop signal. The ring interface 15 also provides an output signal at the appropriate voltage/(and) current level to the output 14 based on the output signal of 1114'. Serial data input from 1a13' is supplied to protocol processing bag w116. This protocol processing device 16 has the functions (a) to ("
) consists of a single chip integrated circuit. This serial data is converted into parallel data in register 17. When this serial data is to be converted into parallel data in register 17 and when this serial data is to be copied.

The input data bytes are copied to data bus 19 by FIFO buffer 18.

The message processor chip 20 is a local CP
Another single top integrated circuit that includes U21 and local RAM 22 and uses direct memory access (DMA) to transfer input data to local RAM 22 via local address data bus 23 and local control bus 24. Message processor chip 20 also includes a general purpose timer 25 and a bus arbitration device 26, both of which are connected to local address data bus 23 and local control bus 24. message processor
The program related to the 0-cal CPU 21 of the chip 20 is stored in the local ROM 27, and this local R
OM 27 is accessed by address bus 28 and data bus 19, which are extensions of local address/data bus 23, and local ROM 27 is located in protocol processing bag M16.

The input data is then copied to local RAM 22 by the direct memory access channel.

It is copied to the host processor unit 12 by DMA via a system interface chip 30, which is another single chip integrated circuit.

The host processor W112 includes a host CPU31.
, main memory 32, and CRT.

Various peripheral devices 33 connected to a keyboard, disk drive, etc. are provided. A main address/data bus 34 and an ill 10 bus 35 interconnect these elements. The host CPU 31 is.

System interface chip 30 is part number 68
000. and 8086 device IIJIll and data
Either one is acceptable as it conforms to the format.

Host processor unit 12 completes the nine communication loops by first forming a message frame in main memory 32 with a destination address, a self address, and the data bytes to be sent as a message. Other host processor devices! Send a message to 12. This message frame is sent to the local RA via a system interface chip 30 and a local address/data bus 23 via a direct memory access channel (or memory mapped 10).
Copied to M22. This message frame is
The decoder 36 in the protocol processing unit 116 is free
Until you confirm receipt of the token.

It is held in the local RAM 22. After checking this,
A controller within the protocol processing unit 16 receives data from the local RAM 22 via a direct memory access channel to the local address/data bus 23 . A frame transfer is initiated via data bus 19 and FIFO 37, the data from which is serialized by shift Φ register 38 and routed via multiplexer 39 to output line 14'.

1113' is transferred to data bus 19, local address/data bus 23°, or local RAM when not copied at this station.
Instead of being transferred to 22.

It is sent via multiplexer 39 to line 14'.

The local CPLJ microprocessor device can have nine different configurations depending on the internal testing of the present invention as described herein. The microprocessor device in this embodiment is a message processor.
It takes the form of a processor chip 20 and includes a local CPU 21 used in the apparatus shown in FIG.

Message processor chip 20, described in more detail below, is a single-chip MO8/LSI device with a local central processing unit (
CPLJ) 21 and local read/south read static random access memory (RAM) 22. The local CPU 21 and local RAM 22 are
They communicate with each other via a 16-bit parallel, bidirectional and multiplexed local address/data bus 23 and local control bus 24. The device is also equipped with suitable power supply voltage and clock terminals2, e.g. +5VC.
A single supply voltage of C, ground voltage or Vs's can be used and on/off voltages defining local timing can be used.
A crystal oscillator can be connected to the terminals of the device to control the frequency of the chip oscillator. In various single-chip microprocessors or microprocessor devices with on-chip or off-chip memory.

It will also be appreciated that instead of a bidirectional local address/data bus 23, the inventive concept can be applied to microprocessors having separate address and data buses.

In general, local CPL 121 of FIG. 2 functions in a conventional manner. By sending the address to the local ROM 27 via the local address/data bus 23 and address bus 28, the local CPU 21
After fetching the instruction, data bus 1
9 and local address/data bus 23 from addressed locations in local ROM 27. Next, the local CPU 21 executes this instruction. usually.

This requires several machine cycles (defined by the clock or crystal oscillator).

This includes sending an address for an operand stored in local RAM 22 over local address/data bus 23, receiving and receiving that data over local address/data bus 23, R.A.
It involves applying an address to the M0-Cull RAM 22 and subsequently writing the result to the O-Cull RAM 22 via the local address/data bus 23 with successive cycles of data.

In the embodiment described in detail, the 0-cal CPU 21
By applying a 15-pit address (the 16th pit is fixedly connected to O for addressing) to the local address/data bus 231, 64 bytes or 32 Address byte memory directly.

Since each 16-bit word in memory stores an 8-bit byte, local CPU 21 will address 64 bytes.

The functional definition of local control bus 24, status pits and interleaved levels in the 16-bit status register are the same as shown in the table of U.S. Pat. No. 4,402,044, which is incorporated herein by reference. Of course, such identified microprocessors are merely indicative of microprocessors or microcomputers at this point in which the configuration of the present invention may be used.

The local CPU 21 in FIG. 2 is described in US Pat. No. 4.402.
Executes the instruction set described in No. 044, but also defines other instructions to a
12 Specific things mentioned.

It is understood that alternative implementations may also be performed. Most instruction sets are sold by Texas Instruments under part number TMS9900 and are sold by Texas Instruments Inc.
R9900 Family System Design, published in 1974 by (Heuston, Texas, 77001. Postal Code 1443.M. 156404) (Dilil Library Catalog No. 78-058005). The instruction set is the same as that of the microprocessor in use.

Such FIG. 1 is shown here as a cited document.

Bus arbitration device 2 of bus arbitration message processor chip 20
6, the protocol processing device 16. System interface chip 30 or other external DMA
It allows devices to arbitrate control of the local address/data bus 23. After system reset with 5RESET, message processor chip 20
The local CPLJ 21 of the local address/data bus 23 immediately 1I111Il, but the protocol processing unit! 16 and system interface chip 30 are MiI of the local address/data bus 23.
ll can be requested and acquired to perform DMA transfers. Following completion of the DMA cycle or cycles, control of the bus is returned to the message processor chip 20. To ensure maximum utilization of the bandwidth of the local address/data bus 23, requests and grants for future bus cycles are superimposed on the currently ongoing bus cycle.

Local address/data by bus arbitration device N26
Arbitration and control of bus 23 is provided by the message processor
LBREQI- on chip 20.

L8GR1 and LBREQ2. Coordinated by bus request/bus grant handshake with LBGR2- handshake bare. L from protocol processing unit 16
BRQl-Human power is system/'interface/
LBRQ2 from chip 3o - has priority over human power.

The external bus mask (protocol processor 16 or system interface chip 30) requests the local address/data bus 23 by setting LBRQl- or LBRQ2-, and the bus arbitration unit W126 requests the local address/data bus 23 by setting LBRQl- or LBRQ2-.
- or after responding to a bus request by setting LBGR2-.

Address/data, LEN-, from message processor chip 20 at the end of the bus cycle.

Floating the LAl, LR/W- wires.

The master of local address/data bus 23 is determined by bus arbitration device 26 for priority.

(a) External mask on LBRQl-, protocol processing device! 16° (b) External mask on LBRQ2-, System Interface Chip 30° (C) Internal mask from local dimension CPU 21 for microprocessor instructions and data accesses.

Within the system interface chip 30, the memory mapped I10 bus controller
Has priority over the bus controller.

If one of the external bus masks is tsw.

The higher priority bus contention master is the local address/
It is possible to request data bus 23. That is,
Protocol processor 16 may request local address/data bus 23 while system interface chip 30 is in control. This may occur when an input message is being copied from main memory 32 to local RAM 22 by DMA. In this case, the following 9th order occurs.

(a) The bus arbitration device f26 is currently in bus cycle 03.
LBGR2- in .

(b) System interface chip 30 has completed the current cycle (perhaps by a wait state) and has tristated its bus signals and set LB during this period.
RQ2- is withdrawn.

(c) Set LBGR.

(d) The higher priority mask protocol processor 16 withdraws the LBRQI when it completes a DMA task, such as copying an incoming message frame to RAM 22.

Bus arbitration device 126 then sets LBGR2 again.

(e) System interface chip 30 resumes i control of local address/data bus 23 and completes the copying process of the output data frame.

System Interface Chips Referring to FIG. 2, the system interface chip 30 has a main address/data bus 3.
4 (and control bus 35), and the remainder to local address/data bus 23. system·
The input and output bins of interface chip 30 are shown in Table 8. Of course, since some bins go to message processor chip 20, some of the bins are identical to the table.

System interface chip 30 includes two independent controllers. The first is a memory mapped I10 controller with MMIO registers that are connected to the host processor unit 1.
2 manages references to memory mapped registers provided by station 10. Second
is a DMA controller that performs data transfers between main address/data bus 34 and local address/data bus 23. Through these mechanisms, various different logical interface processes between the host processor device 12 and the station 10 are executed by the code being executed in the local CPU 21 (this code is stored in the ROM 27). be able to. Memory mapping I10 and system DMA are terms that refer to the data transfer mechanism as seen from the host processor device 12 side. This is different from the registers in the memory space of the local address/data bus 23 on the local side of the system interface chip 30.

With memory mapping I10, station 10 appears to the host processor @12 as a set of 8 consecutive byte addresses. pit level
Two registers are allocated for status and control information. That is.

Local ROM2 executed by local CPU21
The program code in 7 defines the contents of these bits. In addition, the memory mapped I10 device also maintains address registers in the local data space of the station 10 and the host processor device! 12
can directly access memory bytes in local RAM 22 or local ROM 27 via the local bus. While host processor unit 112 or host CPU 31 is reading or writing to local RAM 22 or the local data space, local CPU 21 is locking out local RAM 22. This method allows command and status task blocks to be written by the host CPLJ 31 and examined synchronously by the local CPU 21.

Memory mapping I10 also provides main address/
programmable interconnected data on data bus 34;
Send a vector.

System interface chip 30 also allows local CPU 21 to initiate direct memory access (DMA) between local RAM 22 and main memory 32 to exchange incoming frame data or commands/status. be able to do so. This DMA
is the local CPL stored in the local ROM 27
121 programs, it is completely Ill ill.

In order to send a message, the system sending host processor unit 112 first generates a data frame in main memory 32 by Ill@ of host CPtJ 31.

Next, the host cpuai connects the system interface
Writes to the MMIO register of the chip 30, and the system interface chip 30 writes to the local CPU 21.
, and indicates the starting address of the data frame via the main address/data bus 34 in the MMIO register.

Next, the local CPU 21 configures the system DMA for system-to-local transfer. This is accomplished by executing the program code in local ROM 27 starting from the vector address being used for interconnection.

Local CPLJ21 sets the following registers.

That is, addressing the data frame with the LDMA ADR containing the address of the main address/data bus 34, and addressing the data frame via the local address/data bus 23 with the SDMA ADH containing the address of the local RAM 22. To be addressed.

Setting the SDMA CT L III 111U bit at the start, obtains the length of the data frame from the SDMA LEN. The system DMA then reads the system data from main memory 32 using the FIFO in system interface chip 30.
Local RAM 2 via interface and chip 3o
Because it transfers the data frame to 2.

Main address/data bus 34 to this FIFO
The transfer of data words to l! by System II tl164 in system interface chip 30
lIl] and synchronized to 5BCLK. On the other hand, the transfer from this FIFO to the local RAM 22 via the local address/data bus 23 is performed by the DMA controller in the system interface chip 30 and is synchronized with the local bus clock LBCLK. This FIFO
When is not full, one cycle on the system control side is as follows. That is, the system side controller requests the main address/data bus 34. host·
Processor unit 12 sends a bus grant to system interface chip 30. A word (or byte) of data is transferred from main memory 32 to a FIFO within system interface chip 30. SDMA
Decrement the LEN register. A cycle like this.

Until the SDMA LEN register becomes O.

Until the 5BERR system bus bin is set,
or until the DMAHALT bit in the S I FCTL register is set. When there is data in the FIFO in the system interface chip 30, one cycle on the local control side is when the local controller inputs the local address/data by the LBQI- signal.
This is a cycle in which a request is made to the bus 23, LBGRI is set by the message processor chip 20, and one word of data is written from this FIFO to the local RAM 22.

1 Yu. Good 1. . Ia. Gloss 1,3□F1. . −
When all frames have been copied to the local RAM 22.

System interface chip 30 is local CP
Interconnect LJ21 again to display that the DMA is completed. Therefore, the local CPU 21 can perform processing such as checking, reformatting, and encrypting the data on the 0-cal RAM 22. When the local CPU 21 completes preparations for transmission, it sets the protocol processing device 16 and writes the local start address and the length of the data frame into two registers of the protocol processing device M16, thereby transmitting the data. Here, the transmission l1lIII is switched to the protocol processing device 16. First, FI FO37 is LBR2-
and LBGR2-protocol processing device 11 using control
6 to local RAM 22 of message processor chip 20. Next, the protocol processing device 16 receives input 13 from the unidirectional signal path 11.
and 13' with a free token input.
riru.

When a free token is input, the protocol processing unit 16 sets a bit to 1 to change it to a busy token.
outputs 14' and 1 from the PIFO 37 via the serial conversion register 38 and the multiplexer 39.
Start sending data to 4. When the F I FO 37 is not full, the protocol processing device 16
Q2- sets a request for the local bus;
Bus arbitration device 2 of message processor chip 20
When LBGR2- is output from 6, one word of data is read from the local RAM 22 to the FIFO 37. The length register is decremented each time a word is transferred, and this transfer continues until the length register is zero.

The data rate of unidirectional signal path 11 is typically about 4 Hb/s or 0.5 Hb/s.

〇-The transfer speed from the local RAM 22 to the FIFO 37 is determined by the local bus link or the local CPtJ21.
The maximum speed determined by the cycle R of approximately 333
For example, 16 bits is 6 Mbytes/S.
This means that the data is transferred every 333 ns.

Therefore, about 0.0 of the cycles of local CP LJ 21.
F I FO during this transfer using 5/6 strikes 1/12
37 can be kept full. Therefore, the local CPU 21 can perform other processing by only occasionally transmitting data transfer to the protocol processing device 16 with the loss of one cycle. Similarly, the host processor unit @12 has a system clock of, for example, 88H2 and has a 2 Mbyte/S data transfer rate over the main address/data bus 34, which is four times the data transfer rate of the unidirectional signal path 11. Gaining data transfer speed. Therefore, the DMA for transferring data frames from the main memory 32 to the local RAM 22 is
Transfer is performed at a higher speed than off-load transfer from M22 to FIFO 37 in protocol processing unit 16. Therefore.

The DMA from the host processor device 12 to the local RAM 22 is transferred to the local RΔ by the protocol processing device 16.
Although the DMA to M22 allows for interleaving, this is not necessary for most transmission processes.

Table A Pin holder
1 LAL Address latch for the local bus. When LAL is active (high), it latches the address appearing on the local address/data bus 23.

AL is a message processor ・Mail inside the chip 20 or from outside. Tsage processors and chips 20 can be generated.

LEN - Data enable for local bus.

LEN is active (low) When , 0-cal ad Data on response/data bus 23 data becomes valid.

'Ll/D--Instructions or data on the Cal bus. When Ll/D- is high, it indicates that an instruction fetch is in progress. When low, a data fetch is in progress. Local ROM2
7 and the local RAM 22.

LR/W-0 - Read or write to the Cull bus. When LR/W- is high, it indicates that a read cycle is being executed. When low, it indicates that a write cycle is in progress.

LNMI - Non-maskable interwired to local bus. When this goes low, local CPLJ 21 performs a non-maskable interlude to vector address/data.

LIRQ O-Cal Bus Interabbed.

Determining the interconnected level Input interact code for including.

LBRDY Local Bus Lady. An external device introduces a wait state by holding LBRDY low. The local CPU 21 continues in the wait state until LBRDY goes low.

LBRQI - Local Bus Requests 1 and 2°L8RQ2
- Request control of the local address/data bus 23 by driving the inputs of the message processor chip 20 active (O-) by the protocol processor 16 and the system interface chip 30, respectively. LBRQI- has priority over LBRQ2-. The bus arbiter 26 of the message processor deep 20 samples both signals at a given clock phase and sets LBRQ1- or LBRQ2- at the ninth phase.

LBGRl-o-cal bus permission 1 and 2゜LBGR2
- in response to bus requests L8RQ1- or LBRQ2-, respectively.

message processor chip By 20 bus arbitration devices 26 message processor chip Activate input from 20 (low) Drive. LBRDY is also set (yes) When asked, ask for it. protocol processing device 16 or message processor chip 20 available next cycle represents something.

Table B System interface size f) F:>91
Cane Bin 11 81/M - System Mode Selection. When this input bin is high in mode ■, it makes the system Φ interface chip 30 compatible with the host CPU 31 of an 8086 or 8088 microprocessor. When low in M mode, 81/M allows system interface chip 30 to operate in a format compatible manner with host CPU 31 of a 68000 microprocessor.

88/16- System 88/16 bus selection. Mouth
-, the 16-pit main
The interface mode is selected by address/data bus 34 (8086). When high, selects the 8-bit main address/data bus 34 (eg, for 8088 devices).

5R8ET System reset. This input bin sets all stations 10 to a known initial state. System interface chip 30 passes this signal to message processor chip 20 via the LRESET- pin.

5O8-System chip selection. It is an input bin from the host CPU 31 to the system interface chip 30 functioning as a chip selection, and is a memory mapping I10 for reading or writing to the system interface chip 30 by the host processor W112 as a chip selection. Run and run.

5R8O system Φ register selection. System5R81mu・
By these three manpower for interface chip 30SR82.

System from host CPU31 For interface chip 30 memory mapped I10 access the word being addressed during the Select the code or byte.

5BHE-System Φ High Enable or /5RNW
Read/non-write. I mode (SIM/M-
-1), this bin is used as a byte high enable signal 5BHE- which is active when 0-. In M mode (SIM/M--0).

Used as the II III signal, this signal indicates a read cycle when high and a write cycle when 0-. System interface chip 30 drives this pin as an output to main address/data bus 34 in DMA. This is the input from host CPU 31 to system interface chip 30 during the memory mapping I10 cycle.

5WR-/ System/Writing strobe or 5L
DS is lower data strobe. In mode (2), this pin is used as an active 0- write strobe.

In M mode, this bottle is active − lower data strobe used. Memory mapping In summer 10, system installation Input to Tough Ace Chip 30.

Also, in DMA, it becomes an output.

5RD-/System/Read/Strobe 5U
DS or upper data strobe. In I mode, this bin is an active low strobe, indicating that a read cycle on the main address/data bus 34 is being performed. In M mode.

The active low strobe is the main The highest address/data bus 34 Transferring data to upper byte represents something. memory map System I10 Input of interface chip 30.

In DMA, it becomes an output.

5RAS System register address /5
AS-Strobe or Memory Address Strobe.

■In mode , this bin is the system register As a data address stop 5CS-.

Latch 5R8O-8R32.

■In mode, 5BHE- It also latches the input. Minimum chip In the system, 5RAS is e.g. To ALE output of host CPU31 Connected. This latch feature Easily disabled and non-multiplexed addresses expansion to support bus and data buses. For Zhang 8086/8088 system Usually required in some cases. this The internal latches for these inputs are As long as 5RAS is high, the tiger remains unparent and this The bottle can be fixed to high. and 5C3-, 5BHE, and and 5R8O to 5R82 outputs. Straw CPLI31 ALE can be applied independently from the can. In 1 mode, this bin is in memory mapping I10. Input and output in DMA The active low address list consists of It's a robe.

5RDY - System Bus Ready or De/SOT
^C--evening forward acknowledgment. ■In mode.

This bottle contains an active low bath ready. Used as an E signal. M mode Now, this bin contains active low data. Used as data transfer acknowledgment signal.

5RDY-signal and 5DTACK – The signal is decoded relative to the bus mask. Notify you that the data transfer is complete. It has the function of 5RDY-Signal /5DTACK signal is internally 5BCLK. this is.

To prevent wait states In state T2, Before the falling edge of 5BCLK must be set to .

5RDY-, 5DTACK-.

System interface chip memory map 110 When selected for otherwise, it is input.

5ALE System address latch enable. At the beginning of each DMA cycle, the output of system interface chip 30 is used as an enable pulse to externally latch the lower 16 bits of the address from the multiplexed address/data lines.

5XAL System extension address latch.

This output is used as an enable pulse to latch (external to system interface chip 30) the 8 address extension bits of the 24-bit system address in the DMA. 5XAL is activated as necessary before and after the first cycle of each block DMA transfer (increasing the DMA address counter causes a carry to be output from the lower 16 bits).

5DIR system data transfer. This output becomes a signal representing the direction in which data is transferred to the external data buffer. For memory mapped I10 writes and DMA reads, 5DDIR is low (input mode), and for MMIO reads and DMAI writes, 5DDIR is the system interface chip 1 and 3o is memory mapped I, as follows:
At 10°, that is, when DMA processing is not executed, 5ODIR becomes high due to a failure.

5DBEN - System Data Bus Enable. This output provides an active low enable signal to the data buffer of the host processor unit 12 outside the system interface chip 30 to switch it out of the high impedance state and begin transmitting data. This output is activated in both memory mapped I10 and DMA.

5OWN - System bus occupied. This output becomes an active 0- during a DMA cycle, indicating to external devices that the system interface chip 30 is in control of the system bus. 5OWN- drives the enable signal of the bus transceiver chip, which drives the address and bus control signals.

5BCLK System bus clock. This is an external clock signal by which the system interface chip 30 synchronizes the bus timing of memory mapping I10 and DMA transfers.

5HRQ/System hold request or bar 5B
RQ - request for space. This output is used to request 1III1 of main address/data bus 34 in preparation for a DMA transfer. In mode 2, an active high hold request is made as defined in the standard 8086/8088 interface. 1 mode results in an active low bus request as defined in the standard 68000 interface.

5HLDA System Hold Acknowledgment or /5
BGR - bus permission. ■In mode.

This bottle is active when you're high.

Standard 8086/8088 interface DMA hold according to face Indicates that the request was acknowledged. Show. In M mode, the target Defined as quasi-68000 interface As expected, when it is low becomes an active bus request. Either 5BCLK even in the mode of Synchronized internally.

5BBSY - System Bus Busy. This input signal samples the value of a 68000 type bus grant acknowledge (BGACK-) signal. Before system interface chip 30 drives main address/data bus 34.

Sample the high of 5BBSY- must be searched. ■Mode and specifies operation in M mode. do.

5BRLS - System Bus Release. This input is driven active low in the DMA to indicate that a higher priority device is requesting the main medium address/data path 34 and system interface chip 30 to release the bus as soon as possible. Display.

system interface Tsubu 30 is not executing DMA. otherwise, this input is ignored.

■ and M synchronized to 5BCLK Specifies the behavior in the mode.

5INTR/ System interface request.

The 5IR-system interface chip 30 activates this output to inform the host processor W112 of the interwoven request. In mode ■, this bottle becomes active high. This pin is active low in M mode.

5IACK - System Interconnected Acknowledgment.

This input is used by the host processor It is driven active low from position 12.

System interface chip In response to an interactive request from step 30 Give an affirmative response. system in Tough Ace Chip 30 is the main ・To address/data bus 34 Derive that interwoven vector. respond to this signal by

No need for intertwined cycles The system bus uses 5TACK- Can be fixed high.

5BERR - Bus error. This input is driven active low during a DMA cycle to indicate to system interface chip 30 that this cycle should be aborted. This corresponds to the 68000 microprocessor's bus error signal. This signal is internally synchronized to 5BCLK. This signal is sampled in 1 and M modes.

5ADH System Address Bus (High 0-7
・byte), which is the 16-bit main address /
This is the most significant byte on data bus 34.

In I mode, the main Address/Data Bus 34 Bins connected to ports 15-8. Mmo (68000 standard) bit numbering is according to the convention) address/data bus 34 Connected to bits 0-7 of

5ADL System address bus (low 0~
7. Byte). This is the least significant byte on the 16-bit main address/data bus 34.

■ In mode, (8086 Standard pit numbering depends on regulations) Main - Address/Data Bus 34 bits O-7.

SPH system parity battle high Transferred via 5ADHO~7 each data byte or address ・Bytes are odd parity bits including.

SPL System parity low.

Transferred via 5ADLO~7 each data byte or address ・Bytes are odd parity bits including.

LBCLKl Local bus clock 1 and LB
CLK2 - Local Bus Clock 2 These signals are the clock for all local bus transfers.

90° to L8CLK1 LBCLK2 with a phase difference follows.

LAL Local address latch enable. At the beginning of each local φ bus cycle, LAL is driven high and then low.

Local address/database 23 to 0-7 and externally Latch. The LAL signal stem interface chip 30 is the local address/data When controlling the data bus 23 is the system Φ interface It becomes the output signal of knob 30, and Otherwise, the system Against Tough Ace Chip 30 1　　　　　9　8.6゜ The following sections are further disclosed in connection with the above description.

(1) In digital data communication equipment.

(a) Signal path.

(11) a plurality of stations each connected to the signal path to receive digital data from the signal path and transmit digital data to the signal path, and each station has a (+)
a main central processing unit, a main memory and a plurality of peripheral input/output devices, and includes an address and data bus means and an lll1l bus, A main processor with a system bus interconnecting it.

(ii) a local central processing unit, a read-only memory and a local read and write memory, and a local multiplexed address and data bus; a communications processor having an interconnecting local-control bus;

(iii) connecting said system command bus to said address and data bus and said local control bus to initiate direct memory accesses to said local read and write memory by said main central processing unit; and initiating direct memory access to the main memory by the local central processing unit.

system interface means for controlling each said direct memory access;

(iV) a 1 m signal path and a data input connected to a receive buffer memory and an output connected to the local read and write memory via the local bus, and with the signal path;

a data output connected to a transmit buffer memory and an input connected to the local read and write memory via the local bus; 1 write memory directly, write received data from said receive buffer memory to local read and write memory, and read transmitted data from said local read and write memory to said transmit and receive bus buffer memory; and reception processing means.

(2) In the digital data communication device according to item 1, the signal path is a diagonal unidirectional path.

A digital data communication device characterized in that each of the stations receives data from an upstream direction of the signal path and transmits data downstream of the signal path.

(3) In the digital data communication device according to item 2, access to the signal path is controlled by a token that is included in the transmitted data and is transferred from station to station on the closed signal path. Digital data communication equipment.

(4) In the digital data communication device according to item 2, data is transmitted in a bit-serial format via the signal path, and the transmission and reception processing means includes serial-to-parallel conversion means and parallel-to-serial conversion means; , wherein the local bus and the system bus each include a parallel bus.

(5) In the digital data communication device according to paragraph 4, one frame of a plurality of data bytes to be transmitted is generated in the main memory by IJIII of the main central processing unit, and the frame is After being transferred by the system interface device via the system bus and the local bus to the local read and write memory upon initiation by the processing unit, upon initiation by the transmitting and receiving control means, the local bus and the transmission buffer
1. A digital data communication device, characterized in that the data is transferred to the transmission processing means by the transmission and reception processing means via a memory.

(6) In the digital data communication device according to item 5, generated in the main memory.

The frame transmitted by the station onto the signal path includes a destination address that identifies one particular station among the plurality of stations, and a source address that identifies station addresses of nine source stations. Digital data communication equipment.

(7) The digital data communications device of claim 6, wherein the local central processing unit executes instructions fetched from the local read-only memory via the local bus, and wherein the main central processing unit executes instructions fetched from the local read-only memory via the local bus; A digital data communications device for executing instructions fetched from said main memory via a system bus.

(8) System central processing unit, system memory,
A data communications adapter for connecting a processor unit having a system l1ill bus and a system address and data bus to a data communication signal path, the data communications adapter comprising: (a) a local central processing unit and a 0-cal memory; and,
a local control bus and a local multiplexed address and data bus connecting the local central processing unit and the local memory, and storing program instructions executed by the local central processing unit in the local memory; a programmable processor device comprising read-only memory for storing message data and read and write memory for temporarily storing message data;

(b) connecting the local multiplexed address and data bus to the system address and data φ bus to provide bidirectional direct memory access between the system memory and the local memory; a system interface device for transferring message data and having an input connected to the system u1-path and the local Mlj bus;

(C) a data communication interface device that connects the local multiplexed address and data bus to the signal path and transfers data between the signal path and the local memory by direct memory access in both directions; Be prepared.

(d) A data communications adapter, wherein said data communications interface device, said system interface device, and said local central processing unit all compete for said local multiplex address and data bus.

(9) In the data communication adapter according to item 8, the system interface device includes a memory mapped input/output channel for accessing the local memory and transferring command information and status information by the system central processing unit. IIJ t of the system interface device, and after initiation of the transfer by the system central processing unit or the local central processing unit.
A data communication adapter comprising a direct memory access channel for transferring data between the system memory and the local memory via IJ.

(10) In the data communication adapter according to item 8, after the data communication interface device starts the transfer or after the local central processing unit starts the transfer,
IIJ III, the signal path and the local
Direct memory transfers data to and from memory.
A data communications adapter comprising an access channel.

(11) In the data communication adapter according to item 8, the programmable processor device controls access to the local multiplexed address and data bus by ilJ.
wherein said data communication interface device has the highest priority for said access;
The system interface device has the next highest priority of the access.

and the local central processing unit has the lowest priority for access.

Cl2) Data communication adapter odor described in item 8!
the system interface device includes a memory mapped input/output channel for accessing the local memory by the system central processing unit to transfer command information and status information; 0 after the transfer is initiated by the local central processor. a direct memory access channel for transferring data between the system memory and local memory under its control; , a direct memory access channel for transferring data between the signal path and the local memory via wIIll of the data communications interface device, and the programmable processor device has a direct memory access channel for transferring data between the signal path and the local memory; Equipped with bus arbitration means to control access.

The data communication interface device has the highest priority for the access, the system interface device has the next highest priority for the access, and the local central processing unit has the lowest priority for the access. A data communication adapter comprising:

(13) In digital data communication equipment.

(a) Signal path.

(b) a plurality of stations each connected to the signal path to receive digital data from the signal path and transmit digital data to the signal path; )
a main central processing unit, a main central processing unit, a main memory and a plurality of peripheral input/output devices, and including address and data bus means and a control bus;
a main processor having a system bus interconnecting the main memory and the plurality of peripheral input/output devices;

(11) a local central processing unit, having a read-only memory and a local read and write memory, and a local multiplexed address and data bus; 20 - a communications processor having a local read-only memory and a local control bus interconnecting the local read and write memories;

(iii) connecting said system bus to said local address and data bus and said local control bus to initiate direct memory accesses to said local read and write memory by said main central processing unit; system interface means for initiating and controlling each direct memory access to said main memory by a central processing unit;

(,iv) having a receiving input means connected to said signal path and a receiving buffer memory, and having a transmitting output connected to said signal path and a transmitting buffer memory, further comprising said signal path at said receiving input; address and data bus means connected to the m local bus means for transferring data between the transmit buffer memory and the receive buffer memory; directly accessing the local read and write memory in response to an initiation by the transmit and receive control means, writing received data from the receive buffer memory to the local read and write memory, and from the local read and write memory; A digital data communication device comprising: transmission and reception processing means having means for reading transmission data to the transmission and reception buffer memory.

(14) In the digital data communication device according to item 13, the signal path is a quiet unidirectional path, and each of the stations receives data from an upstream direction of the communication path, and receives data from a downstream direction of the communication path. A digital data communication device characterized in that it transmits data.

C15) The digital data communication device according to item 14, characterized in that access to the signal path is carried out by a token included in the transmitted data and transferred from station to station on the closed CI path. Digital data communication equipment.

(16) In the digital data communication device according to item 15, data is transmitted via the signal path in a pit-serial format, the receiving input means includes a serial-to-parallel converter, and the transmitting output means includes a parallel-to-serial converter. 1. A digital data communication device comprising: means and said local bus and said system bus each comprising a parallel data bus.

(11) In the digital data communication device according to paragraph 16, one frame of a plurality of data bytes to be transmitted is generated in the main memory based on 1lJIl of the main central processing unit, and the frame is after being transferred by the first access means to the local read and write memory via the system bus and the local etc. bus upon initiation by the main central processing unit, upon initiation by the transmission and reception control means h1; A digital data communication device characterized in that the data is transferred to the transmission output means by the transmission output means via the local bus and the transmission buffer memory.

(18) In the digital data communication device according to item 17, the frame generated in the main memory and sent from the station onto the signal path is selected from a specific one of the plurality of stations.
A digital data communication device f characterized in that it includes a destination address identifying a station and a source address identifying two sources.

(19) In the digital data communication device according to clause 18, the local central processing unit executes instructions fetched from the 0-cal read-only memory via the local bus, and A digital data communication device for executing instructions fetched from the main memory via the system bus.

(20) System central processing unit f, system memory,
A data communications adapter for connecting a processor device having a System 1Jill bus and a system address and data bus to a data communications signal path, the data communications adapter comprising: (a) an 0-cal central processing unit, a local memory;
a local address and data bus connecting the local central processing unit and the local memory, the local memory comprising read-only memory for storing program instructions to be executed by the local central processing unit; and a programmable processor device having read and write memory for temporarily storing message data.

(b) Connecting the local address and data bus No. 16 to the system address and data bus, and transmitting messages by direct memory access in both directions between the system memory and the local memory.
A system interface device that transfers data.

(C) connecting said local address and data bus to said signal path, transferring data from said signal path to said local memory by direct memory access, and providing direct memory access from said local memory to said signal path;・In addition to transferring data by access, address bus,
data bus.

a transmitting and receiving processing device having a receiving buffer memory and a transmitting buffer memory.

(d) The data communications adapter wherein the data communications interface device, the system interface device, and the local central processing unit all compete for control of the local address and data bus.

(21) In the data communication adapter according to item 20, the system interface device has a memory mapped input/output channel that allows the system central processing unit to access the local memory and transfer command information and status information. IIJ of the system interface device, and after initiation of the transfer by the system central processing unit or the local central processing unit.
all allows the system memory and the local
direct memory, which transfers data to and from memory;
A data communication adapter characterized by having an access channel.

(22) In the data communication adapter described in paragraph 21,
1y1 The transmission and reception processing device, after the start of the transfer or after the start of the transfer by the local central processing device,
Data communication characterized in that it comprises a direct memory access channel for transferring data between the signal distribution path and the local memory via the receive buffer memory and the second data bus. adapter.

(23) In the data communication adapter according to item 21, the programmable processor device controls access to the local address, data, and bus.
Ij bus arbitration means, wherein the transmitting and receiving processing unit has the highest priority for the access, the system interface unit has the next highest priority for the access, and the local central processing unit has the lowest priority for said access.

(24) In the data communication adapter according to item 21, the system interface device includes a memory memory that allows the system central processing unit to access the local memory and transfer command information and status information.
A direct memory access memory device comprising a mapped input/output channel and allowing its IIJIB to transfer data between the system memory and local memory after initiation of the transfer by the system central processing VtW1 or the local central processing unit. channel, the transmitting and receiving processing device is configured to control its Ill after initiation of the transfer or after initiation of the transfer by the local central processing device.
'H causes the receive data buffer and the data
a direct memory access channel for transferring data between the signal path and the local memory via a bus; arbitration means, the programmable processor device comprising a bus arbitration device for controlling access to the local bus, and the transmitting and receiving processing device having the highest priority for accessing the system interface device; has the next highest priority for said access, and said local central processing unit has the lowest priority for said access.

[Brief explanation of drawings]

FIG. 1 is an electrical connection diagram showing in block form a one-way communication loop of token passing type that can use a microprocessor device having the features of the present invention, and FIGS. 1a and 1b are the communication loop of FIG. 1. FIG. 2 is an electrical block diagram of one station in the communication loop of FIG. 1 with a microprocessor CPU having features of the present invention. 10...Station. 11... Unidirectional signal path. 12...Host processor device. 15...Ring interface. 16...Butcol processing device. 18...-FIFO buffer. 19...Data bus. 20--Message processor chip. 21...Local CPU. 22...Local RAM. 23...Local address/data bus. 24...Local control bus. 26...Bus arbitration device. 27...Local ROM. 28...Address bus. 31...Host CPU. 32...Main memory. 33... Peripheral device. 37...FIFOo

Claims (1)

Claims: A digital data communication device comprising: (a) a signal path; and (b) each connected to the signal path to receive digital data from the signal path; a plurality of stations each transmitting (i)
a main central processing unit, a main memory and a plurality of peripheral input/output devices, and includes address and data bus means and a control bus; a main processor having an interconnecting system bus; (ii) a local central processing unit, a local central processing unit having a read-only memory and a local read and write memory; and a local multiplexed address and data bus; a communications processor having a local control bus interconnecting the local read-only memory and the local read and write memory; (iii) connecting the system bus to the local address and data bus and the local control bus; initiating direct memory accesses to the local read and write memory by the main central processing unit; and initiating direct memory accesses to the main memory by the local central processing unit and system interface means for controlling memory access; (iv) data connected to said signal path and an output connected to said local read and write memory via a receive buffer memory and said local bus; a data output connected to the signal path and an input connected to the local read and write memory via the transmit buffer memory and the local bus; directly accessing the local read and write memory in response to an initiation by means, writing received data from the receive buffer memory to the local read and write memory, and from the local read and write memory to the transmit and receive bus buffer. - A digital data communication device characterized by comprising transmission and reception processing means for reading transmission data to a memory.