JPS61234428A - Data shift circuit - Google Patents

Abstract

PURPOSE:To execute various shift operations in a prescribed processing time independently of the shift amount by selecting and generating data to be buried to an idle bit from the result of operation in response to the shift operation mode and direction by a selector group. CONSTITUTION:Data except the most significant bit 2 of n-bit data 1 to be shifted, or a bit 2 of the data 1, or an immediate 5 is selected by an (n-1)-bit selector group 3. Data except the least significant bit of the data 1 or the immediate 5 is selected and outputted by an (n-1)-bit selector group 4. Data of continuous (2n-2)-bit being an output of the selector group 4 is inputted to a level shifter 6 in the least significant bit of the output of the selector group 3. The shifter 6 selects and outputs n-bit data according to a control signal 22 from a decoder 21 inputting the shift amount command signal 18 and the shift direction signal 8, and the most significant bit of the shifter 6 or the bit 2 of the data 1 is selected and outputted by a selector 7. A control signal to the selectors 3,4,7 is outputted from the control circuit 12 inputting the signal 8 and the shift mode command signals 9-11.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data shift circuit capable of shifting a plurality of bits of digital data by arbitrary bits in both left and right directions.

BACKGROUND ART Conventionally, in order to shift or rotate digital data, a shift register method has been adopted in which flip-flops are connected in series for the number of bits of the data to be shifted, and one bit is shifted or rotated for each shift pulse. (For example, "New Edition Information Processing Handbook" edited by Information Processing Society of Japan, March 30, 1981, Ohmsha, p. 76)
3, etc.) In order to enable shifting or rotation in both the left and right directions, either a selector is provided for each flip-flop corresponding to each bit, or a shift register is provided for each of the left and right directions. A method such as selecting one output is adopted.

Problems to be Solved by the Invention However, with the above method, when data is shifted or rotated by multiple bits, a processing time proportional to the shift amount is required, and when the shift amount is large, the processing time is It has the disadvantage of being long. Furthermore, shifting or rotating in both left and right directions requires complicated and redundant hardware, which is disadvantageous to circuit integration.

In view of the above, an object of the present invention is to provide a data shift circuit that can perform various shift operations in a fixed processing time independent of the shift amount, and that can perform shift operations in both left and right directions without hardware redundancy. shall be.

Means for Solving the Problems In order to solve the above problems, the present invention selects data excluding the most significant bit of the given shift data, the most significant bit data of the shifted data, or the immediate value "o". A first selector group of (n-1) bits for output, and a second selector group of (n-1) bits for selectively outputting the shifted data excluding the least significant bit or the immediate value "0". , a decoder that generates a control signal for a barrel shift (described later) according to a shift amount instruction signal and a shift direction instruction signal, and a control signal that outputs consecutive n bits of (2n-2) bits of input data from the decoder. a barrel shifter for selectively outputting the most significant bit data of the output of the barrel shifter and the most significant bit data of the shifted data; and a group of selectors according to the shift direction instruction signal and the shift operation mode instruction signal. This is a data shift circuit equipped with a control circuit for generating a selection control signal.

According to the above-described configuration, the present invention selectively generates data to be embedded in empty bits resulting from a shift operation using the first and second selector groups according to the mode and shift direction of the shift operation. The mitator and shifted data are input to the barrel shifter, and consecutive n bits are selected and output from the bit position according to the specified shift amount, and the third selector corrects the most significant bit data of the barrel shifter output data. The final shift operation result by adding the direction and mode of the shift operation.

It is generated in a constant processing time regardless of the amount of shift.

Embodiment FIG. 1 is a block diagram showing an embodiment of the data shift circuit of the present invention.

1 is input data of length n bits to be subjected to shift operation, 3 is a control signal to select one data from shifted data 1 excluding the most significant bit, shifted data most significant bit data 2, or immediate data 10#5 a selector group consisting of (n-1) selectors that output according to 16;
4 is a selector group consisting of (n-1) selectors that output shifted data 1 excluding the least significant bit or immediate data "0" 6 according to the selection control signal 16; 6 is the highest output of the output 19 of selector group 3; A barrel shifter 21 that selects and outputs data of n consecutive pits from bit positions according to a barrel shifter control signal 22 from (2n-2) bit data connected to the output 20 of the selector group 4 on the lower bit side.
7 is a decoder that generates the barrel shifter control signal 22 from the shift direction control signal 8 and the shift amount instruction signal 18; 7 is a selector that outputs the barrel shifter output most significant bit data 13 or the shifted data most significant bit data 2 in accordance with the selection control signal 17; 14 is the final shift operation result,
12 is a selection control signal 15, 16.17 according to the shift direction instruction signal 8 and the shift mode instruction signal 9, 10.11.
This is a control circuit that generates It is assumed that the shift direction instruction signal indicates a rightward shift when the logic is "1", and a leftward shift when the logic is "01". Shift mode instruction signal 9, 10°1
1 indicates a logical shift operation, an arithmetic shift operation, and a two-round shift operation when the logic is ``11'', and it is assumed that two or more shift mode instruction signals will not become logic ``1'' at the same time.

The operation of the data shift circuit of this embodiment configured as described above will be explained below.

First, three types of shift operations performed by the data shift circuit of the present invention will be explained.

A logical shift operation shifts input data to the right or left by the specified shift amount, discards the bits that overflow from the least significant bit (in the case of a right shift) or the most significant bit (in the case of a left shift), and creates a new k ao1 in the open part
is an operation in which is embedded.

Arithmetic shift operation considers the most significant bit as the sign bit and fixes it in the shift, shifts the input data excluding the most significant bit to the right or left by the specified shift amount, and shifts the least significant bit (in the case of a right shift) or The bits that overflow from the bit next to the most significant bit (in the case of left shift) are discarded, and in the case of right shift, the newly vacant part is filled with the same data as the sign bit, and in the case of left shift, it is @0. ” is an operation that is embedded.

A rotational shift operation shifts the input data by the specified shift amount to the right or left, and the bits that overflow from the least significant bit (in the case of a right shift) or the most significant bit (in the case of a left shift) are placed in the newly vacant part. The operations are embedded in the order of overflow.

The n-bit shifted data is A'' (a□, a
1,...

-n, ) (however, the smaller the subscript, the higher the bit), and the shift amount is m (1<:m<, n-1), the above shift operation result A' is expressed as follows. .

Right logical shift operation A'=(0, 0, ., O, ao, al, ., anm-
1) Left logical shift operation A'=(a-, a!!&+1.-・-, an, ,O,
-, O, O) Right arithmetic shift operation ""("Oj"OP""#"Op"OP
"1m"" e "n-m-1) left arithmetic shift operation" = ("Oe"m+1 '"m+2'"""n
110""") Right rotation shift operation ""("n-ms"nm-1-1"・'
#"n-1"O'a1 p ""-n-m-1) Left rotation shift operation ""("m'"m+1#"°9"n-1t
"Qt"1#""e"m-1) Generalizing the above shift operation, the right shift operation inserts the data (long The second
The figure shows the case of right logical shift operation. 1o1 is embedded data, and in this example, all bits @o'' are 01
02 indicates the data to be shifted, and 103 indicates the shift operation result. Similarly, in the case of a right arithmetic shift operation, the embedded data is data in which all bits have a value equal to the most significant bit (i.e., the sign bit) of the shifted data, and in the case of a right rotation shift operation, the embedded data is data that is the shifted data itself. It is.

On the other hand, the left shift operation is performed by concatenating data (length n bits) to be embedded in the empty part for the shift to the least significant bit side of the data to be shifted A. Equivalent to selecting bits of data. FIG. 3 shows the case of counterclockwise rotation shift calculation.

201 is shifted data, and 202 is embedded data, which in this example is equal to the shifted data. 2o3 indicates the shift operation result. Similarly, the embedded data in the case of a left logical shift operation is all bits @0'', and the embedded data in the case of a left arithmetic shift operation is also all bits ``oj''.

Therefore, it can be seen that each of the above shift operations can be performed using a barrel shifter having the function of selecting and outputting n consecutive bits from a designated bit position from data having a length of 2n bits. FIG. 4 shows an example of a well-known barrel shifter using MOSFETs. The example in Figure 4 is 8
This is a barrel shifter that selects the output of 4 pits from the input data of the pits. 3o1 is input data, 302 is output data, and 303 is a control signal. Two or more control signals 303 do not become 1" at the same time. For example, the control signal s
When 2 becomes 1'', the output data 302 is 02.C
It becomes equal to 3+ C4, Cs.

In the embodiment of the present invention, the shift amount m is set to 1<;:m<;: considering that a shift operation with a shift amount of 0 or a shift operation with a shift amount of n or more has no meaning for n-bit data.
limited to the range n-1. Therefore, of the 2n-bit data obtained by concatenating the shifted data and the embedded data, the most significant bit of the data concatenated on the left side and the least significant bit of the data concatenated on the right side are not selected. Therefore, the input data length of the barrel shifter only needs to be (2n-2) bits.

Next, the operation of the embodiment of the present invention will be described below with reference to FIG.

Shifted data 1 is input to selector group 3 and selector group 4. In selector group 3, (2n
-2) The left side (n-1) bits of the input data are selected. As described above, in the case of a right shift operation, the embedded data is selected, and in the case of a left shift operation, the shifted data is selected. The individual selectors constituting selector group 3 are SAI (i=1, 2, +++, n
1), shift data 1 as ai(L=0,1-
, n -1), the relationship between the shift direction, shift operation mode, and data selected in SAi is as shown in FIG. The shift direction instruction signal 8 is expressed as RI,
When RI is logic "11", it indicates a right shift, and when it is logic "0", it indicates a left shift.
．． 10.11 each 1. Let OG, ARI, and ROT represent a logical shift operation, an arithmetic shift operation, and a rotation shift operation when logic @I J+, respectively. At this time, the output of SA1 can be expressed by the following logical formula.

RI, Lα2+10+RI 5ARI *aO+RI
5fLOT*a, 1-RI aa.

・・・・・・(1) An example of a selector that implements equation (1) is shown in FIG. 6a.

401 is the shifted data, 402 is the immediate value @OII.

403 is the most significant bit data of the data to be shifted, 404 is a selection control signal, and 405 is a selection output, which correspond to 1.5, 2, 15, and 19 in FIG. 1, respectively.

The example of FIG. 6a may be simplified as shown in FIG. It goes without saying that equation (1) can also be realized using other logic elements such as tri-state gates.

・Similarly, in selector group 4, (2n-
2) The right (n-1) bits of the bit input data are selected.0 As mentioned above, in the case of a right shift operation, the shifted data is selected, and in the case of a left shift operation, the embedded data is selected. To be elected. The individual selectors constituting the selector group 4 are expressed as 5B1 (1==o t 1 , ”・, n
2), the relationship between the shift direction, shift operation mode, and data selected in SB is as shown in FIG. Similarly to the above, the output of SB can be expressed by the following logical formula.

・・・・・・(2) An example of a selector that implements equation (2) is shown in FIG. 8a.

501 is the data to be shifted, and 502 is the immediate value lIO.

503 is a selection control signal, and 504 is a selection output, which correspond to 1.5 and 16.20 in FIG. 1, respectively. The example of FIG. 8a may be simplified as shown in FIG.

Output 19 selected by selector group 3 and selector group 4
, 20 are input to the barrel shifter 6 as (2n-2) bit data connected to each other, with the selector group output 19 on the left side and the selector group output 2o on the right side. The barrel shifter 6 is configured as shown in the example shown in FIG. 4, and has an input data length of (2n-2) bits, an output data length of n bits,
The number of control signals is (n-1). The input data is ci(i
= 1゜..., 2n-2), output data as 'J (j=1
T...

n), and the control signal is 5i (t=1..., n-1), when 8i is logic "1", n-bit data starting from C1 ('i'i+110' P 'i+n -1
) is selectively output from bl to bn. A control signal 22 for the barrel shifter 6 is generated in the decoder 21 according to the shift direction instruction signal 8 and the shift amount instruction signal 18. FIG. 9 shows the relationship between the shift direction, the shift amount, and the control signal that becomes logic "11" at that time.

Outputs n bits selected by barrel shifter 6.

is equal to the final shift operation result 14 except in the case of left arithmetic shift operations. However, in the case of left arithmetic shift operation, the most significant bit data b1 of the output of the barrel shifter 6 is the most significant bit data (i.e., sign bit) of the shifted data.
Not equal to 2. Therefore, the selector 7 performs correction. The output of the selector 7 can be expressed by the following logical formula.

FIG. 10 shows an example of a selector that implements equation (3).

601 is the most significant bit data of the data to be shifted, 602 is the most significant bit data output from the barrel shifter, and 603 is a selection control signal, which corresponds to 17 in FIG. 604 is a selection output, and the sum of this output and the output of the barrel shifter 6 excluding the most significant bit (n-1) bits becomes the final shift operation result 14.

The control circuit 12 is a circuit that generates selection control signals for each selector group. FIG. 11 shows an example of the control circuit 12 when the selector group 3 is the example shown in FIG. 6, the selector group 4 is the example shown in FIG. 8, and the selector 7 is the example shown in FIG. 10. 0701 is a shift direction instruction signal, and 702 is a shift mode signal. 703.70
4.

705 is a selection control signal, which corresponds to 16°17.1 in FIG.
Corresponds to 6.

Effects of the Invention As described above, according to the present invention, logical shift operations in both left and right directions of digital data, arithmetic shift operations, and one-rotation shift operations can be executed in the same processing time regardless of the amount of shift.
Moreover, it is particularly effective when the amount of shift is large compared to a conventional shift register type data shift circuit. In addition, the circuits in the selector section and barrel shifter section are regular and LSI
It is advantageous for

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data shift circuit in an embodiment of the present invention, FIGS. 2 and 3 are explanatory diagrams showing an example of a shift method used in the present invention, and FIG. 4 is a component of the present invention. A circuit diagram showing an example of a barrel shifter, FIGS. 6 and 7 are relational diagrams showing logical relationships by selectors that are constituent elements of the present invention, and FIGS. 6 and 8 are shown in FIGS. 5 and 7, respectively. FIG. 9 is a circuit diagram showing the selector, FIG. 9 is a relational diagram showing the logical relationship by the decoder which is a component of the present invention, FIG. 10 is a circuit diagram showing the selector shown in FIG. 9, and FIG. 11 is a diagram showing each of the above selectors. FIG. 2 is a circuit diagram illustrating an example of a control circuit for controlling. 1...Data to be shifted, 3, 4...Selector group, 6...Barrel shifter, 7...
・Selector, 8, 9 to 11.18...Various signals indicating the type of shift operation, 12...Selector control circuit, 14...Shift operation result, 21.
·····decoder. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 5
Figure 7 Figure 81! ! (a) Figure 9, Figure 10, Figure 11'

Claims (1)

[Claims] a first selector group of (n-1) bits that selectively outputs data excluding the most significant bit of the given n-bit shifted data, the most significant bit data of the shifted data, or an immediate value "O"; a second selector group of (n-1) bits that selects and outputs data excluding the least significant bit of the shifted data or an immediate value "O", and generates a control signal in accordance with a shift amount instruction signal and a shift direction instruction signal. A decoder and the output of the second selector group were connected to the least significant bit side of the output of the first selector group (2n
-2) a barrel shifter that takes bit data as input data and selects and outputs continuous n-bit data from the input data according to a control signal generated by the decoder; and the most significant bit data of the output of the barrel shifter, or the shifted target data. A third selector that selectively outputs the most significant bit data of data, and control that generates a selection control signal to be supplied to the first, second, and third selector groups in accordance with the shift direction instruction signal and shift operation mode instruction signal. A data shift circuit characterized by comprising a circuit.