JPS61231746A - Integrated electron element for controlling inducing load and use thereof - Google Patents

Integrated electron element for controlling inducing load and use thereof

Info

Publication number
JPS61231746A
JPS61231746A JP61075374A JP7537486A JPS61231746A JP S61231746 A JPS61231746 A JP S61231746A JP 61075374 A JP61075374 A JP 61075374A JP 7537486 A JP7537486 A JP 7537486A JP S61231746 A JPS61231746 A JP S61231746A
Authority
JP
Japan
Prior art keywords
layer
collector
type
controlling
buried layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61075374A
Other languages
Japanese (ja)
Inventor
ピエトロ・エツラテイーコ
ピエトロ・メンニテイ
フアビーオ・マルキーオ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Microelettronica SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Microelettronica SpA filed Critical SGS Microelettronica SpA
Publication of JPS61231746A publication Critical patent/JPS61231746A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0744Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
    • H01L27/075Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
    • H01L27/0755Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
    • H01L27/0761Vertical bipolar transistor in combination with diodes only

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Electronic Switches (AREA)
  • Bipolar Transistors (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 この発明は誘導性負荷を制御するための集積電子素子に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION This invention relates to integrated electronic devices for controlling inductive loads.

公知のように、たとえば継電器のような誘導性負荷を制
御するためにはトラジスタのような電力要素を用いるこ
とが常套手段であり、これは負荷を内部制御信号に基づ
いた最適状態にする効果がある。通常、そのような素子
は負荷の信頼できる切換えを確実にするように、制御電
力要素の迅速なターンオフに続く負荷からの電流需要を
満たすことができるリサイクル要素を必要とする。
As is known, it is common practice to use power elements such as transistors to control inductive loads such as relays, which have the effect of bringing the load into an optimal state based on internal control signals. be. Typically, such devices require a recycling element that can meet the current demand from the load following rapid turn-off of the control power element to ensure reliable switching of the load.

リサイクル要素を提供するために、制御素子を切換えて
電流のリサイクルを可能にするために、適切に接続され
たディスクリートな外部要素を用いることが現在の慣例
である。
To provide a recycling element, it is current practice to use discrete external elements suitably connected to switch the control element and enable recycling of the current.

しかしながら、費用および一般的な便宜上の理由からリ
サイクル要素が素子自身に集積される制御素子の必要性
が感じられる。
However, for reasons of cost and general convenience, a need is felt for a control element in which the recycling elements are integrated into the element itself.

ゆえに、この発明の課業はオフにスイッチされている本
来の制御電力要素に迅速に作用がもたらされるように、
適合された内部リサイクル要素を有する、誘導性負荷を
制御するための集積電子素子を提供することである。
Therefore, it is the task of the present invention to ensure that the actual control power elements that have been switched off are quickly brought into action.
It is an object of the present invention to provide an integrated electronic device for controlling inductive loads with adapted internal recycling elements.

この発明の特別な目的は大量生産技術によっても充分に
一貫性のある特性を有し、その再生産性を確実にする電
子集積素子を提供することである。
A particular object of the invention is to provide an electronic integrated component which has sufficiently consistent properties even with mass production techniques to ensure its reproducibility.

この発明の別の目的は、動作に信頼性があり、特に高周
波数で負荷特性にも対応して動作できる集積電子素子を
提供することである。
Another object of the invention is to provide an integrated electronic component that is reliable in operation and can operate with load characteristics, especially at high frequencies.

この発明のさらに他の目的は、減じられた集積面積を必
要とする集積電子素子を提供することである。
Yet another object of the invention is to provide an integrated electronic device that requires reduced integration area.

この発明の重大な目的は、従来の集積技術を用いて製造
でき、したがって適度に安い工程および生産品仕上げ費
用で済む集積電子素子を提供することである。
An important object of this invention is to provide an integrated electronic device that can be manufactured using conventional integration techniques and thus requires reasonably low processing and product finishing costs.

上記の狙いおよびこれより先明らかとなるその他の目的
は、少なくとも1つの第1導電型または極性型のサブス
トレートと、前記サブストレートに隣接し、それと接合
を形成してダイオードを規定する第2極性型の埋設層と
、前記埋設層に隣接しそれと接合を形成してリサイクル
ツェナーダイオードを規定する実質的に前記第1の極性
型のさらに他の層と、実質的に前記第2の極性型のエピ
タキシャル層と、前記その他の層と前記エピタキシャル
層とともに絶縁コレクタ垂直トランジスタを規定する前
記第1の極性型の負荷のゾーンとを含む、多層構造を含
むことを特徴とし、かつ実質的に前記第1の極性型で前
記さらに他の層と接触した部分を有し、素子の他の部分
に電気的に接続していない出力電極が設けられている領
域があることを特徴とする、誘導性負荷を制御するため
の集積電子素子によって達成される。この発明はその基
本的な局面に従えば、絶縁コレクタの付いた垂直トラン
ジスタを有する集積構造が適切に利用され、誘導性負荷
を制御するために必要なリサイクル要素を構成する電力
要素を形成するという認識に存する。実際、そのような
集積構造は埋設層とコレクタ層の間にツェナーダイオー
ドを形成する接合を含み、その特性は素子を製造する際
に用いられる技術のために再生の可能性が高く、かつツ
ェナーが誘導性負荷のためのリサイクル要素としての動
作に特に適している。しかしながら、先行技術の絶縁コ
レクタ垂直トランジスタではそのようなツェナーダイオ
ードは認められず、かつまた不所望であり、そのため構
造は埋設層から素子の外部表面にまで延在しているゾー
ンで製作され、トランジスタのコレクタ層の延長部を形
成するさらに他のゾーンに電気的に接続された。このよ
うにして、ツェナーは短絡され利用され得なかった。
The aim of the above and other objects which will become apparent hereinafter is to provide at least one substrate of a first conductivity type or polarity type and a second polarity adjacent to said substrate and forming a junction therewith to define a diode. a buried layer of the mold; a further layer substantially of the first polarity type adjacent to and forming a junction with the buried layer to define a recycled Zener diode; and a further layer substantially of the second polarity type. characterized in that it comprises a multilayer structure comprising an epitaxial layer and a zone of load of said first polarity type which together with said other layer and said epitaxial layer defines an insulated collector vertical transistor; An inductive load having a polarity type and having a part in contact with the other layer and having an area provided with an output electrode not electrically connected to other parts of the element. This is accomplished by integrated electronics for control. According to its basic aspects, the invention provides that an integrated structure having vertical transistors with insulated collectors is suitably utilized to form a power element that constitutes the recycle element necessary to control inductive loads. It consists in recognition. In fact, such integrated structures contain a junction forming a Zener diode between the buried layer and the collector layer, the properties of which are highly reproducible due to the technology used in manufacturing the device, and the Zener Particularly suitable for operation as a recycling element for inductive loads. However, in prior art isolated collector vertical transistors such Zener diodes are not allowed and are also undesirable, so the structure is fabricated with a zone extending from the buried layer to the external surface of the device and the transistor electrically connected to yet another zone forming an extension of the collector layer. In this way, the Zener was shorted out and could not be utilized.

その代わりに、この発明に従えば埋設層からそれの延在
部として素子の外部表面にまで延在するゾーンは設けら
れない。なぜなら、ツェナーカソードがアノードの電位
に追随することをもはや強制されないように、ツェナー
アノードをも形成しているコレクタ層に接続された領域
をツェナーカソードの電位に電気的に接続することなく
負荷に接続するためにはそのような短絡を避けることが
本質的になるからである。
Instead, according to the invention there is no zone extending from the buried layer as an extension thereof to the external surface of the element. Because the area connected to the collector layer, which also forms the Zener anode, is connected to the load without electrically connecting it to the potential of the Zener cathode, so that the Zener cathode is no longer forced to follow the potential of the anode. This is because in order to do so, it is essential to avoid such short circuits.

こうしてトランジスタをオフにスイッチすると、ツェナ
ーにかかる電圧はツェナーの破壊電圧に降下することが
でき、それゆえこれはリサイクル電流が接地から誘導性
負荷まで流れることを可能にする。
Thus, switching off the transistor allows the voltage across the zener to drop to the breakdown voltage of the zener, thus allowing recycle current to flow from ground to the inductive load.

この発明のさらに他の特徴および利点は添付の例示的か
つ非限定的な図面に関連して、以下のこれに限られるわ
けではないがそれの好ましい実施例の説明から、よりは
っきりと明らかになるであろう。
Further features and advantages of the invention will become more clearly apparent from the following description of preferred, but not exclusive, embodiments thereof, taken in conjunction with the accompanying illustrative and non-limiting drawings. Will.

第1図を参照すると、この発明に従った素子を形成する
いくつかの層が見られる。これは既に説明されたように
、実質的にここではPNP型の絶縁コレクタ垂直トラン
ジスタから構成され、そしてp型の極性のサブストレー
ト1、層1の上に載っているn型の埋設層2、順に埋設
層2の上に載るp型のコレクタ層3、およびこの発明の
素子を作るさらに他のゾーンがそこで形成されるn型の
極性のエピタキシャル層4を含む。特に図においては、
ここではCで示されるトランジスタのベース電極に接続
するためのn+型の濃密度の領域5と、トランジスタの
エミッタを形成するp++層6、これは第2図では電力
源電圧に接続されて示されている、p+型の極性を持っ
た層7と8(シングル領域の一部であるかもしれないが
、いかなる場合も電気的に一緒に接続される)、および
p1型の絶縁極性を持った領域10’ と10’が見ら
れる。特に、電気的にコレクタ層3に接続される領域8
は素子の外部表面にまで延在し、そこでコレクタ電極A
に接続されるか、一方埋設層2を素子の外部表面に接続
するための領域は設けられておらず、これはツェナーア
ノードとカソードが異なる電位に至ることを可能にする
必要があるからである。さらにその上、p型のサブスト
レート1とn型の埋設層2の間に、実際にダイオードを
形成するさらに他の接合がある。
Referring to FIG. 1, several layers forming a device according to the invention can be seen. As already explained, this essentially consists of an insulated collector vertical transistor, here of the PNP type, and consists of a substrate 1 of p-type polarity, a buried layer 2 of n-type overlying layer 1; It includes a collector layer 3 of p-type which in turn overlies the buried layer 2 and an epitaxial layer 4 of n-type polarity in which further zones making up the device of the invention are formed. Especially in the diagram,
A dense region 5 of the n+ type for connection to the base electrode of the transistor, here designated C, and a p++ layer 6 forming the emitter of the transistor, which is shown connected to the power supply voltage in FIG. layers 7 and 8 (which may be part of a single region, but are in any case electrically connected together) with a p+ polarity, and a region with an insulating polarity of the p1 type. 10' and 10' can be seen. In particular, the region 8 electrically connected to the collector layer 3
extends to the external surface of the device, where the collector electrode A
, while no area is provided for connecting the buried layer 2 to the external surface of the device, since this is necessary to allow the Zener anode and cathode to reach different potentials. . Furthermore, there is a further junction between the p-type substrate 1 and the n-type buried layer 2, which actually forms a diode.

埋設層2およびコレクタ層3は両方とも周知の技術に従
ってイオン注入によって形成される。これは素子を作る
種々のチップに対して充分に一貫性のある条件を確実に
する良好な制御可能および再生可能な電気的特性を与え
る。
Both buried layer 2 and collector layer 3 are formed by ion implantation according to known techniques. This provides good controllable and reproducible electrical properties ensuring sufficiently consistent conditions for the various chips making up the device.

第1図に示される構造の等価回路が第2図で示される。An equivalent circuit of the structure shown in FIG. 1 is shown in FIG.

その図では、第1図の層3.4および6からなるトラン
ジスタ20が見られ、そこではトランジスタ20のコレ
クタがコレクタと埋設層および埋設層とサブストレート
間の接合上に形成するダイオード21と22に接続され
る。見るとわかるように、ツェナーのアノードとカソー
ドはその代わりに先行技術によって設けられていたよう
な回路接続ではなく、電極Aはそれを制御するために誘
導性負荷23に接続される。
In that figure, a transistor 20 is seen, consisting of layers 3.4 and 6 of FIG. connected to. As can be seen, the Zener anode and cathode are instead not in circuit connection as provided by the prior art, and electrode A is connected to an inductive load 23 to control it.

この発明の素子は以下のように動作する。トランジスタ
20がオフにスイッチするとき、誘導子は以前にトラジ
スタ20を介して供給された電流をそれに供給すること
ができるリサイクル要素を必要とする。それゆえ、オフ
にスイッチすると端子Aでの電圧はツェナー21の破壊
電圧にまで迅速に降下する。その結果、ツェナニはオン
になり、負荷23に必要とするリサイクル電流を接地か
ら供給する。
The device of the invention operates as follows. When transistor 20 switches off, the inductor requires a recycling element that can supply it with the current previously supplied through transistor 20. Therefore, when switched off, the voltage at terminal A quickly drops to the breakdown voltage of Zener 21. As a result, the zener is turned on and supplies the required recycle current to the load 23 from ground.

前述の説明から認められるように、この発明はその目的
を充分に達成する。実際、後者をオンにするときの負荷
のための電力制御要素と制御要素をオフにしたときに動
作するリサイクル要素を一緒に含む集積電子素子が設け
られ、ゆえに素子の全体のサイズが減じられる。2つの
イオン注入を用いる技術のために簡単に反復可能となる
電気特性が達成されるので、素子の特性は特に適当で、
一方それに関連した製造技術および費用は絶縁コレクタ
垂直トランジスタの製造を象徴するものである。別の利
点は採用される技術で現在前られる電圧(約30ボルト
)によって与えられ、それは(たとえば継電器の)誘導
性負荷の迅速なスイッチオフまたはリサイクル段階の迅
速な完成を可能にする。これにより負荷自身が迅速な切
換時間を有する比較的高い切換速度が達成できるかもじ
れない。リサイクル要素がなくて負荷に対する危険な電
圧サージとなる危険が招かれるであろうとき。
As can be seen from the foregoing description, the present invention satisfactorily achieves its objectives. In fact, an integrated electronic component is provided which includes together a power control element for the load when the latter is switched on and a recycling element that operates when the control element is switched off, thus reducing the overall size of the component. The characteristics of the device are particularly suitable since easily repeatable electrical properties are achieved due to the technique using two ion implantations.
On the other hand, the manufacturing techniques and costs associated therewith are typical of the manufacture of isolated collector vertical transistors. Another advantage is given by the voltages currently available in the technology employed (approximately 30 volts), which allow a rapid switch-off of inductive loads (for example of relays) or a rapid completion of the recycling phase. This may make it possible to achieve relatively high switching speeds in which the loads themselves have quick switching times. When the absence of a recycling element would result in a risk of dangerous voltage surges to the load.

に電力供給が降下する場合でも素子は適切に利用され得
ることに気付くはずである。
It should be noted that the device can be properly utilized even when the power supply drops.

ここでの発明は発明概念の範囲内で多くの修正および変
化が可能である。
The invention herein is capable of many modifications and variations within the scope of the inventive concept.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の集積制御素子が形成される半導体チ
ップの断面図である。 第2図は第1図の構造の等価回路を示す。 図において、1はサブストレート、2はn型の層、3は
p型のコレクタ層、4はn型のエピタキシャル層、5は
n+型層、6はp+型層、7と8はp+型の層、10′
 と10’はp+型絶絶縁領域ある。 特許出願人 エッセ・ジ・エッセ・ミクロエレットロニ
ー力・エッセ・ピ・ア
FIG. 1 is a sectional view of a semiconductor chip on which an integrated control element of the present invention is formed. FIG. 2 shows an equivalent circuit of the structure shown in FIG. In the figure, 1 is the substrate, 2 is the n-type layer, 3 is the p-type collector layer, 4 is the n-type epitaxial layer, 5 is the n+ type layer, 6 is the p+ type layer, and 7 and 8 are the p+ type layers. layer, 10'
and 10' are p+ type insulation regions. Patent Applicant Esse The Esse Microeret Ronnie Power Esse Pia

Claims (3)

【特許請求の範囲】[Claims] (1)誘導性負荷を制御するための集積電子素子であっ
て、少なくとも1個の第1の極性型のサブストレートと
、前記サブストレートに隣接した、ダイオードを規定す
るそれとの接合を形成する第2の極性型の埋設層とを含
み、前記埋設層に隣接したリサイクルツェナーダイオー
ドを規定するそれとの接合を形成する実質的に前記第1
の極性型のさらに他の層を含み、前記さらに他の層と前
記エピタキシャル層とともに絶縁コレクタや垂直トラン
ジスタを規定する実質的に第2の極性型のエピタキシャ
ル層と実質的に前記第1の極性型の付加のゾーンを含み
、多層構造を含むことを特徴とする素子。
(1) an integrated electronic device for controlling an inductive load, comprising: at least one substrate of a first polarity type; a buried layer of two polar types, forming a junction therewith that defines a recycled Zener diode adjacent to said buried layer;
an epitaxial layer substantially of the second polarity type, and an epitaxial layer substantially of the first polarity type, which together with the further layer and the epitaxial layer define an insulated collector and a vertical transistor; An element characterized in that it comprises an additional zone of , and comprises a multilayer structure.
(2)前記埋設層と前記コレクタ層の間のツェナーダイ
オードを得るためのサブストレートと埋設層とコレクタ
層領域を有する、垂直トランジスタおよび絶縁コレクタ
集積構造の使用法。
(2) Use of a vertical transistor and isolated collector integrated structure having a substrate, a buried layer and a collector layer region to obtain a Zener diode between the buried layer and the collector layer.
(3)誘導性負荷を制御するための、特許請求の範囲第
2項に記載の垂直トランジスタおよび絶縁コレクタ集積
構造の使用法。
(3) Use of the vertical transistor and isolated collector integrated structure of claim 2 for controlling inductive loads.
JP61075374A 1985-04-01 1986-03-31 Integrated electron element for controlling inducing load and use thereof Pending JPS61231746A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT20174/85A IT1221019B (en) 1985-04-01 1985-04-01 INTEGRATED ELECTRONIC DEVICE FOR THE CONTROL OF INDUCTIVE LOADS, WITH RECIRCULATION ELEMENT
IT20174A/85 1985-04-01

Publications (1)

Publication Number Publication Date
JPS61231746A true JPS61231746A (en) 1986-10-16

Family

ID=11164418

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61075374A Pending JPS61231746A (en) 1985-04-01 1986-03-31 Integrated electron element for controlling inducing load and use thereof

Country Status (4)

Country Link
JP (1) JPS61231746A (en)
DE (1) DE3609629A1 (en)
FR (1) FR2579830B1 (en)
IT (1) IT1221019B (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4894622A (en) * 1988-06-15 1990-01-16 U.S. Philips Corporation Integrated current-mirror arrangement comprising vertical transistors
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DE3609629A1 (en) 1986-10-02
IT1221019B (en) 1990-06-21
IT8520174A0 (en) 1985-04-01
FR2579830B1 (en) 1990-07-20
FR2579830A1 (en) 1986-10-03

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