JPS61230512A - Surface acoustic wave device - Google Patents

Surface acoustic wave device

Info

Publication number
JPS61230512A
JPS61230512A JP7086385A JP7086385A JPS61230512A JP S61230512 A JPS61230512 A JP S61230512A JP 7086385 A JP7086385 A JP 7086385A JP 7086385 A JP7086385 A JP 7086385A JP S61230512 A JPS61230512 A JP S61230512A
Authority
JP
Japan
Prior art keywords
conductance
matching
inductive element
receiving electrode
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7086385A
Other languages
Japanese (ja)
Inventor
Atsushi Sasaki
淳 佐々木
Akiami Yuhara
湯原 章網
Kazushi Watanabe
一志 渡辺
Jun Yamada
純 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7086385A priority Critical patent/JPS61230512A/en
Publication of JPS61230512A publication Critical patent/JPS61230512A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To realize low loss and low ripple over a wide frequency range by applying complex number conjugate matching when viewing an irradiation conductance from a conductance of an external circuit and also applying complex number conjugate matching vice versa at the same time. CONSTITUTION:A matching capacitive element 5, a matching capacitive element 3, and a stray capacitance 7 of a pin and package part are connected to a connecting point of a series connecting body comprising a matching inductive element 4 and a wire inductance inductive element 6 and other ends to form a matching circuit as shown in an equivalent circuit. In this circuit, each imaginary part of an admittance Yin viewed from the conductance Gl of a power supply 1 and of an admittance YOUT viewed from an irradiation conductance Ga of an electrode is zero, the real part of the admittance Yin is equal to the conductance Gl and the real part of the admittance YOUT is equal to the conductance Ga by selecting each matching element.

Description

【発明の詳細な説明】 「発明の利用分野〕 本発明は低損失、低リップルを目的とした弾性長面波装
置に係シ、特に高周波で容易に低損矢、低リップルを実
現するのに良好な整合回路°1弾性表面波装置を設計す
る方法に関する自〔発明の背景〕 弾性表面波装置の外部(ロ)路との整合には、従来から
り、O,R,を用いた整合回路が用いられている。例え
ば特開昭56−1575015号公報に示された方法で
は、インダクタンス特性を肩する導電体を弾性表面波装
置に並列に接続している。しかしこの方法では、仮に虚
部の打ち消しができたとしても実部の整合を取る場合、
例えば50Ωの外部回路Glに対して′#L他の放射コ
ンダクタンス0αは20 mlrに設計しなければなら
ず、電極の開口を大きくする必要が生じ基板面積が大き
くなる。
[Detailed Description of the Invention] "Field of Application of the Invention" The present invention relates to an elastic long-plane wave device that aims at low loss and low ripple, and particularly to easily achieve low loss and low ripple at high frequencies. Background of the Invention Regarding the method of designing a good matching circuit °1 surface acoustic wave device [Background of the Invention] Conventionally, matching circuits using O, R, and For example, in the method disclosed in JP-A-56-1575015, a conductor that has an inductance characteristic is connected in parallel to a surface acoustic wave device.However, in this method, if the imaginary part Even if it is possible to cancel, when matching the real part,
For example, for an external circuit Gl of 50Ω, the radiation conductance 0α of '#L must be designed to be 20 mlr, which necessitates making the opening of the electrode larger and increasing the substrate area.

また特開昭56−27525号公報に示される方法は2
つのりアクタンス素子を用いて整合を取る様述べている
。しかしこの方法は通常の2電極構成の弾性表面波装置
を対象としており、電源側から見て複素共役整合と成る
様にリアクタンス素子の値を定めている事なら低損失、
低リップルを目的とした弾性表面波装置・例え#f3′
4惚型構成においては、′に他の放射コンダクタンスG
aから111LTJ1.Itllを見て複素共役整合と
する必要が有るため、前記公開特許では低損矢、低リッ
プルとする事ができない。
In addition, the method shown in Japanese Patent Application Laid-Open No. 56-27525 is 2
It describes how to achieve matching using a linear actance element. However, this method targets surface acoustic wave devices with a normal two-electrode configuration, and if the value of the reactance element is determined so that complex conjugate matching is achieved when viewed from the power supply side, low loss can be achieved.
Surface acoustic wave device for low ripple, example #f3'
In the four-love configuration, another radiation conductance G is added to ′.
a to 111LTJ1. Since it is necessary to obtain complex conjugate matching by looking at Itll, it is not possible to achieve low loss and low ripple in the above-mentioned published patent.

さらに高周波では、弾性表面波素子チップをパッケージ
のピンと電気的に接続するボンディングワイヤのインダ
クタンスが無視できなくなる・ また、パッケージのピンと弾性表面波素子チップを取り
付ける面に発生する浮遊容量も考えなくてはならない。
Furthermore, at high frequencies, the inductance of the bonding wire that electrically connects the surface acoustic wave element chip to the package pin cannot be ignored. Also, it is necessary to consider the stray capacitance that occurs between the package pin and the surface where the surface acoustic wave element chip is attached. It won't happen.

前記2つの公開特許において、これらについては何ら述
べられていない。
There is no mention of these in the two published patents.

〔発明の目的〕[Purpose of the invention]

本発明は、前記従来技術の欠点をなくし、同時に広い周
波数範囲において、低損失、低リップルとする弾性表面
波装置を提供する事にある。
An object of the present invention is to provide a surface acoustic wave device that eliminates the drawbacks of the prior art and at the same time exhibits low loss and low ripple over a wide frequency range.

〔発明の概要〕[Summary of the invention]

本発明では、外部回路のコンダクタンスGlから11c
極の放射コンクタンスGaを見で複素共役整合し、同時
にt憔の放射コンダクタンスGaから外部回路のコンダ
クタンスGlを見てもi索共役整合となる様にする・こ
の時ワイヤのインダクタンスやパッケージのピンとチッ
プを取り付ける面の浮遊容量も考慮した整合回路を見出
した。
In the present invention, from the conductance Gl of the external circuit to 11c
Complex conjugate matching is achieved by looking at the radiation conductance Ga of the pole, and at the same time, i-line conjugate matching is achieved when looking at the conductance Gl of the external circuit from the radiation conductance Ga of the pole. At this time, the inductance of the wire and the pins and chips of the package We have developed a matching circuit that also takes into account the stray capacitance of the mounting surface.

第1図に基本構成を示し、これを説明する。The basic configuration is shown in FIG. 1 and will be explained.

第1図は外部回路、整合素子を含んだ3%極型弾性表面
波装置の中央電極の等価回路図である。ここで1は信号
源、2は信号源(外部回路・)のコンダクタンスGl、
3は整合用の容量性素子01%4は製合用の誘導性素子
L1.5は第2の容量性素子C2,6は第2の誘導性素
子L2.7は[他の11p亀容童Ct、8は電極の放射
コンダクタンスGaである。
FIG. 1 is an equivalent circuit diagram of a central electrode of a 3% polar surface acoustic wave device including an external circuit and a matching element. Here, 1 is the signal source, 2 is the conductance Gl of the signal source (external circuit),
3 is a capacitive element for matching 01% 4 is an inductive element for manufacturing L1.5 is a second capacitive element C2, 6 is a second inductive element L2.7 is [Other 11p Kameyodo Ct , 8 is the radiation conductance Ga of the electrode.

また図に示したYinは外部回路のコンダクタンスG 
t 1iLuから見たアドミタンスを示し、Youtは
′vL極の放射コンダクタンス側から見たアドミタンス
を示す。
In addition, Yin shown in the figure is the conductance G of the external circuit.
t represents the admittance seen from 1iLu, and Yout represents the admittance seen from the radiation conductance side of the 'vL pole.

第1図において(中心周波数において)ニア1nYou
tの虚部が零となり、Yinの実部が(Jtに等しく 
、Youtの実部がGaに等しくなる様に各々の整合用
素子の値を決定する。
In Figure 1 (at the center frequency) near 1nYou
The imaginary part of t becomes zero, and the real part of Yin becomes (equal to Jt.
, Yout is equal to Ga. The value of each matching element is determined so that the real part of , Yout is equal to Ga.

ここで高周波では5の第2の容量性素子C2と6の第2
の誘導性素子L2は、各々デバイスの浮遊容量とワイヤ
のインダクタンスとして弾性表面波装置の実装状態に含
まれる場合もある〔発明の実施例〕 以下、本発明の具体的実施例を示す。
Here, at high frequencies, the second capacitive element C2 of 5 and the second capacitive element C2 of 6
The inductive element L2 may be included in the mounted state of the surface acoustic wave device as the stray capacitance of the device and the inductance of the wire, respectively [Embodiments of the Invention] Specific embodiments of the present invention will be shown below.

まず全体のデバイス構成例を第2図に示す・第2図に示
したものは低損失化弾性表面波装置の一例である3%極
聾構成例である。10は圧電性基板であり、11は電極
の交差幅重み付けを付した入力電極、12.12’は電
極の交差幅重み付けの無い出力電極、1五13′はシー
ルド電極である。第1因に示した等伽回路図は、第2図
に示した11の入力WL極とその外部回路および整容回
路を示している。
First, an example of the overall device configuration is shown in FIG. 2. What is shown in FIG. 2 is a 3% deaf configuration example, which is an example of a low-loss surface acoustic wave device. 10 is a piezoelectric substrate, 11 is an input electrode with electrode cross width weighting, 12.12' is an output electrode without electrode cross width weighting, and 15 and 13' are shield electrodes. The equilateral circuit diagram shown in the first factor shows the 11 input WL poles shown in FIG. 2, their external circuits, and the rectifying circuit.

ここで第2図に示した311L他型構成を、中心周波数
400MH2とした弾性表面波装置として試作し、11
の入力電極の整合を行う・第1図に示した等価回路を用
い、7の電極の靜電容Hotおよび8の電極の放射コン
ダクタンスGaは設計値から中心周波数において2.2
9(PF) 、および2.55(mv)を与え、5の¥
2の容量性素子C2と6の第2の誘導性素子L2にはそ
れぞれ1 (PF)、 4(no)を与えた。
Here, we prototyped the 311L other type configuration shown in Fig. 2 as a surface acoustic wave device with a center frequency of 400 MH2.
- Using the equivalent circuit shown in Figure 1, the electrostatic capacitance Hot of electrode 7 and the radiation conductance Ga of electrode 8 are set to 2.2 at the center frequency from the design values.
9 (PF), and 2.55 (mv), giving 5 ¥
1 (PF) and 4 (no) were given to the capacitive element C2 of No. 2 and the second inductive element L2 of No. 6, respectively.

こむで本実施例において5の02は弾性表面波装置の冥
装実態における浮遊容量とし、6のL2はワイヤのイン
ダクタンスとしている@この条件のもとで、5の整合用
の容量性素子C1を15.4(PF)とし、4の整合用
の誘導性素子Llを29.5(nH)とすれば、中心周
波数においてYinとYou tの虚部はそれぞれt4
(=υ)apl(mりと本近くでき、またYinの実部
は21 (mv)と外部(ロ)路のコンダクタンス20
(mりに近(、Youtの実部は15 (mりと1!!
惚の放射コンダクタンス2.55(−)と一致する。こ
の事から、本実施例における整合時の入力電極の周波数
特性は第3図に示す様に、中心周波数において損失0.
18(αβ)、リップルの原因となる電極間の多重反射
波(以下TTEと略す)を47αβまで抑圧できる。
In this example, 02 in 5 is the stray capacitance in the hidden state of the surface acoustic wave device, and L2 in 6 is the inductance of the wire. Under these conditions, the capacitive element C1 for matching in 5 is 15.4 (PF) and the matching inductive element Ll of 4 is 29.5 (nH), the imaginary parts of Yin and You t are each t4 at the center frequency.
(=υ)apl(m), and the real part of Yin is 21 (mv), and the conductance of the external (b) path is 20
(Close to mri(, Yout's real part is 15 (mrito 1!!
This corresponds to the radiation conductance of 2.55 (-). From this, the frequency characteristics of the input electrode during matching in this example are as shown in FIG. 3, with a loss of 0.0 at the center frequency.
18 (αβ), and multiple reflected waves between electrodes (hereinafter abbreviated as TTE) that cause ripples can be suppressed to 47αβ.

第3図において実線が損失、破線がTTE抑量を示して
いる。
In FIG. 3, the solid line shows the loss, and the broken line shows the TTE suppression.

次に他の実施例を示す。全体のデバイス構成は第1の実
施例と同様であるが、第1図に示した等価回路を用い、
7の電極の静電容量atおよび8の1[極の放射コンダ
クタンスGaは設計値から中心周波数において2.29
 (PF)および255(mv)を与え、5の第2の容
量性素子C2に3(PF)、6の第2の誘導性素子L2
には4 (no)を与えた・ この条件のもとで、3の整合用の容量性素子Osを20
.7(Pk”)とし、4の整合用の誘導性素子L2を2
3.4(nH)とすれば、中心周波数において損失0.
18(αβ)、 T T E抑圧霊46(αβ)と゛な
る◎さらに(第4図に周波数特性を示す様に)TTE抑
圧量が20(αβ)における周波数帯域幅を第1の実施
例に比べて約s MHz広くできる・第2の容量性素子
L2については、本実施例で用いた電極においては5P
fI’以上にするとTTE抑圧量20(αβ)における
周波数帯域幅が狭くなるためそれ以下の値とする事が望
ましい。
Next, another example will be shown. The overall device configuration is the same as that of the first embodiment, but using the equivalent circuit shown in FIG.
The capacitance at of electrode 7 and the radiation conductance Ga of electrode 8 are 2.29 at the center frequency from the design value.
(PF) and 255 (mv), 3 (PF) to the second capacitive element C2 of 5, and the second inductive element L2 of 6
4 (no) is given for ・Under this condition, the matching capacitive element Os of 3 is
.. 7 (Pk"), and the matching inductive element L2 of 4 is set to 2.
3.4 (nH), the loss at the center frequency is 0.
18 (αβ), and 46 (αβ) for TTE suppression. Furthermore, (as shown in the frequency characteristics shown in Fig. 4), the frequency bandwidth when the TTE suppression amount is 20 (αβ) is compared with that of the first embodiment. The second capacitive element L2 can be widened by approximately s MHz.
If it is greater than fI', the frequency bandwidth at the TTE suppression amount of 20 (αβ) will become narrower, so it is desirable to set it to a value less than fI'.

以上2つの実施例を用いて本発明の詳細な説明を行った
が、整合用の各々の素子餉−は設計した′l!極の放射
コンダクタンスQaと静電容量Ctによシ定まシ、前記
した複素共役整合を満足する値とすれば良い・ なお、本発明に記載中の静電容量C1に、たとへば電極
部とパッケージ部分との間に浮遊容量が存在するばあい
は、それらを加えてCtとしても良い。
The present invention has been described in detail using the above two embodiments, and each element for matching has been designed. The radiation conductance Qa and the capacitance Ct of the pole are determined, and it is sufficient to take a value that satisfies the above-mentioned complex conjugate matching.In addition, the capacitance C1 described in the present invention includes, for example, the electrode portion and the package. If there are stray capacitances between the two parts, they may be added to form Ct.

また、前記した説明は高周波の場合であるため、誘導性
素子IJ2をワイヤのインダクタンス容量性素子C2の
一部あるいは全部を浮遊容量としたが、これに限定され
るものでは無く、特にこれ等の容量等があまり問題とな
らない低周波で用いる場合には、容量性素子C2、誘導
性素子L2を与えることで低リップルとなる周波数帯域
幅を広くできる。
In addition, since the above explanation is for a high frequency, the inductive element IJ2 is a part or all of the inductance and capacitive element C2 of the wire as a stray capacitance, but the invention is not limited to this. When used at low frequencies where capacitance and the like are not a big problem, the frequency bandwidth with low ripple can be widened by providing the capacitive element C2 and the inductive element L2.

さらに上記説明は3電憔型構成について説明しているが
、低損失、低リップルを目的とした他の弾性表面fL鉄
装の壷金に用いても良い。
Further, although the above description describes a three-electrode type configuration, it may be used for other elastic surface fL iron-clad pots aimed at low loss and low ripple.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、簡単な整合方法によシ、外部回路のコ
ンダクタンスから見た検素共役整合と、xmの放射コン
ダクタンスから見た複素共役整合が同時に達成でき、か
つ低リップル化となる周波数帯域幅を広くできる事から
、弾性表面波装置の低損失化、低リップル化に貢献でき
る・
According to the present invention, by a simple matching method, the test conjugate matching seen from the conductance of the external circuit and the complex conjugate matching seen from the radiation conductance of xm can be simultaneously achieved, and a frequency band with low ripple can be achieved. Since it can be made wider, it can contribute to lower loss and ripple in surface acoustic wave devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による整合方法の基本等価回路図、第2
図は3′IE他型m成による弾性表面波装置の基本構成
図、第3図は本発明による等価回路を用いて整合を行っ
た場合の第1の実施例の周波数特性図、第4図は個の実
施例による周波数特性図である。 2・・・・・・電?l@(外部回路”) 1111Jの
コンダクタンス 3・・・・・・整合用の容量性素子 4・・・・・・整合用の誘導性素子 5・・・・・・整合用の容量性素子 6・・・・・・ピンとパッケージ部の浮遊容量7・・・
・・・ワイヤのインダクタンス8・・・・・・電極の静
電容量 9・・・・・・電極の放射コンダクタンス狽大、T下E
其pq計(09り
FIG. 1 is a basic equivalent circuit diagram of the matching method according to the present invention, and FIG.
The figure is a basic configuration diagram of a surface acoustic wave device using a 3'IE other type m configuration, Figure 3 is a frequency characteristic diagram of the first embodiment when matching is performed using the equivalent circuit according to the present invention, and Figure 4 is a frequency characteristic diagram according to an embodiment. 2...Electric? l@(external circuit) 1111J conductance 3... Capacitive element for matching 4... Inductive element for matching 5... Capacitive element for matching 6 ... Stray capacitance between pin and package 7...
... Wire inductance 8 ... Electrode capacitance 9 ... Electrode radiation conductance is extremely large, T lower E
Its pq total (09ri)

Claims (1)

【特許請求の範囲】 1、圧電性基板上に1個もしくは複数個のくし形電極群
を電気的に接続した第1の送受波電極を設け、該第1の
送受波電極と相互に弾性表面波を送受する1個もしくは
複数個のくし形電極群を電気的に接続した第2の送受波
電極を設けて成る弾性表面波装置において、少なくとも
第1の送受波電極と、該送受波電極が接続される、コン
ダクタンスGlを持つ外部回路との間に、直列に接続さ
れた第1の誘導性素子L_1と第2の誘導性素子L_2
が、前記送受波電極と外部回路のコンダクタンスGlと
の間に直列に接続され、かつ前記第2の誘導性素子L_
2との接続点ではない側の前記第1の誘導性素子L_1
と、前記外部回路のコンダクタンスGlとの接続点に前
記外部回路のコンダクタンスGlと並列に容量性素子L
_1が接続され、かつ前記第1の誘導性素子L_1と第
2の誘導性素子L_2との接続点に、前記外部回路のコ
ンダクタンスGlに対して並列に容量性素子L_2が接
続され、かつ前記第1の送受波電極の放射コンダクタン
スGaから外部回路のコンダクタンスGl側を見たアド
ミタンスと前記放射コンダクタンスGaと前記第1の送
受波電極の静電容量Ctとから収るアドミタンス特性が
複素共役整合となる様に、前記誘導性素子および容量性
素子を定める、もしくは前記誘導性素子および容量性素
子を定め、整合回路として用い、かつ前記放射コンダク
タンスGaと静電容量Ctを定めた事を特徴とする弾性
表面波装置。 2、第2の誘導性素子L_2を電極部のボンディングパ
ッドとパッケージの入出力ピン間を接続するワイヤのイ
ンダクタンスあるいは、圧電性基板上にプリント化した
インダクタンス、あるいはその両方とした事を特徴とす
る特許請求の範囲第1項に記載の弾性表面波装置。 3、第2の容量性素子L_2の一部あるいは全部をパッ
ケージのピンとデバイスを実装するパッケージ面の間の
浮遊容量とした事を特徴とする特許請求の範囲第1項に
記載の弾性表面波装置。 4、第2の誘導性素子L_2を電極部のボンディングパ
ッドとパッケージの入出力ピン間を接続するワイヤのイ
ンダクタンスあるいは、圧電性基板上にプリント化した
インダクタンスあるいは、その両方とし、かつ第2の誘
導性素子Lの一部あるいは全部をパッケージのピンとデ
バイスを実装するパッケージ面の浮遊容量とした事を特
徴とする特許請求の範囲第1項に記載の弾性表面波装置
。 5、第1の送受波電極を1個とし、第2の送受波電極を
第1の送受波電極の両側に配置した事を特徴とする特許
請求の範囲第1項あるいは特許請求の範囲第2項あるい
は特許請求の範囲第3項あるいは特許請求の範囲第4項
に記載の弾性表面波装置。
[Claims] 1. A first wave transmitting/receiving electrode in which one or more comb-shaped electrode groups are electrically connected is provided on a piezoelectric substrate, and an elastic surface is connected to the first wave transmitting/receiving electrode. In a surface acoustic wave device comprising a second wave transmitting/receiving electrode electrically connected to one or more comb-shaped electrode groups for transmitting and receiving waves, at least the first wave transmitting/receiving electrode and the wave transmitting/receiving electrode are A first inductive element L_1 and a second inductive element L_2 connected in series between a connected external circuit having a conductance Gl.
is connected in series between the wave transmitting/receiving electrode and the conductance Gl of the external circuit, and the second inductive element L_
the first inductive element L_1 on the side that is not the connection point with 2;
and a capacitive element L in parallel with the conductance Gl of the external circuit at the connection point with the conductance Gl of the external circuit.
_1 is connected, and a capacitive element L_2 is connected in parallel to the conductance Gl of the external circuit to the connection point between the first inductive element L_1 and the second inductive element L_2, and the The admittance seen from the radiation conductance Ga of the first wave transmitting/receiving electrode to the conductance Gl side of the external circuit, the radiation conductance Ga, and the capacitance Ct of the first wave transmitting/receiving electrode constitutes complex conjugate matching. , the inductive element and the capacitive element are determined, or the inductive element and the capacitive element are determined and used as a matching circuit, and the radiation conductance Ga and the electrostatic capacitance Ct are determined. surface wave device. 2. The second inductive element L_2 is the inductance of the wire connecting the bonding pad of the electrode part and the input/output pin of the package, the inductance printed on the piezoelectric substrate, or both. A surface acoustic wave device according to claim 1. 3. The surface acoustic wave device according to claim 1, wherein part or all of the second capacitive element L_2 is a stray capacitance between a pin of the package and a surface of the package on which the device is mounted. . 4. The second inductive element L_2 is the inductance of the wire connecting between the bonding pad of the electrode part and the input/output pin of the package, or the inductance printed on the piezoelectric substrate, or both, and the second inductive element L_2 is 2. The surface acoustic wave device according to claim 1, wherein part or all of the elastic element L is a stray capacitance of a pin of the package and a surface of the package on which the device is mounted. 5. Claim 1 or Claim 2 characterized in that the number of the first wave transmitting/receiving electrode is one, and the second wave transmitting/receiving electrode is arranged on both sides of the first wave transmitting/receiving electrode. A surface acoustic wave device according to claim 3 or claim 4.
JP7086385A 1985-04-05 1985-04-05 Surface acoustic wave device Pending JPS61230512A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7086385A JPS61230512A (en) 1985-04-05 1985-04-05 Surface acoustic wave device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7086385A JPS61230512A (en) 1985-04-05 1985-04-05 Surface acoustic wave device

Publications (1)

Publication Number Publication Date
JPS61230512A true JPS61230512A (en) 1986-10-14

Family

ID=13443820

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7086385A Pending JPS61230512A (en) 1985-04-05 1985-04-05 Surface acoustic wave device

Country Status (1)

Country Link
JP (1) JPS61230512A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1394856A2 (en) * 2002-08-29 2004-03-03 Fujitsu Media Devices Limited Surface-mounted electronic component module and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1394856A2 (en) * 2002-08-29 2004-03-03 Fujitsu Media Devices Limited Surface-mounted electronic component module and method for manufacturing the same

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