JPS61227664A - Power converter - Google Patents

Power converter

Info

Publication number
JPS61227664A
JPS61227664A JP6622585A JP6622585A JPS61227664A JP S61227664 A JPS61227664 A JP S61227664A JP 6622585 A JP6622585 A JP 6622585A JP 6622585 A JP6622585 A JP 6622585A JP S61227664 A JPS61227664 A JP S61227664A
Authority
JP
Japan
Prior art keywords
voltage
transformer
circuit
winding
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6622585A
Other languages
Japanese (ja)
Other versions
JPH0313826B2 (en
Inventor
Ryoji Saito
斎藤 亮治
Shuichi Ushiki
修一 宇敷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Origin Electric Co Ltd
Original Assignee
Origin Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Origin Electric Co Ltd filed Critical Origin Electric Co Ltd
Priority to JP6622585A priority Critical patent/JPS61227664A/en
Publication of JPS61227664A publication Critical patent/JPS61227664A/en
Publication of JPH0313826B2 publication Critical patent/JPH0313826B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/40Means for preventing magnetic saturation
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/22Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

PURPOSE:To prevent a switching semiconductor element from damaging due to the saturation of a transformer by connecting the output of a double voltage rectifying and smoothing circuit connected with the tertiary winding of the transformer with a load through a variable impedance circuit. CONSTITUTION:When operated in a normal state, a variable impedance circuit 8 is driven by a detection drive circuit 7, and an internal impedance in substantially zero. However, when the voltage of a capacitor c3, i.e., the output voltage V0 is remarkably low as compared with the normal state, the voltage VC3 of a capacitor C3 is detected by the circuit 7, the internal impedance of the circuit 8 is varied in response t the voltage to always maintain the VC3 to sufficiently avoid the saturation of a transformer T, thereby continuing the operation in the circuit.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は少なくとも6巻線を有するトランスの第1の巻
線にスイッチング半導体素子を接続し、該スイッチング
半導体素子をオン・オフすることにより、上記トランス
の第2の巻線に接続された整流平滑回路を介して負荷に
電力を供給する電力変換装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention connects a switching semiconductor element to the first winding of a transformer having at least six windings, and turns on and off the switching semiconductor element. The present invention relates to a power conversion device that supplies power to a load via a rectifying and smoothing circuit connected to the second winding of the transformer.

〔従来の技術〕[Conventional technology]

第2図及び第3図は従来の電力変換装置を示す図でめシ
、第2図CB)及び26図CB)は夫々第2図(A)及
び第3 IQ (A)の回路の各部の波形を示す図でる
る。
Figures 2 and 3 are diagrams showing conventional power converters, and Figures 2 (CB) and 26 (CB) are diagrams showing the various parts of the circuits in Figures 2 (A) and 3 (IQ (A)), respectively. A diagram showing the waveform.

先ず第2図について説明すると、同図において、1.2
は入力端子、3.4は出力端子、Qlはスイッチング半
導体素子、例えばトランジスタ、Tは第1の巻線である
入力巻線N1  と第2の巻線である出力巻MN2と第
3の巻線であるリセット巻線N3  とを肩するトラン
ス、5はダイオードD1、D2、チョークコイルL1 
 及びコンデンサC1からなる整流平滑回路、2は負荷
、V は入力電圧、’Nl ’ vN2、vN、は夫々
巻線Nl 、N2  、N2  O電圧、vo  は出
力電圧、TolはトランジスタQエ のコレクタ・エミ
ッタ間電圧でるる。
First, let us explain about Figure 2. In the figure, 1.2
is an input terminal, 3.4 is an output terminal, Ql is a switching semiconductor element such as a transistor, T is a first winding (input winding N1), a second winding (output winding MN2), and a third winding 5 is a transformer that shoulders the reset winding N3, diodes D1 and D2, and a choke coil L1.
2 is the load, V is the input voltage, 'Nl' vN2, vN are the winding Nl, N2, N2O voltages, vo is the output voltage, Tol is the collector of the transistor Qe, The emitter voltage is Ruru.

次に第2図の動作1説明する。定常状態で動作している
とき、トランジスタQ1  が時刻t□でオ/してから
時刻t2  でオフするまでの期間をT。Nとすると、
オン期間T。Nでは入力巻線N1に入力電圧v1  が
印加され、トランスTの磁束密度の変化量1ΔB11は
、 1Δ”l l ” −vI TON 1g (但し、n、は巻数N1の巻数、SはトランスTの鉄心
の断面積) となる。
Next, operation 1 in FIG. 2 will be explained. When operating in a steady state, T is the period from when the transistor Q1 turns on at time t□ until it turns off at time t2. If N,
On period T. At N, the input voltage v1 is applied to the input winding N1, and the amount of change 1ΔB11 in the magnetic flux density of the transformer T is 1Δ"l l" -vI TON 1g (where, n is the number of turns of the transformer T, and S is the number of turns of the transformer T. (cross-sectional area of the iron core).

すると、リセット期間TR(TR≦T−ToN%但しで
は周期うでは入力巻線N1  が遮断されるので、リセ
ット巻線N、に電圧が誘起され、咳誘起電圧はダイオー
ドD3を介して入力電圧V、でりニアノブされる。この
時のトランスTの磁束密度の変化量1ΔB21は 1ja21 =−VI TR 3g となる。
Then, during the reset period TR (TR≦T-ToN%, however, the input winding N1 is cut off during the periodic period, so a voltage is induced in the reset winding N, and the cough induced voltage increases to the input voltage V via the diode D3. , the magnetic flux density of the transformer T is changed 1ΔB21 by 1ja21 = -VI TR 3g.

ここでlΔB11 = lΔB21であるのでトランス
Tは飽和せず、時刻t4  で再びトランジスタQ1が
オフして以上の動作を繰返す。
Here, since lΔB11 = lΔB21, the transformer T is not saturated, and at time t4, the transistor Q1 is turned off again, and the above operation is repeated.

次に第3図の動作を説明する。定常状態で動作している
とき、時刻t、から時刻t2マでの、 q トラ/シスrつオン期間T。Nでは入力巻線N0に入力
電圧v1  が印加され、トランスTの磁束密度の変化
量lΔB、 lは、 1jB□l =   VI TON 1g となる。
Next, the operation shown in FIG. 3 will be explained. When operating in steady state, the on-period T from time t to time t2. At N, the input voltage v1 is applied to the input winding N0, and the amount of change lΔB, l in the magnetic flux density of the transformer T becomes 1jB□l=VI TON 1g.

次に時刻t2  から時刻t3 tでのトランジスタQ
1  のリセット期間TB  では入力巻線N0  が
遮断されるので、リセット巻線N、に電圧が誘起され、
該誘起電圧はダイオードi)4  を介して出力電圧v
0  でクランプされる0この時のトランスTの磁束密
度の変化量lハ、1は 1 jB、 I = −vOTR 一 となる。
Next, the transistor Q from time t2 to time t3 t
1 during the reset period TB, the input winding N0 is cut off, so a voltage is induced in the reset winding N,
The induced voltage is passed through the diode i)4 to the output voltage v
0 is clamped at 0. At this time, the amount of change l in the magnetic flux density of the transformer T, 1, is 1 jB, I = -vOTR 1.

ここでlΔB11 = lΔB21であるのでトランス
Tは飽和せず、時刻t4  で再びトランジスタQ1が
オフして以上の動作を繰返す。
Here, since lΔB11 = lΔB21, the transformer T is not saturated, and at time t4, the transistor Q1 is turned off again, and the above operation is repeated.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところで一般に電力変換装置は入力電圧の変変動に反比
例するように可変して、 になるように制御している。
By the way, power converters are generally controlled so that the input voltage is varied in inverse proportion to fluctuations, so that the voltage is controlled as follows.

しかし従来の電力変換装置は、第2図の実施例では、リ
セット期間TRは の関係をもち、第3図の従来例では、リセット期間TR
は の関係をもつ。
However, in the conventional power conversion device, in the embodiment shown in FIG. 2, the reset period TR has the following relationship, and in the conventional example shown in FIG.
has the following relationship.

従って前者は、?が大きくなれは、それに比戸 例してTRも長くなる。後者は弁に関係なくT。Therefore, the former? The bigger the person is, the more Hito For example, TR also becomes longer. The latter is T regardless of the valve.

くすれはよいが、そうすると、トランジスタQ1のコレ
クタ・エミッタ間電圧v91の最大値が大を小さくする
しかなく、これはトランジスタQ1の耐圧ま几は寛流肝
容量を大きくすることになり、どちらもトランジスタQ
1  の選定上不利である。
It may be dull, but in that case, the maximum value of the collector-emitter voltage v91 of the transistor Q1 has to be reduced, and this means that the withstand voltage of the transistor Q1 will increase the permissible current capacitance. transistor Q
1 is disadvantageous in terms of selection.

以上のように従来の装置ではトランジスタQ1の利用率
を向上させることが困難であった。
As described above, in the conventional device, it is difficult to improve the utilization rate of the transistor Q1.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は以上の欠点を除去する友めに、少なくとも3巻
Mを有するトランスの第1の巻線にスイッチフグ牛導体
素子金接続し、該半導体スイッチフグ素子をオ/・オフ
することにより、上記トランスの第20巻線に接続され
次整流平清回路を介して負荷に電力を供給する電力変換
装置において、上記トランスのオ乙の巻線に倍電圧整流
平滑回路を接続すると共に、該倍電圧整流平滑回路の出
力と上記負荷と全可変インピーダ/ス回路金介して接続
したことを特徴とする電力変換装置を提供するものであ
る。
The present invention aims to eliminate the above-mentioned drawbacks by connecting a switch conductor element to the first winding of a transformer having at least 3 turns M, and turning the semiconductor switch conductor element on/off. In a power conversion device that is connected to the 20th winding of the transformer and supplies power to a load via a secondary rectifier circuit, a voltage doubler rectifier smoothing circuit is connected to the second winding of the transformer, and a voltage doubler rectifier smoothing circuit is connected to the second winding of the transformer. The present invention provides a power conversion device characterized in that the output of a voltage rectifying and smoothing circuit is connected to the load via a fully variable impedance/smoothing circuit.

〔作 用〕[For production]

本発明は、上記のような構成になっているので、定常状
態時にリセット期間でスイッチング半導体素子に印加さ
れる電圧は出力電圧及び第1の巻線と第3の巻線との巻
数比とによって決定され、入力電圧の変動に対して一定
となる。
Since the present invention has the above-described configuration, the voltage applied to the switching semiconductor element during the reset period in a steady state is determined by the output voltage and the turns ratio between the first winding and the third winding. determined and remains constant against fluctuations in input voltage.

また出力電圧が定常状態時に比べて著しく低い場合には
可変インビーダンス回路の内部インピーダンスを変化さ
せてトランスの飽和を防止する。
Furthermore, when the output voltage is significantly lower than in the steady state, the internal impedance of the variable impedance circuit is changed to prevent saturation of the transformer.

〔実施例〕〔Example〕

第1図は本発明の一実施例を示す図であり、第1図CB
)は第1図(A)の回路の各部の波形を示す図でおる。
FIG. 1 is a diagram showing an embodiment of the present invention, and FIG.
) is a diagram showing waveforms of various parts of the circuit of FIG. 1(A).

同図において、6はダイオードD5、D6、コンデンサ
C21C3からなる倍電圧整流平滑回路、7は抵抗R,
、R,、ツェナーダイオードZDからなり、コンデ/す
C3の電圧を検出して可変インピーダンス回路8を駆動
する回路でめる08はコンデ/すC1の電圧に応じて検
出駆動回1112!r7により駆動されて内部インピー
ダンスが変化する可変インピーダンス回路であり、例え
ばトランジスタQ2 からなる。
In the same figure, 6 is a voltage doubler rectifier and smoothing circuit consisting of diodes D5, D6 and capacitor C21C3, 7 is a resistor R,
, R, , is a circuit that detects the voltage of the capacitor C3 and drives the variable impedance circuit 8. The circuit 08 detects the voltage of the capacitor C3 and drives the variable impedance circuit 8 according to the voltage of the capacitor C1. This is a variable impedance circuit whose internal impedance is changed by being driven by r7, and is made up of, for example, a transistor Q2.

次に第1図の動作を説明する。Next, the operation shown in FIG. 1 will be explained.

(jL)定常状態で動作しているとき 定常状態で動作しているときには、可変インピーダンス
回路8は検出駆動回路7によフ駆動されており、内部イ
ンピーダンスはほぼ零でおる。また、コンデンサC1に
は入力電圧Vエ とコンデ/すC2の電圧vc2 との
差電圧が充電されている0 時刻t0  から時刻t2  までのトランジスタQ1
のオン期間T。Nでは入力巻l!MN1に入力電圧が印
加され、トランスTの磁束密度の変化量1ノis、11
ΔB、 I =VI TON へ8 となる。
(jL) When operating in a steady state When operating in a steady state, the variable impedance circuit 8 is driven by the detection drive circuit 7, and the internal impedance is approximately zero. Also, the capacitor C1 is charged with the difference voltage between the input voltage Ve and the voltage vc2 of the capacitor C2.
ON period T. In N, input volume l! An input voltage is applied to MN1, and the amount of change in magnetic flux density of transformer T is 1 nois, 11
ΔB, I = VI TON becomes 8.

次に時刻t2  から時刻t31でのトランジスタQ1
  のリセット期間T8 では入力巻線N、が遮断され
るので、リセット巻線N3  に電圧が誘起され、該誘
起電圧はダイオードD6を介してコンデ/すC1の電圧
vc3、即ち出力電圧V。
Next, transistor Q1 from time t2 to time t31
During the reset period T8, the input winding N is cut off, so a voltage is induced in the reset winding N3, and the induced voltage is passed through the diode D6 to the voltage vc3 of the capacitor C1, that is, the output voltage V.

とコンデ/すC2の電圧v02との差電圧V、−V。and the voltage v02 of the capacitor C2, the difference voltage V, -V.

ンスTの磁束密度の変化量1ΔB2Iはとなる。The amount of change 1ΔB2I in the magnetic flux density of the magnetic flux T is as follows.

ここで1ΔB、 I = lΔB21であるのでトラン
スTは飽和せず、時刻t、で再びトランジスタQ0がオ
ンして以上の動作を繰返す。
Here, since 1ΔB and I = lΔB21, the transformer T is not saturated, and at time t, the transistor Q0 is turned on again and the above operation is repeated.

ま友、トランジスタQ1  に印加される電圧v、。Friend, the voltage v applied to the transistor Q1.

l は、リセット期間TRではv9□=v1十−司−vN、
=でめ夕、出力電圧V・ と巻数比マとによって決定さ
n1入力端子の変動に対して一定である。
In the reset period TR, l is v9□ = v1 - Tsu - vN,
= is determined by the output voltage V and the turns ratio and is constant with respect to variations in the n1 input terminal.

これは、第2図、第3図に示す従来例よりも、必要とす
るトランジスタQ1  のコレクタeエミッタ間電圧v
Q□の最大値を低くすることができる。このことより、
vQlの最大値を従来例と同じ値にするならば、トラン
ジスタQ1  の電流許容値を小さくでき、利用重金向
上させることができる。
This is higher than the conventional example shown in FIGS. 2 and 3 because the required collector-e-emitter voltage v of transistor Q1 is
The maximum value of Q□ can be lowered. From this,
If the maximum value of vQl is set to the same value as in the conventional example, the allowable current value of the transistor Q1 can be reduced, and the utilization of heavy metals can be improved.

(b)出力電圧v0が定常状態時に比べ、看しく低い場
合ことから、出力電圧v0  が著しく低い場合、v0
3の値は定常時に比べ者しく低下するか或は負になる場
合もあるので、トランスTが飽和してし葦う0そこでコ
ンデンサC1の電圧vcs t”検出駆動回路7で検出
し、その電圧に応じて可変インピーダンス回路8の内部
インピーダンスを変化させて、−1=屹十−一瓦Vl(
但し、v(Jはnl 可変イノビーダンス回路であるトランジスタQ。
(b) When the output voltage v0 is noticeably lower than in the steady state. Therefore, when the output voltage v0 is extremely low, v0
Since the value of 3 may drop significantly or become negative in steady state, the transformer T may become saturated.Therefore, the voltage of the capacitor C1 is detected by the detection drive circuit 7, and the voltage By changing the internal impedance of the variable impedance circuit 8 according to
However, v(J is nl) Transistor Q is a variable innovidance circuit.

の主電流路に印加される電圧)の関係を炸ル、トランス
Tの飽和を避けるのに充分なりcs f常に維持するこ
とにより、この回路は動作を続けることが可能である。
This circuit can continue to operate by always maintaining the relationship between the voltage applied to the main current path of the transformer T (cs f) sufficient to avoid saturation of the transformer T.

〔発明の効果〕〔Effect of the invention〕

以上述べ友ように本発明は少なくとも3巻線を有するト
ランスの第10巻線にスイッチング半導体素子を接続し
、該半導体スイッチング素子をオ/Qオフすることによ
p1上記トランスの第2の巻線に接続された整流平滑回
路を介して負荷に電力を供給する電力変換装置において
、上記トランスの第3の巻線に倍電圧整流平滑回路を接
続する逅共に、該倍電圧整流平滑回路の出力と上記負荷
とを可変インピータンス回路を介して接続し几ことを特
徴とする電力変換装置である。本発明はこのような特徴
を有するので、スイッチング半導体素子に大きな耐圧を
要求しなくとも、デユーティ比を大きくすることができ
、特に入力寛♂i@の大きな電力変換装置に対して、ス
イッチツク半導体素子の耐圧、電流許容値を大きくする
ことなく高出力を得ることができる。また、トランスの
励磁エネルギは定常出力電圧においては損失なく出力と
して取り出せるので電力変換装置の高効率化が達成でき
る。また、起動時、出力短絡時など、出力電圧が低い時
もトランスのリセットが可能で69、トランスの飽和に
よるスイッチツク半導体素子の破壊を防止することがで
きる0
As described above, the present invention connects a switching semiconductor element to the tenth winding of a transformer having at least three windings, and turns the semiconductor switching element on/off to connect p1 to the second winding of the transformer. In a power converter that supplies power to a load via a rectifier and smoothing circuit connected to the transformer, when a voltage doubler rectifier and smoother is connected to the third winding of the transformer, the This power converter is characterized in that it is connected to the load through a variable impedance circuit. Since the present invention has such characteristics, it is possible to increase the duty ratio without requiring the switching semiconductor element to have a large withstand voltage, and it is particularly suitable for power converters with large input tolerances. High output can be obtained without increasing the withstand voltage and current tolerance of the element. In addition, the excitation energy of the transformer can be taken out as output without loss at a steady output voltage, so high efficiency of the power conversion device can be achieved. In addition, the transformer can be reset even when the output voltage is low, such as when starting up or when an output short-circuit occurs69, which prevents damage to switching semiconductor devices due to transformer saturation.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す図であり、第2図及び
第6図は従来の電力変換装置を示す図である。 1.2・・・入力端子   3.4・・・出力端子5・
・・整流平滑回W&6・・・倍電圧整流平滑回路7・・
・検出駆動回#& 8・・・可変イ/ピーダンス回路Q
l、!・・・トランジスタ  T・・・トランスN、・
・・第1の巻M    N、・・・第2の巻線N3 ・
・・26の巻M    D、〜D6・・・ダイオードZ
D ・・・ツェナーダイオード Ll ・・・チョークコイル C〜C3・・・コンデンサ R1e R2・・・抵抗 2・・・負荷 特許出願人  オリジン電気株式会社 (A) 第3 図
FIG. 1 is a diagram showing an embodiment of the present invention, and FIGS. 2 and 6 are diagrams showing a conventional power conversion device. 1.2...Input terminal 3.4...Output terminal 5.
... Rectification and smoothing circuit W & 6 ... Voltage doubler rectification and smoothing circuit 7...
・Detection drive circuit # & 8...Variable impedance circuit Q
l,! ...Transistor T...Transformer N,...
...First winding M N, ... Second winding N3.
...26 windings M D, ~D6...Diode Z
D...Zener diode Ll...Choke coil C~C3...Capacitor R1e R2...Resistor 2...Load Patent applicant Origin Electric Co., Ltd. (A) Fig. 3

Claims (1)

【特許請求の範囲】[Claims] 少なくとも3巻線を有するトランスの第1の巻線にスイ
ッチング半導体素子を接続し、該スイッチング半導体素
子をオン・オフすることにより、上記トランスの第2の
巻線に接続された整流平滑回路を介して負荷に電力を供
給する電力変換装置において、上記トランスの第3の巻
線に倍電圧整流平滑回路を接続すると共に、該倍電圧整
流平滑回路の出力と上記負荷とを可変インピーダンス回
路を介して接続したことを特徴とする電力変換装置。
A switching semiconductor element is connected to a first winding of a transformer having at least three windings, and by turning on and off the switching semiconductor element, a rectifying and smoothing circuit is connected to a second winding of the transformer. In a power conversion device that supplies power to a load, a voltage doubler rectifier and smoothing circuit is connected to the third winding of the transformer, and an output of the voltage doubler rectifier and smoother circuit is connected to the load via a variable impedance circuit. A power conversion device characterized in that:
JP6622585A 1985-03-29 1985-03-29 Power converter Granted JPS61227664A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6622585A JPS61227664A (en) 1985-03-29 1985-03-29 Power converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6622585A JPS61227664A (en) 1985-03-29 1985-03-29 Power converter

Publications (2)

Publication Number Publication Date
JPS61227664A true JPS61227664A (en) 1986-10-09
JPH0313826B2 JPH0313826B2 (en) 1991-02-25

Family

ID=13309678

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6622585A Granted JPS61227664A (en) 1985-03-29 1985-03-29 Power converter

Country Status (1)

Country Link
JP (1) JPS61227664A (en)

Also Published As

Publication number Publication date
JPH0313826B2 (en) 1991-02-25

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