JPS6122764A - Parallel operation control system of voltage type inverter - Google Patents

Abstract

PURPOSE:To reduce the size and weight of a reactor and to improve the reliability by detecting a cross current between inverters operated in parallel, and delaying an extinguishing pulse applied to a switching element to cancel it. CONSTITUTION:A No.1 inverter 10 has GTO thyristors 11G, 12G and circulating diodes 11D, 12D, GTO thyristors 11G, 12G are alternately turned ON and OFF to convert a DC power into an AC power. A No.2 inverter 20 also has similarly, and AC power is supplied to a load 18 from the both inverters 10, 20 operated in parallel. The output currents I1, I2 are respectively detected by current detectors 14, 24, and a cross current DELTAI and a load current I are respectively detected by adders 31, 32. This is input to a signal converter 37 through a polarity integrating circuit 33, polarity discriminators 34, 35, and a regulator 36, a common pulse oscillation occurs by the output DELTAT, a common firing pulse output from a distributor 41 is delayed by pulse delay circuits 11L-22L, and fed to gate drive circuits 11P-22P.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to a parallel operation control method when voltage source inverters configured with self-extinguishing switching elements are operated in parallel.

[Prior art and its problems]

When operating multiple voltage source inverters in parallel, a method of inserting a reactor into the main circuit is often used to suppress cross current flowing between each inverter.

Fig. 5 is a circuit diagram showing a conventional example in which a reactor is inserted into the AC output circuit of an inverter to suppress cross-current current, and Fig. 5 (a) shows a case where a separate reactor is inserted for each inverter. DC power from DC power source 1 is converted to AC power by two sets of voltage source inverters 2 and 3, and the AC outputs of these inverters 2 and 3 are connected in parallel via reactors 5 and 6, respectively, and then connected to the load. The transverse current flowing between the two inverters 2 and 3 is suppressed by the inductance of the inverters 5 and 6. Also, in Figure 5 (b), the output of each inverter is supplied to the load via a coupling reactor, and the outputs of two sets of voltage source inverters 2 and 3 receiving DC power from DC power supply 1 are AC power is supplied to the load 4 after being connected in parallel via a coupling reactor 7, and this coupling reactor 7 is used only when a cross current flows between both inverters 2 and 3 due to a voltage difference or a phase difference. acts as an inductance to suppress cross-current current.

FIG. 6 is a circuit diagram showing a conventional example of inserting a reactor into the DC input circuit of an inverter to suppress cross-current current. The DC power is supplied to the voltage source inverters 2 and 3 via coupling reactors 8 and 9, respectively, and the voltage source inverters 2 and 3 supply AC power to the load 4 through parallel operation.

The conventional examples shown in FIG. 5 and FIG. 6 mentioned above both attempt to suppress the cross current flowing between inverters operating in parallel by inductance inserted into the main circuit, and these inverters are configured. Differences in switching time due to differences in the characteristics of switching elements, especially when current tends to concentrate on one switching element due to a difference in switching time at turn-off, is effective in transient operation to suppress the increase in current, that is, the increase in cross current. Even if there is, it will not have a significant effect on steady current imbalance caused by variations in the current-voltage characteristics, that is, the on-voltage characteristics, of the switching element and the free-wheeling diode connected in antiparallel to the switching element. Furthermore, when there is a constant amount of cross-current current that can be considered as direct current, there is a risk that the reactor inserted in the main circuit will become biased and no longer act as an inductance even during operation in the aforementioned transient state. In order to prevent this, it is necessary to additionally insert a pure resistor, which is a drawback. They also have the disadvantage of increasing the weight and cost of these reactors due to the large main circuit current flowing through them.

Therefore, there is Japanese Patent Publication No. 57-29952 J as a conventional example of suppressing the cross current by controlling an inverter circuit instead of using the above-mentioned main circuit reactor insertion method.

This is a system in which a controlled rectifier is used as a DC power supply, and multiple inverter devices are installed, each consisting of an inverter connected to this DC power supply, and the AC output sides of the inverters are connected in parallel to operate in parallel. The aim is to make the fundamental wave phase of the inverter output voltage match, detect the output voltage difference with a voltage detector, and control the output DC voltage of the control rectifier to reduce the cross current to zero. This type of method adjusts the voltage in the so-called DC intermediate circuit between the rectifier and the inverter, so on average the cross current is canceled out, but the transient current unbalance associated with element switching is eliminated. Since there is no compensation effect, it is still necessary to insert a reactor into the main circuit for this purpose, and a thyristor or the like must be used in the rectifier to adjust the DC intermediate circuit voltage, making the circuit complicated. This has the disadvantage that the cost also increases.

[Purpose of the invention]

This invention is for parallel operation of voltage-source inverters composed of self-extinguishing switching elements, in which the accelerator that is inserted into the main circuit is omitted or has a very small capacity, and it can be used both steadily and transiently. It is an object of the present invention to provide a parallel operation control method for voltage source inverters that can reduce costs, reduce size and weight, and improve reliability by compensating for current imbalance through control.

[Key points of the invention]

This invention directly or indirectly detects the cross current flowing between a plurality of voltage source inverters configured with self-extinguishing switching elements operating in parallel, and A point extinguishing pulse delay circuit is provided between the common pulse oscillation/distributor that generates and distributes pulses and the gate circuit of the switching element, and the point of the switching element to be delayed is determined based on the magnitude and polarity of the detected cross current. The DC component of the output current of each voltage source inverter is canceled by identifying the extinction pulse and determining the amount of delay, which then performs an adjustment operation that brings the average value of the cross current to zero even in a relatively short period. This is what I am trying to do.

[Embodiments of the invention]

FIG. 1 is a control block diagram showing an embodiment of the present invention, which is a neutral point type single-phase inverter using a gate Kuhn-off thyristor (hereinafter abbreviated as GTO thyristor) as a self-extinguishing switching element. The case where two units are operated in parallel is shown.

In Fig. 1, the No. 1 inverter 10, which is a neutral point type single-phase voltage type impark, is connected in antiparallel to GTO thyristors IIG and 12G as self-extinguishing switching elements, and the respective GTO thyristors IIG and 12G. The GTO thyristors 11G and 12G are alternately turned on and off to convert DC power into AC power. Similarly, the No. 2 inverter may be GTO Cyrisk 2.
It is composed of 1G, 22G and free wheel diodes 21D, 22D connected in antiparallel to these. The DC sides of the No. 1 inverter 10 and No. 2 inverter mentioned above are connected in parallel to the DC power supplies 16 and 17 connected in series, and the AC sides of both inverters 10 and 2 are connected to reactors 13 and n, respectively. If the inverters 10 and 10 are connected in parallel, the load 18 will be supplied with alternating current power from both inverters 10 and 10.

The output current 11 of the No. 1 inverter 10 is detected by the current detector 14, and the output current I2 of the No. 2 inverter is detected by the current detector 1, and is applied to adders 31 and 32, respectively. The adder 31 is an adder that detects the cross current Δ■ from the difference between both input current signals, and this output signal ΔI
is applied to the polarity unification circuit 33.

Further, the adder 32 is an adder that detects a load current I from both input current signals, and this load current signal I is used as a polarity discriminator 3 that discriminates the polarity of the load current and outputs a polarity signal Pl.
4, and the polarity signal Pi from here is input to the aforementioned polarity unification circuit 33, and from this polarity unification circuit 33, when the polarity of the load current is negative, a cross current current with the polarity of the cross current Δ■ is inverted. A signal Δi is output.

However, in FIG. 1, the adder 32 is not required if the load current (2) is detected from the circuit of the load 18 instead of being detected separately from the No. 1 inverter 10 and No. 2 inverter addition. It is obvious that if the currents 11 and 12 of each inverter input to the adder 31 can be determined by a full-wave rectified current signal, the polarity unifying circuit 33 will be unnecessary.

The cross current signal Δi outputted from the polarity unifying circuit 33 is input to a regulator 364ζ, and the output Δt of this regulator 36 is input to the polarity discriminator 35 which outputs a polarity signal P2 together with the cross current signal Δi. Furthermore, the output Δt of the regulator 36
is inputted to the signal switch 37 operated by the polarity signal P2 described above via the single connection or inverting amplifier 36N, and the output signal ΔT of this year switch 37 is input to the common pulse oscillator/distributor 41 outputs the signal switch 37. It is input to pulse delay circuits 11L, 12L, 21L, and 22L that delay the ignition/extinguishing pulse. Either the No. 1 inverter 1o or the No. 2 inverter 21) (in Fig. 1, the No. 2 inverter 20)
), inverting amplifiers 21N and 22N are inserted before the pulse delay circuits 21L and 22L, but the pulse delay circuit and the inverting amplifier may be integrated into one.

The pulse delay circuit referred to here is a so-called phase shifter, and the pulse delay circuit is a so-called phase shifter, and in addition to the No. 1 and No. 2 inverters 10 from the common pulse oscillation/distributor 41, the common point extinguishing pulse gx 'L g
The outputs of these pulse delay circuits 11L, 12L, 21L, and 22L drive gate drive circuits ZIF, 12P, 2IP, and 22P, respectively. Through each GTO thyristor IIG, 12G, 21G, 22
Sent to G gate. Reference numeral 42 denotes a frequency setter for setting the output frequency of both inverters 10 and the additional output frequency.

FIG. 2 is an operation waveform diagram showing the operation of the embodiment shown in FIG. 1, and FIG. ■
2 is shown by a dashed line. Figure 2 (b) shows the cross current signal Δ1111N (c) output from the polarity unification circuit 33.
is the output signal Δt of the regulator 36, and (see FIG. 2) is the signal switching 3.
7 shows the output signal ΔT. Figure 12 (E) Ki Ryo 2
Figure (7) shows the common point arc extinguishing pulse output from the common pulse oscillator/fractionator 41.
IJ) and (NU) are pulse delay circuits 11L and 2, respectively.
1L, 12L.

ignition/extinguishing pulses gll, g21, g output from 22L to turn on and off each GTO cyrisk
1, 2, g22 are shown.

In FIG. 2, currents 11 and 12 that begin to flow through the GTO thyristors 11G and 21G at time tQ gradually generate a current difference due to variations in the on-voltage characteristics (i.e., current-voltage characteristics) of the elements. t-t just before turn-off
Since II>I2 at time 1, a cross current with a value of Δ1(tl) is generated (see Figure 2 (b); note that Δ1
(tl) means the value of the cross current Δi at time t-ts). The output Δ■ of the adder 31 is calculated by the following equation (1).

ΔI −11+ (−12)・・・・・・・・・・・・
・・・・・・・・・・・・・・・・・・・・・・・・
...(1) Therefore, Δ1(ts):>Q, and the output Δt of the regulator 36 generates an extinguishing pulse delay command of Δt*(tl) to cancel the input signal Δ1(tl). (See Figure 2 (c)). In this embodiment, since the regulator opening reversal characteristic is assumed, Δtτt1)<O as shown in FIG. 2(C).

In this way, since the polarity of Δ+(H) and the polarity of Δt”(H) do not match, the output of the signal switch 37, ΔT(
tx) is also not inverted and Δt”(tx)−ΔT(t 1 )
However, this ΔT(tx) is 1x(tt) and Iz(t
Since I(tt), which is the sum with t), is positive, it is sent to pulse delay circuits ILL, 21L, 12L, and 22L. Since an inverting amplifier 21N is inserted before the pulse delay circuit 21L, its input is inverted so that ΔT>O and is sent to the pulse delay circuit 21L.

The pulse delay circuits 11L, 21L, 12L, and 22L have the characteristic of delaying the off pulse, that is, the falling signal, when the input is positive, and delaying the on pulse, that is, the rising signal, when the input is negative. The point-extinguishing pulse given by the circuit 21L to the GTO sirisk 21G, g21, is a pulse delayed by Δt(tl) with respect to the common point-extinguishing pulse g1 (see FIG. 2 (g)). At this time, the pulse delay circuit 11L attempts to generate a pulse gll that is a delayed on-pulse of the common pulse g1, that is, a falling signal, but at t - t 1
Since the common pulse g1 at the time is only an OFF operation, the OFF portion of the pulse g21 is Δt(tx)
This means that the delay will be delayed by a certain amount. In this way, since the off pulse of the GTO thyristor 21G of the No. 2 inverter is delayed, the current I flowing through the GTO thyristor 21G
2 is the cross current Δi that rises transiently and after time t-t1
The polarity of is opposite to that before time t-t1 (
(See Figure 2 (a) and (b)).

By repeating the above adjustment operation, the average value of the cross current Δi is brought to zero, so the DC component of the cross current is canceled.

In the above explanation, the reason why the cross current ΔI flows between the two inverters due to the difference between the output current 1 of the No. 1 inverter 10 and the output current I2 of the No. 2 inverter during parallel operation is as follows. In addition to the voltage characteristics, the first turn of the element. Although this is caused by a difference in the characteristics of the Kuhn-off time, the DC component of the cross-current current can be similarly reduced to zero by the above-mentioned adjustment operation.

In the above description, it is obvious that if the regulator 36 does not have an inverting characteristic, the inverting amplifiers 21N and 22N must be inserted not in the preceding stage of the pulse delay circuits 21L and 22L but in the preceding stage of the pulse delay circuits 11L and 12L. In this embodiment, the polarity of the cross current Δ■ is reversed when the load current I is negative, but if the time constant of the regulator 36 is sufficiently smaller than half of the load current cycle and the response is fast, this 1 of load current
Even though there is a cross current during the period, there is no risk that this cross current ΔI will be canceled out and the output of the regulator 36 will become zero, so there is no need to create an inverted signal depending on the polarity of the load current I. Therefore, the polarity unifying circuit 33 is omitted, and the inverting amplifier 22N for giving a gate signal to the negative side arm of the No. 2 inverter is replaced by the pulse delay circuit 12L.
The circuit is shown in FIG. 3.

FIG. 3 is a control block diagram showing an application example of the present invention, and since the DC power source 16, 17, two sets of impurities 10, 20, and load 18 are the same as in the embodiment shown in FIG. It is omitted. That is, as explained above, by using the regulator 38 with a small time constant, the polarity unifying circuit 33 and the polarity discriminator can be omitted, and the inverting amplifier 22N, which was provided at the front stage of the pulse delay circuit 22L, can be omitted. , instead, a new f is installed before the pulse delay circuit 12L.
, an inverting amplifier 12N is provided, and the other components are adders 31 and 32, a polarity discriminator, and an inverting amplifier 36N.

Signal switch 37, pulse delay circuits 11L, 21L, 12
L, 22L, inverting amplifier 21N, gate drive circuit 11P
, 21P, 12P.

22P, common pulse oscillator/distributor 41, frequency setter 4
Since the name, purpose, and function of 2 are the same as in the case of FIG. 1, their explanation will be omitted.

Viewed from a further perspective, the characteristics of the regulator 36 in FIG. When the polarity discriminator 35 and signal switch 37 in FIG.
The polarity of is reversed to make the signal Δ1゛ (see e9 in Figure 2).
(Refer to) Since it is not necessary, a delayed pulse is selected according to the polarity of the cross current ΔI, so there is no inconvenience caused by the delay in regulator operation, and therefore the signal switch 37 after the polarity discriminator is not necessary. You can also do it.

FIG. 4 shows the pulse delay circuits 11L, 21L, and
12L and 22L are bypassed, and FIG. 4(A) shows the output current 1 of the No. 1 inverter 10.
1 is a solid line, and the output current 12 of the No. 2 inverter is shown as a dashed line. 4(b) is the cross current ΔI output from the adder 31, FIG. 4 G7-1 is the cross current Δi output from the polarity unifying circuit O, polarity signal P1, Fig. 4 (E), (
), (g), and (g) are gate drive circuits 11P, respectively.
, 21P, 12P, and 22P, but since the pulse delay circuit is bypassed, the point extinction pulse signals gll and g21 input to the gate drive circuits 11P and 21F are common pulses. Oscillation number distributor 41
It is the same as the pulse signal g1 output from (Fig. 4 (
(e) (see f)), and gate drive circuits 12P and 22P
Pulse signal gx2c! : g22 is the same as the pulse signal g2 from the common pulse oscillator/distributor 41 (see FIGS. 4(G) and 4(G)). Therefore, as shown in FIG. 4(b), the cross current Δ■ has not decreased at all, and it can be seen that the embodiment of the present invention shown in FIG. 1 is highly effective.

〔Effect of the invention〕

According to the present invention, when a plurality of voltage source inverters configured with self-extinguishing switching elements are operated in parallel, the cross current flowing between these inverters is detected directly or indirectly, and the magnitude of the cross current current is detected. A circuit for selecting and delaying a pulse to be delayed from the output of the regulator is provided, and a regulator is provided to output a delay amount for delaying a turning-off pulse applied to the switching element so as to cancel the cross current. is inserted between the original ignition/extinguishing pulse generator and the gate circuit of the switching element. control is performed so that the average value of the cross-current current generated by this process is reduced to zero, and its DC component is canceled. This eliminates the need to selectively use the element characteristics of switching elements for parallel operation. In addition, since the DC component is canceled in a very small period, the iron core of the reactor installed on the output side of each inverter becomes difficult to saturate, so the amount of iron core can be reduced, and the inductance value of this reactor can be Since a very small value that only suppresses current changes is sufficient, this reactor can be small and lightweight, reducing the cost and improving the reliability of the entire inverter.

[Brief explanation of the drawing]

FIG. 1 is a control block diagram showing an embodiment of the present invention,
FIG. 2 is an operation waveform diagram showing the operation of the circuit shown in FIG. 1, FIG. 3 is a control block diagram showing an application example of the present invention, and FIG. 4 is a pulse delay circuit derived from the circuit shown in FIG. It is an operation waveform diagram when it is omitted. Figure 5 is a circuit diagram of a conventional example in which a reactor is inserted on the AC side of the inverter to suppress cross current current, and Figure 6 is a circuit diagram of a conventional example in which a reactor is inserted in the DC side of the inverter to suppress cross current current. It is a diagram. 1...DC power supply, 2.3...Voltage type inverter 4
...Load, 5,6...Reactor, 7.8.9...
Combined reactor, 10... No. 1 inverter, 20...
No. 2 Impark, 11G, 12G, 21G, 22G...
GTO Sirisk as a self-extinguishing switching element, LID, 12D, 21D, 22D... slow flow diode, 11L, 12L, 21L, 22L... pulse delay circuit, 11P, 12P, 21P, 22P... gate drive Circuit, 12N, 21N, 22N, 36N...Inverting amplifier, 13.23...Reactor, 14. Sae...
Current detector, 1-C1, 17...DC power supply, 18...
・Load, 3], 32...Adder, 33...Polarity unification circuit, 3・I, 35...Polarity discriminator, 36, 3
8...Adjuster, 37.Signal switcher, 41..Common pulse oscillation/distributor, 42..Frequency setting device. Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] Parallel operation is possible by connecting multiple voltage source inverters made up of self-extinguishing switching elements to a DC power source with the same voltage, connecting their AC sides in parallel, and applying a common point-extinguishing pulse to the multiple inverters. In a voltage source inverter, the magnitude and polarity of the cross current flowing between each of the voltage source inverters is detected, and the magnitude and polarity of the cross current flowing just before the self-extinguishing switching element performs a switching operation is used to detect the magnitude and polarity of the cross current flowing between the voltage source inverters. Selecting a point extinction pulse of a specific voltage type inverter running in parallel so as to cancel the cross current, delaying the turn-off or turn-on of the pulse with respect to the common point extinction pulse, and calculating the average value of the cross current. 1. A parallel operation control system for voltage source inverters, characterized in that the delay amount for the common point arc extinguishing pulse is adjusted by the output of a regulator that makes the common point arc extinguishing pulse zero.