JPS61224571A - Horizontal afc circuit - Google Patents
Horizontal afc circuitInfo
- Publication number
- JPS61224571A JPS61224571A JP6433485A JP6433485A JPS61224571A JP S61224571 A JPS61224571 A JP S61224571A JP 6433485 A JP6433485 A JP 6433485A JP 6433485 A JP6433485 A JP 6433485A JP S61224571 A JPS61224571 A JP S61224571A
- Authority
- JP
- Japan
- Prior art keywords
- time constant
- loop filter
- loop
- air
- function
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005684 electric field Effects 0.000 abstract description 2
- 230000004075 alteration Effects 0.000 abstract 2
- 230000010355 oscillation Effects 0.000 description 6
- 238000000926 separation method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
Landscapes
- Synchronizing For Television (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明はテレビ受像機において、水平走査を行なう水
平AFC回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a horizontal AFC circuit that performs horizontal scanning in a television receiver.
従来のとの循の水平AFC回路として、第2図に示すも
のがあった。この第2図において、1は基準周波数を得
るための同期分離回路、2は位相比較器、3は偏向ヨー
クを含めた水平発振回路、4はループフィルターであり
、PLLループを構成している。As a conventional circular horizontal AFC circuit, there is one shown in FIG. In FIG. 2, 1 is a synchronization separation circuit for obtaining a reference frequency, 2 is a phase comparator, 3 is a horizontal oscillation circuit including a deflection yoke, and 4 is a loop filter, which constitutes a PLL loop.
第2図の構成において、映像信号は同期分離回路IK大
入力れ、水平同期信号が取出される。In the configuration shown in FIG. 2, the video signal is input to the sync separation circuit IK, and the horizontal sync signal is taken out.
この水平同期信号は、位相比較器2に入力されると共に
、水平発振回路3からの発振信号が入力され、こめ2つ
の信号の位相比較によシ、その位相差による電圧を出力
する。この出力電圧はループフィルター4を通して水平
発振回路3に供給され、映像信号の水平同期信号にロッ
クした水平発振信号が得られる。This horizontal synchronization signal is input to the phase comparator 2, as well as the oscillation signal from the horizontal oscillation circuit 3, which compares the phases of the two signals and outputs a voltage based on the phase difference. This output voltage is supplied to the horizontal oscillation circuit 3 through the loop filter 4, and a horizontal oscillation signal locked to the horizontal synchronization signal of the video signal is obtained.
従来の水平AFC回路は、以上のように構成されている
ので、ループフィルター4の時定数が固定であるため:
VTRなどのジッタに追従させるように時定数を小さく
すると、オンエア一時の弱入力時にはノイズに追従して
画面に水平方向のゆらぎが生じ、オンエアー弱入力時の
対策として時定数を大きくすると、VTRなどでジッタ
が目立つことになる。Since the conventional horizontal AFC circuit is configured as described above, the time constant of the loop filter 4 is fixed:
If the time constant is made small to follow the jitter of a VTR, etc., it will follow the noise and cause horizontal fluctuations on the screen when there is a temporary weak input on air.If the time constant is made large as a countermeasure for weak input on air, jitter becomes noticeable.
この発明は上記した従来の欠点を除去するために成され
たものでζ−VTRなどのジッタやオンエアの弱入力時
にも水平方向のゆらぎを抑えた画面が得られる水平AF
C回路を提供することを目的とする。This invention was made in order to eliminate the above-mentioned drawbacks of the conventional technology.Horizontal AF allows you to obtain a screen with suppressed horizontal fluctuations even during the jitter of ζ-VTRs and weak inputs on air.
The purpose is to provide a C circuit.
〔発#Iあ1!tlり
この発明の水平AFC回路は、PLLループ内に比較的
大きなループフィルターと小さなループフィルターとを
有し、AGC電圧によってこの2つのループフィルター
を切換えるようにしたものである。[From #IA1! The horizontal AFC circuit of this invention has a relatively large loop filter and a small loop filter in the PLL loop, and the two loop filters are switched by the AGC voltage.
第1図はこの発明の一実施例を示し、第2図と同一部分
は同一符号を記しである。FIG. 1 shows an embodiment of the present invention, and the same parts as in FIG. 2 are denoted by the same reference numerals.
第1図にお−て、PLLループ内には、比較的小さな時
定数のループフィルター4at!−1比較的大きな時定
数のループフィルター4bとを有し、この2つのループ
フィルター4a、4bを切換スイッチ5によシ切換える
。切換スイッチ5はAGC電圧入力により制御信号が出
力される切換信号発生回路6によって切換わる。In FIG. 1, the PLL loop includes a loop filter 4at! having a relatively small time constant. -1 loop filter 4b having a relatively large time constant, and these two loop filters 4a and 4b are switched by a changeover switch 5. The changeover switch 5 is changed over by a changeover signal generation circuit 6 which outputs a control signal based on the AGC voltage input.
この構成によるPLLループとしての動作は第2図と同
様であるが、オンエアー受信時において、その製作が異
なる。オンエア一時にテレビジョン受信以外のファンク
ションを選択したときは、ファンクション連動スイッチ
は開放され、切換スイッチ5は比較的時定数の小さいル
ープフィルター4aに切換わる。The operation as a PLL loop with this configuration is similar to that shown in FIG. 2, but the fabrication is different during on-air reception. When a function other than television reception is selected while on-air, the function interlocking switch is opened and the selector switch 5 is switched to the loop filter 4a, which has a relatively small time constant.
一方、テレビジョンを選択した場合には、ファンクショ
ン連動スイッチは閉成され、切換スイッチ5は切換信号
発生回路6の制御信号によって制御される。On the other hand, when television is selected, the function interlocking switch is closed, and the changeover switch 5 is controlled by the control signal from the changeover signal generation circuit 6.
つまシ、オンエアーの電界強度に応じたRFAGC電圧
を基準電圧と比較し、通常入力時Vζは比較的小さい時
定数のループフィルター4aに切換わ〕、弱入力時には
比較的大きい時定数のループフィルター4bに切換わる
ように切換信号発生回路7から切換スイッチ6に制御信
号が出力される。The RFAGC voltage corresponding to the on-air electric field strength is compared with the reference voltage, and Vζ is switched to the loop filter 4a with a relatively small time constant during normal input, and the loop filter 4b with a relatively large time constant during weak input. A control signal is output from the switching signal generating circuit 7 to the changeover switch 6 so as to switch to the switch 6.
従って、テレビジョンファクション以外のとき1及びテ
レビファンクションで弱入力時には比較的大きな時定数
のループフィルター4bを通してPLLループが動作す
ることによシ、比教的小さな時定数のループフィルター
4aによjj)VTRやビデオディスク等のジッタに追
従できるレベルにし、比較的大きな時定数のループフィ
ルター4bをオンエアー弱入力時のノイズに追従できな
いレベルにすることにより、どめファンクション及びオ
/エア弱入力時でも水平方向のゆらぎのない安定した画
面が得られる。Therefore, when there is a weak input in 1 and TV functions other than the television function, the PLL loop operates through the loop filter 4b with a relatively large time constant, and the PLL loop operates through the loop filter 4a with a relatively small time constant. By setting the level to a level that can track the jitter of VTRs, video discs, etc., and setting the loop filter 4b, which has a relatively large time constant, to a level that cannot track noise during weak on-air input, the level can be maintained even when the stop function and weak air/air input are input. A stable screen with no directional fluctuations can be obtained.
また、RFAGC電圧によるループフィルターの切換え
によ、9、VTRやビデオディスク等をRF信号で入力
した場合でもジッタが目立つことのな一安定した画面が
得られる。Furthermore, by switching the loop filter using the RFAGC voltage, a stable screen without noticeable jitter can be obtained even when an RF signal from a VTR, video disc, etc. is input.
以上のように、この発明によれば、VTR等のジッタや
、オンエアーの弱入力時におiても水平方向のゆらぎの
ない画面を得ることができる口As described above, according to the present invention, it is possible to obtain a screen with no horizontal fluctuation even when there is jitter in a VTR or weak input on air.
第1図はこの発明の一実施例を示す水平AFC回路のブ
ロック図、第2図は従来の水平AF’C回路のブロック
図である。
1・・・・・・同期分離回路
2・・・・・・位相比較器
3・・・・・・水平発振回路
41L、4b・・・・・・ループフィルター5・・・・
・・切換スイッチFIG. 1 is a block diagram of a horizontal AFC circuit showing an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional horizontal AF'C circuit. 1...Synchronization separation circuit 2...Phase comparator 3...Horizontal oscillation circuit 41L, 4b...Loop filter 5...
・・Choice switch
Claims (1)
ープフィルターと、比較的大きな時定数を有する第2の
ループフィルターとを設け、前記第1及び第2のループ
フィルターを、AGC電圧によつて切換えるようにした
ことを特徴とする水平AFC回路。A first loop filter having a relatively small time constant and a second loop filter having a relatively large time constant are provided in the PLL loop, and the first and second loop filters are controlled by an AGC voltage. A horizontal AFC circuit characterized by switching.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6433485A JPS61224571A (en) | 1985-03-28 | 1985-03-28 | Horizontal afc circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6433485A JPS61224571A (en) | 1985-03-28 | 1985-03-28 | Horizontal afc circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61224571A true JPS61224571A (en) | 1986-10-06 |
Family
ID=13255236
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6433485A Pending JPS61224571A (en) | 1985-03-28 | 1985-03-28 | Horizontal afc circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61224571A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5060066A (en) * | 1989-02-21 | 1991-10-22 | Visage, Inc. | Integrating-phase lock method and circuit for synchronizing overlay displays on cathode-ray-tube monitors of digital graphic information and video image information and the like |
US5113257A (en) * | 1987-10-26 | 1992-05-12 | U.S. Philips Corporation | Line synchronising circuit |
US5251032A (en) * | 1987-10-26 | 1993-10-05 | U.S. Philips Corporation | Line synchronizing circuit |
-
1985
- 1985-03-28 JP JP6433485A patent/JPS61224571A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5113257A (en) * | 1987-10-26 | 1992-05-12 | U.S. Philips Corporation | Line synchronising circuit |
US5251032A (en) * | 1987-10-26 | 1993-10-05 | U.S. Philips Corporation | Line synchronizing circuit |
US5060066A (en) * | 1989-02-21 | 1991-10-22 | Visage, Inc. | Integrating-phase lock method and circuit for synchronizing overlay displays on cathode-ray-tube monitors of digital graphic information and video image information and the like |
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