JPS61224433A - Formation of impurity region - Google Patents

Abstract

PURPOSE:To form the impurity regions in a narrow width by suppressing the depth of impurity diffusion and to contrive to improve the integration degree of a semiconduc- CONSTITUTION:An etching is performed on a masking layer 25, a buffer layer 24 and a substrate 21, mesa grooves 29 are formed, an impurity-containing substance.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a method for selectively forming an impurity region that serves as a collector electrode extraction region in a bipolar transistor, for example, when the collector electrode is extracted from the same side of a semiconductor substrate as the base and emitter electrodes. The present invention relates to a method for forming an impurity region that is generally applicable and suitable for forming an impurity region.

[Summary of the invention]

The present invention forms a mesa, that is, unevenness, on the surface of a semiconductor substrate, and deposits a substance containing an impurity on the stepped part, that is, the side wall of the mesa,
This impurity is diffused in a solid phase to form an impurity region having a required narrow width from the sidewall of the mesa toward the inside of the mesa.

[Conventional technology]

An example of a conventional method for obtaining a transistor in which the emitter, base, and collector electrodes are led out from one side of a semiconductor substrate will be described with reference to FIG.

In this case, first, for example, an n-type semiconductor substrate (such as silicon) (
1), and selectively fill the n-type high-concentration buried region (
2), and a p-type channel stopper region (3) surrounding this.

As shown in FIG. 3B, an insulating layer (4) is formed to a required thickness by thermal oxidation at the peripheral part of the buried region (2) from the main surface (1a) side, the so-called field part, and the heating The ion-implanted impurity in the buried region (2) is diffused so that the periphery of the buried region (2) reaches the insulating layer (4), and the channel stopper region (3) is caused to reach the insulating layer (4). I'll try to reach you.

Next, as shown in FIG. 3C, an ion implantation mask layer (5) such as photoresist is applied over the entire surface of the main surface (1a), and the buried portion surrounded by the insulating layer (4) is A window (4a) is formed on a portion of the region (2) using a photographic technique. Then, through this window (5a), the embedded area (
An n-type impurity having the same conductivity type as 2) is ion-implanted and annealing is performed to form a collector electrode extraction region (6).

Thereafter, as shown in the third diagram, in the part facing the main surface (1a) and surrounded by the insulating layer (4), the p-type base region (
7) and further an emitter region (8) thereon by selective diffusion, respectively, to form each region (6).

A collector electrode (9), a base electrode α field, and an emitter electrode (11) are ohmically attached to (7) and (8), respectively.

In this way, one main surface (1a) of the semiconductor substrate (1)
Collector, base and emitter electrodes (91
, Qllll, and (11) are deposited to form a bipolar transistor having collector, base and emitter terminals C, B and E, respectively.

In this way, the collector electrode extraction region (6) is usually formed by introducing impurities by ion implantation or diffusion through the window (5a) formed in the mask layer (5) formed on the semiconductor substrate (1). However, in this case the window (5a
), for example, the width W facing the main surface (1a) of the impurity-introduced region, that is, the collector electrode extraction region (6), is relatively small due to errors in mask alignment during drilling using photographic techniques and restrictions on the minimum mask width. It becomes big. As a result, the area occupied by the transistor as a whole becomes large, making it impossible to achieve sufficient miniaturization, and furthermore, when used in integrated circuits, there is a problem that the degree of integration cannot be sufficiently increased.

Further, as another method for forming a selective impurity region, for example, as disclosed in Japanese Patent Laid-Open No. 58-213470, a mesa is formed and a mask layer is formed covering this mesa. A method has been proposed in which a window is formed on the side of the mesa and impurity ions are selectively implanted through this window. It is practically difficult to perform etching with good controllability, and even in this case, opening the mask layer involves work, so the impurity region must be narrow enough to avoid errors in mask alignment during selective etching. is difficult to form.

[Problem that the invention seeks to solve]

In selectively controlling the region into which impurities are introduced, the present invention makes it possible to avoid an increase in the occupied area of the impurity region on the surface of the semiconductor substrate due to the above-mentioned restriction on opening the diffusion window. A method for forming an impurity region is provided.

[Means for solving problems]

In the present invention, irregularities, that is, mesa portions, are formed on the surface of a semiconductor substrate, and a material containing impurities, such as As silicate glass, is deposited on the sidewalls of the stepped portions, that is, the sidewalls of the mesa, by chemical vapor deposition (CD). V) formed by a method;
The entire surface is anisotropically etched using, for example, reactive ion etching (RIE) to selectively leave As silicate glass on the sides of the mesa, and then heat treatment is used to solid-phase diffuse impurities from the sides of the mesa. An impurity region having a narrow width, that is, a shallow diffusion width, is formed on the side wall of the mesa.

[Effect]

In the present invention, an impurity-containing substance is deposited on the measuring part of the mesa and then diffused to form an impurity region. Therefore, by selecting a small diffusion depth, the surface of the mesa is It is possible to form an impurity region with a narrow area.

〔Example〕

An example of obtaining an npn type transistor according to the present invention will be described in detail with reference to FIG.

In this example, as shown in FIG. 1A, a semiconductor substrate (21) made of, for example, n-type silicon is provided, and selective impurity ions are implanted into each desired depth from its main surface (21a). An impurity implantation region (22) that becomes a low resistivity n-type collector buried region, and surrounding this, a p-type channel stopper region (23) in a ring shape, for example.
form.

Further, on the main surface (21a) of the substrate (21), for example, 5
A Si3N4 mask layer (25), which can serve as a selective oxidation mask, is deposited via the i02 buffer layer (24), for example, by CVD.

As shown in FIG. 1B, a mask layer (25) and a buffer layer (
The substrate (24) is removed by etching, leaving a part of the substrate (24).
1) to form a negative main surface (2) of the substrate (21).
Irregularities, that is, mesas (27), are formed on the 1a) side.

Next, as shown in Figure 1C, at least the mesa (27)
A material layer (2B) containing n-type impurities, for example, an As silicate glass layer containing As having a small diffusion coefficient, is deposited on the entire surface including a part of the side wall portion (27) by the CVD method.

Next, as shown in the first diagram, anisotropic etching in which etching progresses in the thickness direction by, for example, RIE is performed to remove the material layer other than the portion deposited on the side wall portion (27a) of the mesa (27). (28) is removed.

In this case, as shown in FIG. 1C, the material layer (28)
Since the apparent thickness Ll of the attached portion of the side wall portion (27a) of the mesa (27) is larger than the thickness t2 of the other portion, anisotropic etching such as the above-mentioned RIE method is applied. Then, even though the entire surface is etched, the side wall portion (27a
) can remain without being etched away.

Next, as shown in FIG. 1, a resist layer (30) having etching resistance, for example, a photoresist, is applied to the etching solution for the material layer (28), and the mesa (27) is coated using a well-known photographic technique. ) is provided with a window (30a) that exposes the material layer (28) in a portion other than the portion that will eventually form the collector electrode extraction region to the outside. The material layer (28) is then etched away through this window (30a).

After that, heat treatment is performed in an oxidizing atmosphere, and as shown in FIG.
As shown in FIG. 2, an insulating layer (31) made of a thick oxide film is formed in the portions not covered by the oxidation-resistant mask layer (25), and the material layer (28) is removed by this heat treatment or by another heat treatment. The impurity As is mesa (2
1), an n-type collector electrode extraction region (32) with a high impurity concentration is formed by diffusion from the side wall portion (27a). In this case, by selecting the temperature and time of the heat treatment, the mesa (27
) can be selected to be as small as necessary.

In addition, the buried region (22) and channel stopper region (23) formed by ion implantation are formed by heat treatment at this time.
The impurities are diffused and reach the insulating layer (31).

Next, as shown in Figure 1G, the insulating layer (
21) and the collector buried region (33), a p-type base region (35) is sequentially formed facing the main surface (21a) and separated from the collector electrode extraction region (32).
) and an n-type emitter region (36) are formed by selective diffusion or the like, and each region (32) is formed.

collector electrodes (37) at (35) and (36), respectively;
By ohmicly depositing the base electrode (38) and the emitter electrode (39), a bipolar transistor of the npn type is obtained in this example.

Further, with reference to FIG. 2, other examples of the manufacturing method of the present invention are similarly described.
The case where a pn type transistor is obtained will be explained. In FIG. 2, parts corresponding to those in FIG. 1 are given the same reference numerals.

In this example, the collector buried region (22) of the semiconductor substrate (21) is formed on the entire surface at the required depth position, and as shown in FIG. 5 through the buffer layer (24)
An oxidation-resistant mask layer (25) such as iaN4 is formed over the entire surface.

Then, as shown in FIG. 2B, the mask layer (25), the buffer layer (24) thereunder, and the substrate (21) are buried in the buried region (22) by, for example, photolithography.
For example, a ring-shaped or lattice-shaped mesa groove (29) is formed by etching to a depth of .about.000 to form a mesa (27) surrounded by the mesa groove (29).

Next, as shown in FIG. 2C, a material layer containing impurities (
28) is applied including the side wall portion (27a) of the mesa (27).

Thereafter, as shown in the second diagram, etching with anisotropy in the depth direction such as RIB is performed to form the mesa (27
The material layer (28) on the top surface of the mesa (27) and the bottom surface of the mesa groove (29) is etched away, leaving behind a portion of the side wall portion of the mesa (27) having a substantially greater thickness tl. Next, a channel stopper region (23) is formed by selectively implanting p-type impurity ions into the bottom surface of the mesa groove (29) as required.

Thereafter, as shown in FIG. 2E, a heating process is performed in, for example, an oxidizing atmosphere to activate the ion implantation region (23) and remove impurities from the material layer (28) from the side wall (27a) of the mesa (27). ) to the required depth into the mesa. Furthermore, at the same time, an oxide film is formed in the mesa trench (29), and the inside of the mesa trench (29) is filled with the insulating layer (31) of this oxide. In this case, the conditions for this heat treatment should be appropriately selected to take out the collector electrode (3) by solid phase diffusion.
2) penetration into the mesa (27), that is, the diffusion depth is selected to a required narrow width, and under this condition, the inside of the mesa groove (29) can be filled with the oxide insulating layer (31). If not, 5i02 by CVD method etc.
The inside of the mesa groove (29) is filled by depositing and filling the inside of the mesa groove (29).

Next, as shown in Figure 2F, at mesa (27), p
forming a type base region (35) and an n-type emitter region (36) thereon, respectively, for example by selective diffusion;
Collector electrode extraction area (32), base area (35)
), and a collector electrode ( ) on the emitter region (36), respectively.
37), base electrode (38), and emitter electrode (3
9) can be ohmically deposited to form an npn l-transistor.

Also in this case, the side wall portion (27a) of the mesa groove (27)
), the collector electrode lead-out region (32) is formed by solid-phase diffusion from the impurity-containing substance deposited on the electrode, so by selecting the heat treatment conditions for this solid-phase diffusion, its depth can be made shallow. Therefore, the width of the collector electrode extraction region facing the main surface (21a) of the substrate (21) can be selected to be sufficiently small.

In addition, in the example explained in FIG. 2, the channel stopper region (23) and the collector electrode extraction region (32)
For example, after forming the mesa groove (29) as explained in FIG. An insulating layer is interposed between the material layer (28) formed on the side wall (27a) of the mesa (27) and the channel stopper region (23) to maintain a distance therebetween. You can also do it.

In addition, on each side mentioned above, the material layer (28) containing impurities is
In the case of using silicate glass containing arsenic As, in this case As has a relatively small diffusion coefficient, it is advantageous when forming a sufficiently narrow impurity region (32). The material is not limited to phosphorus (P) silicate glass, antimony (Sb) silicate glass, or the like. Further, when forming a p-type impurity region, boron silicate glass or the like can be used.

Furthermore, in each of the above-mentioned sides, the present invention is applied to an npn type bipolar transistor;
) It can be applied not only to the formation of a transistor, but also to the formation of an impurity region in various semiconductor devices, not only to the formation of a collector electrode lead-out region of a transistor.

〔Effect of the invention〕

As mentioned above, in the manufacturing method of the present invention, a semiconductor substrate (
21) An uneven surface, for example, a mesa, is formed on the main surface, and a material layer containing selective impurities is deposited on the sidewalls of the mesa, and the impurities are introduced from the sidewalls into the mesa groove by diffusion of the impurities. Therefore, the impurity region formed in this way can be formed sufficiently narrow by controlling the depth of diffusion. This makes it possible to improve the degree of integration.

[Brief explanation of drawings]

FIGS. 1 and 2 are process diagrams of a method for forming an impurity region according to the present invention, and FIG. 3 is a process diagram of a conventional method for forming an impurity region. (21) is a semiconductor substrate, (27) is a mesa, (29) is a mesa groove, (28) is a material layer containing an impurity, and (32) is an impurity region, for example, a collector electrode extraction region. Fig. 3 3 process opening diagram birth process fl round 2 diagram

Claims (1)

[Claims] Formation of an impurity region characterized by forming an impurity region on the side wall of the stepped portion of a semiconductor substrate having an uneven surface by depositing an impurity-containing substance on the side wall of the stepped portion and heat-treating the material. Method.