JPS6122359B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an alarm display circuit that can display the alarm occurrence status even after the alarm buzzer is reset.

When a condition that requires an alarm occurs, it is widely practiced to alert the operator by sounding a buzzer, for example, to appeal to the auditory senses, or by lighting an LED (light emitting diode), for example, to visually appeal to the operator.
In this case, an audible indication by a buzzer is convenient for informing the operator that an alarm condition has occurred, regardless of the type or cause of the alarm, even when the operator is not paying attention to the alarm device, while a visual indication by an LED The display is useful for distinguishing and informing the operator of the cause of the alarm.

Since the buzzer display is no longer necessary once the operator recognizes the occurrence of an alarm condition, it is often possible for the operator to manually reset the alarm. In this case, the reset
If the LED display is also turned off at the same time, you will not only be unable to tell whether the alarm condition continues or has been canceled after a reset, but also be unable to tell which part has an abnormality, which may affect the operation of the device. This is extremely inconvenient in terms of maintenance.

The present invention aims to eliminate such drawbacks of the prior art, and in order to achieve this objective, the alarm display circuit of the present invention has a system that, when an alarm signal is generated,
In an alarm display circuit that provides an audible display and a visual display, a first memory that is set by the rise of an alarm signal and output goes to a high level and holds the output state until it is reset by a reset signal. an audible display means that operates when the output of the first storage element is at a high level; and an audible display means that is set when an alarm signal is generated so that its output is at a high level, and after the alarm signal is set, the alarm signal disappears and a reset signal is issued. a second storage element whose output is reset to a low level when the alarm is applied; a visual display means which operates when the output of the second storage element is at a high level; and the second
The device is characterized in that it includes a reset switch that supplies a reset signal to the memory element.

Examples will be described in detail below.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the alarm display circuit of the present invention, and FIG. 2 is a time chart showing the operation of each part in the embodiment of FIG.

In FIG. 1, when an alarm occurs, the input terminal 1 changes from low level to high level due to the alarm signal, and the first storage element 2, which is a D-type flip-flop, is set and its output Terminal _Q1 becomes high level. In the memory element 2, _C1 is a clock terminal to which an alarm signal is applied, _D1 is a data input terminal to which a high level constant voltage _VDD is always applied, and _R1 is a reset input. This is a terminal, and by applying a high level input thereto, the memory element 2 is reset. The required function of the memory element 2 is to detect the rising edge of the alarm signal and to hold its output terminal _Q1 at a high level until it is set and reset.

When the output terminal Q ₁ of the memory element 2 becomes high level, a base current flows into the transistor 4 through the series resistor 3, turning it on, and a current flows from the power supply +V _C through the resistor 5, turning off the buzzer 6. Make me groan.

The alarm signal is simultaneously applied to the second storage element 7, which is a set priority latch, and the storage element 7 enters the set state, and its output terminal _Q2 also becomes high level. Note that in the memory element 7, _S2 is a set input terminal to which an alarm signal is applied. Further, _R2 is a reset input terminal, and by applying a high level input thereto, the memory element 7 is reset. The function required of the memory element 7 is that when the alarm signal is at a high level, it is set and the output terminal _Q2 becomes a high level, and once set, even if the alarm signal changes from high level to low level, the reset input is not activated. The set state is maintained unless the alarm signal becomes high level, and when the alarm signal is low level and the reset input becomes high level, it is reset and the output terminal _Q2 becomes low level.

As a result, a base current flows to the transistor 9 through the series resistor 8, turning it on, and a current flows from the power supply +V _C through the resistor 10 to the LED1.
1 lights up.

When the reset switch 12 is then operated and turned on, a constant voltage V _DD is applied to the reset terminal R ₁ of the memory element 2 and the reset terminal R ₂ of the memory element 7 . As a result, the output terminal _Q1 of the memory element 2, which is a D-type flip-flop, becomes a low level regardless of the alarm signal at the terminal _C1 . However, the output terminal _Q2 of the storage element 7 consisting of a set priority R-S latch is the input terminal
If the _S2 alarm input remains at high level, it remains at high level and does not change.

Now, with the output terminal Q ₁ of storage element 2 at low level and the output terminal Q ₂ of storage element 7 at high level, even if the alarm signal at input terminal 1 goes to low level, each storage element Output status does not change. Furthermore, when the alarm signal at the input terminal 1 changes to high level again in this state, the output terminal _Q1 of the storage element 2 becomes high level, and as a result, current flows through the buzzer 6 again, causing it to buzz.

The conditions under which the output terminal _Q2 of the storage element 7 can change from high level to low level are that the alarm signal at input terminal 1 is at low level and the reset switch 1
2 is operated and a constant voltage _VDD is applied to the reset terminal _R2 .
only when given.

The time chart of FIG. 2 shows the specific operation of the circuit of FIG. 1 in various cases. Second
In the figure (a) is the alarm signal at terminals C ₁ and S ₂ , (b) is the signal for the operation of the buzzer at terminal Q ₁ , (c) is the signal for the operation of the LED at terminal Q ₂ , (d ) represent the reset input signals at terminals _R1 and _R2 , respectively.

In Fig. 2, (A) shows the first operation example;
The operation example shown in the figure is performed according to the following steps.

′ When an alarm occurs, the buzzer sounds and the LED lights up.

′ The buzzer will stop buzzing by resetting it, but the alarm condition continues.
The LED remains lit.

Even if you reset it again, the alarm status continues, so the LED remains lit.

Furthermore, when a reset is performed, the LED will turn off since the alarm state is no longer present. In addition, in the part (A) of Figure 2, the numbers...
each correspond to the same numbered stage in the above description.

In Fig. 2, (B) shows the second operation example;
The operation example shown in the figure is performed according to the following steps.

′ When an alarm occurs, the buzzer sounds and the LED lights up.

′ The buzzer stops buzzing by resetting it, but the alarm status continues, so the LED
remains lit.

′ The alarm occurred again while the LED was lit, so the buzzer sounded again.

′ The buzzer will stop buzzing by resetting it, but the alarm condition continues.
The LED remains lit.

′ When a further reset is performed, the LED will turn off because the alarm state is no longer present. In addition, in the part (B) of Figure 2, the numbers ′, ′,
′, ′, ′ correspond to the same numbered steps in the above description, respectively.

In Fig. 2, (C) shows the third operation example;
The operation example shown in the figure is performed according to the following steps.

″ When an alarm occurs, the buzzer sounds and the LED lights up.

``When the reset is performed, the alarm status is no longer present, so the LED will also turn off at the same time as the buzzer stops.

Note that in the part (C) of FIG. 2, the numbers "," respectively correspond to the stages with the same number in the above explanation.

FIG. 3 is a circuit diagram showing the configuration of another embodiment of the alarm display circuit of the present invention. In Fig. 3, the symbols 1, 3, 4, 5, 6, 7, 8, 9, 10, 11,
12 is the same as that in the embodiment of FIG. 13 is Edge Trigger J-K
The first memory element is a flip-flop. In the memory element 13, C is a clock terminal, and when an alarm signal is applied thereto, it is set and the output terminal _Q1 becomes high level. Note that the J terminal is always given a high level input, and the K terminal is grounded and kept at low level. The functions required of the first memory element 13 are the same as those of the first memory element in the embodiment of FIG. 1, and therefore the configuration shown in the embodiment of FIG. Since it is clear that the same operation as in the example can be performed, detailed explanation will be omitted.

As explained above, according to the alarm display circuit of the present invention, if the alarm condition continues after an alarm signal is generated and the buzzer is reset, the LED remains lit to prompt the operator to take countermeasures. be able to. If the alarm signal is generated again while the LED is lit, the buzzer will sound again to alert the operator that an alarm condition has occurred.
The operator who has taken the appropriate measures will be able to know that the alarm has been canceled by resetting the alarm and turning off the LED. Furthermore, if you perform a reset when an alarm signal is generated, the buzzer sounds, and the LED is lit, if the alarm condition has already been resolved, the LED will also go out at the same time as the buzzer stops, so the alarm condition will disappear. can be known immediately.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing the configuration of an embodiment of the alarm display circuit of the present invention, Fig. 2 is a time chart showing the operation of each part in the embodiment of Fig. 1, and Fig. 3 is the alarm display circuit of the invention. FIG. 2 is a circuit diagram showing the configuration of another embodiment. 1...Alarm signal input terminal, 2...Storage element, 3
... Series resistance, 4 ... Transistor, 5 ... Resistor, 6 ... Buzzer, 7 ... Memory element, 8 ... Series resistance, 9 ... Transistor, 10 ... Resistor, 11
...LED, 12...Reset switch, 13...
...Memory element.

Claims (1)

[Claims] 1. When an alarm signal is generated, in the alarm display circuit that provides audible and visual display, the output is set to high level by the rising edge of the alarm signal.
a first storage element that retains its output state until reset by a reset signal; an audible display means that operates when the output of the first storage element is at a high level; When the alarm signal disappears and the reset signal is applied, the second memory element is reset and its output becomes low level, and the output of the second memory element becomes high level. 1. An alarm display circuit comprising: a visual display means which operates when the alarm display is activated; and a reset switch which supplies a reset signal to said first and second storage elements when resetting the alarm display.