JPS61219207A - Cmos differential amplifier - Google Patents

Abstract

PURPOSE:To obtain stable CMOS differential amplifiers without damaging the responding speed against the variation of transistor capability in the manufacturing process, by inputting an activating signal in a gate terminal and connecting the 6th MOS transistor, whose conductive channel is different from those of the 1st-3rd MOS transistors, between drain terminals of the 4th and 5th MOS transistors. CONSTITUTION:When an activating signal (phi) is 'H' level and a CMOS differential amplifier is activated, the amplifier has a differential amplifying function as conventional ones have, since a P-channel MOS transistor Q16 is in its 'OFF' condition. When the activating signal (phi) is 'L' level and the CMOS differential amplifier is inactivated, the P-channel MOS transistor Q16 is set to its 'ON' condition. Therefore, a node N and output signal OUT are maintained at equal potential even when a difference exists between the transistor capabilities between P-channel MOS transistors Q11 and Q12 and N-channel MOS transistors Q13 and Q14. Therefore, if the activating signal (phi) is changed from the 'L' level to the 'H' level and the differential amplifying operation of the amplifier is started at times t1 and t2, the responding speed is not delayed, because the node N and output signal OUT always change from the equal potential.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a CMOB differential amplifier.

[Conventional technology]

FIG. 3 is a circuit diagram of a conventional example of this type of CMOS differential amplifier/differential amplifier. This CMOB differential amplifier has differential input signals IN and IN applied to its gate terminals, respectively, and N which forms a differential pair.
Channel MO8) Kunjistor Q1@* Qs4 and the source terminal are connected to the ground terminal GND K, and the activation signal φ input to the gate terminal becomes @H- level, and the CM
When the OB differential amplifier operates, it operates in the saturation region and becomes a constant current source. An N-channel MO transistor Qts that operates in the saturation region and becomes a constant current source, and a Pf Yarnel transistor Q It consists of N-channel MO8 transistor Qss
drain terminal of N-channel MO8) transistor Qts
*The source terminal of Qta is connected to configure a differential amplifier circuit, while the P-channel MOS) transistor C15t
Each gate terminal of eQtt is connected to the drain terminal of a P-channel MO8) transistor Qts, and becomes a kind of Karen)1ler, forming an active load circuit. P channel MO
B) Transistor Qll and N-channel MOS) Each drain terminal of transistor Qts and P-channel MO8) Transistor Q11 and N-channel MOS)
The drain terminals of transistor Q14 are connected, and the differential input signals IN and IN of opposite phases are connected to the N-channel MOS transistor Q14.
+- transistor Qllll I (N-channel MOS when applied to the gate terminal of lta) transistor %
A difference occurs in the on-resistance of eQs, and together with the differential amplification operation of the N-channel MOS transistor QtseQtteQim, the output signal OUT in phase with the differential input signal IN has a high gain due to the current mirror effect of the P-channel MO8) transistor Qtt eQt*. It can be obtained with

[Problem to be Solved by the Invention 3] Next, the variation in transistor performance due to misalignment of the mask during the manufacturing process will be explained with reference to the above-mentioned conventional 0MO8.

Suppose that the transistor capability of the P-channel MO8) transistor Qn is lower than that of the P-channel MO8) transistor Qlt, and this will be explained by focusing on the potential of the node N and the output signal OUT. First, when the activation signal φ is II and the level is inactive (to≦time 1+ <time 11), even if the differential input signals IN and IN are at the same potential, the output signal OUT has a high potential difference compared to the node N. A case will be described in which the dynamic amplification operation is started.

When the differential input signal IN changes to a higher potential than the differential input signal IN, the output signal OUT changes to a higher potential than the node NK, so there is no delay in response speed.
On the other hand, when the differential input signal IN changes to a lower potential side than the differential input signal INK (time t), the output signal OU
T changes from a high potential to an equal potential to a low potential compared to the node NK. Therefore, the response speed is delayed by T until the output signal OUT becomes equal in potential to the node N and cancels the unbalanced potential ΔV.

So far, we have explained the case where the transistor performance of the P-channel MO8) transistor Qll has decreased.
During the period of 14, the Pf Janel MO8 transistor QIIQI which constitutes the active load circuit! It is clear that a difference in transistor capability between the two also causes a delay in response speed.

An object of the present invention is to provide a stable CMOS structure that can withstand variations in transistor performance during the manufacturing process without sacrificing response speed.
An object of the present invention is to provide a differential amplifier.

[Means for solving problems]

The present invention provides a first
．． a second MOS) transistor, a third MOS) transistor which inputs an activation signal to its gate terminal and constitutes a constant current source; Second. 3rd MOS) The transistor and conduction channel are different, and the 4th MOS constitutes a pair of load elements. The fifth MOS) has a transistor as a component, and the first MOS. The source terminal of the second MOS transistor is commonly connected to the drain terminal of the third MOS transistor,
1st. The drain terminal of the second MOS transistor is the fourth
．． In a CMOS differential amplifier, the gate terminals of the fourth and fifth MOS transistors are connected to the drain terminals of the first MOS transistor, respectively, and the gate terminals of the fourth and fifth MOS transistors are commonly connected to the drain terminal of the first MOS transistor. Input the activation signal and select the 1st. 2nd and 3rd.

When the activation signal φ is at IL'' level and the CMOS differential amplifier becomes inactive, the sixth MOS transistor is turned on.
．． Even if there is a difference in transistor ability between the fifth MOS transistors, the node N and the output signal OUT are kept at the same potential. Therefore, when the activation signal φ changes from the 1L level to the IH level and the differential amplification operation is started, the node N and the output signal OUT always change from the same potential, and there is no delay in response speed.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of a CMOS differential amplifier according to the present invention.

In the CMOS differential amplifier of this embodiment, in the conventional example shown in FIG. 2, the activation signal φ is applied to the gate terminal between the node N and the output signal OUT. When the CMOS differential amplifier is activated at the lH level, the P-channel MO8 transistors Q, .

Next, when the activation signal φ is "L level" and the CMOS differential amplifier becomes inactive, the transistor Ql
ll turns on. Therefore, P channel MO8)
Even if there is a difference in transistor ability between the transistors 9116911, N-channel MO8) transistors Qss, and the transistor Qss, the node N and the output signal OUT are kept at the same potential.

When the differential amplification operation is started, the node N and the output signal OUT always change from an equal potential, so there is no delay in response speed.

〔Effect of the invention〕

As explained above, in the present invention, an activation signal is input to the gate terminal, and the first . This has the effect of making it possible to construct a stable CMOS amplifier with no delay in response speed against variations in transistor performance in the second and third MO8 processes.

[Brief explanation of the drawing]

FIG. 1 shows an example of a CMOS differential amplifier according to the present invention.
* Ql! * Ql. ...P channel MO
B) Langister. Qss *Qba *Qss...N-channel MOB) transistor. IN, IN/Old...Differential input signal. OUT ・・・・・・・・・・・・Output signal. N・・・・・・・・・Node Point. 4・・・・・・・・・Activation signal. Vcc...... Radio terminal. GND・・・・・・Ground terminal.

Claims (1)

[Claims] The first and second M, which form a differential pair with the gate terminal as input,
The OS transistor, a third MOS transistor that inputs an activation signal to its gate terminal and forms a constant current source, and the first, second, and third MOS transistors have different conduction channels and form a pair of load elements. 4th and 5th MOS
The source terminals of the first and second MOS transistors are commonly connected to the drain terminals of the third MOS transistor, and the drain terminals of the first and second MOS transistors are connected to the fourth and fifth MOS transistors. The fourth and fifth MOs are connected to the drain terminals of the MOS transistors respectively.
In a CMOS differential amplifier in which the gate terminals of the S transistors are commonly connected to the drain terminals of the first MOS transistors, the activation signal is input to the gate terminals, and conduction is established with the first, second, and third MOS transistors. A sixth MOS transistor with a different channel is connected to the fourth and fifth MOS transistors.
A CMOS differential amplifier characterized in that it is connected between drain terminals of an OS transistor.