JPS6121880Y2 - - Google Patents

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Publication number
JPS6121880Y2
JPS6121880Y2 JP1100879U JP1100879U JPS6121880Y2 JP S6121880 Y2 JPS6121880 Y2 JP S6121880Y2 JP 1100879 U JP1100879 U JP 1100879U JP 1100879 U JP1100879 U JP 1100879U JP S6121880 Y2 JPS6121880 Y2 JP S6121880Y2
Authority
JP
Japan
Prior art keywords
circuit
amplification
insulating substrate
high frequency
uhf band
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1100879U
Other languages
Japanese (ja)
Other versions
JPS55109958U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1100879U priority Critical patent/JPS6121880Y2/ja
Publication of JPS55109958U publication Critical patent/JPS55109958U/ja
Application granted granted Critical
Publication of JPS6121880Y2 publication Critical patent/JPS6121880Y2/ja
Expired legal-status Critical Current

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  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structure Of Receivers (AREA)

Description

【考案の詳細な説明】 この考案は絶縁基板を用いてプリント配線した
チユーナ、特にUHF帯RF信号の増幅又は減衰回
路におけるプリント板高周波回路装置に関する。
[Detailed Description of the Invention] This invention relates to a tuner printed with wiring using an insulating substrate, and particularly to a printed board high-frequency circuit device in an amplification or attenuation circuit for UHF band RF signals.

一般の増幅素子は高周波的に接地すべき端子又
はリードを有しており、この端子又はリードを接
地して高周波増幅がなされる。しかし、このよう
な接地用端子又はリードの確実且つ完全な接地は
所望されるリード長や回路配置状況により非常に
困難であり、リードインダクタンスやストレー容
量としての悪影響が知られている。特に、UHF
帯域の信号を処理する場合の回路素子からパスコ
ンまでのリード長の悪影響はこのような回路特性
を大きく劣化させるものであることを体験的に知
得している。これは接地されるべき端子又はリー
ドが高周波的にホツトになり、出力側から入力側
への帰還あるいは逆方向の結合があるからである
と考えられ、これらはストレー容量に起因してい
ると考えられる。例えば、増幅素子としてFET
を用いてAGC信号を与えて利得減衰させると
き、FET素子の内部帰還が非常に小さく0.05PF
以下であるのに対しストレー容量がこれに比べて
大きな0.1PF以上になつており、そのために入出
力の分離が行なわれず充分な減衰特性が得られな
い。
A general amplification element has a terminal or lead that should be grounded at high frequencies, and high frequency amplification is performed by grounding this terminal or lead. However, reliable and complete grounding of such a grounding terminal or lead is extremely difficult depending on the desired lead length and circuit layout, and is known to have an adverse effect on lead inductance and stray capacitance. In particular, UHF
It has been learned from experience that the adverse effect of the lead length from the circuit element to the bypass capacitor when processing band signals greatly deteriorates the circuit characteristics. This is thought to be because the terminal or lead that should be grounded becomes hot at high frequencies, and there is feedback or reverse coupling from the output side to the input side, and this is thought to be caused by stray capacitance. It will be done. For example, FET as an amplification element
When applying an AGC signal and attenuating the gain using
However, the stray capacitance is larger than 0.1PF, which is why the input and output are not separated and sufficient damping characteristics cannot be obtained.

従つて、考案の目的は前述する欠陥を除去する
ことにあり、特にUHF帯RF信号のプリント配線
回路に対して改良された高周波回路を提供するこ
とにある。
Therefore, the object of the invention is to eliminate the above-mentioned deficiencies, and in particular to provide an improved high frequency circuit for printed wiring circuits for UHF band RF signals.

本考案によれば、UHF帯の増幅又は減衰用回
路素子をプリント配線するものにおいて配線位置
に対応する部分の絶縁基板の両面を実質的にアー
ス用導電パターンで覆われた高周波回路が提供さ
れる。具体的な高周波チユーナにおいて、シール
ド区画して形成されたUHF帯RF信号の増幅又は
減衰回路は、少なくともこの回路素子の配置され
る絶縁基板の表裏両面に素子リード用挿通孔部分
を除く略全面に導電パターンを形成しこのパター
ンをシールド仕切板に半田接続して接地して構成
される。このような構造は回素子の端子又はリー
ドや絶縁基板上のプリント配線用ランド間に生ず
るストレー容量を減じて減衰を十分にし、キンク
バツクの小さい高周波回路を提示する。従つて
RF信号の不必要な結合が抑止されて設計上から
所望される増幅又は減衰特性が得られる。尚本考
案はUHF帯域のRF信号を処理するに際して見い
出されたものであり、UHF帯域又はこれ以下の
周波数帯の信号を扱う場合には特に重要な問題と
ならないことに注意すべきである。例えば、
VHF帯ではストレー容量による帰還も少なくな
り且つ帰還量の絶対値が小さくなる。
According to the present invention, there is provided a high frequency circuit in which UHF band amplification or attenuation circuit elements are printed-wired, in which both surfaces of an insulating substrate in a portion corresponding to the wiring position are substantially covered with grounding conductive patterns. . In a specific high-frequency tuner, the UHF band RF signal amplification or attenuation circuit formed by dividing the shield covers at least the entire surface of the insulating substrate on which this circuit element is placed, excluding the insertion hole for the element lead, on both the front and back surfaces of the insulating substrate. It is constructed by forming a conductive pattern and connecting this pattern to a shield partition plate by soldering and grounding. Such a structure reduces the stray capacitance generated between the terminals or leads of the frequency element and the lands for printed wiring on the insulating substrate, provides sufficient attenuation, and presents a high frequency circuit with small kinkback. accordingly
Unnecessary coupling of RF signals is suppressed, and the amplification or attenuation characteristics desired from the design point of view can be obtained. It should be noted that the present invention was discovered when processing RF signals in the UHF band, and does not pose a particularly important problem when dealing with signals in the UHF band or lower frequency bands. for example,
In the VHF band, there is less feedback due to stray capacitance and the absolute value of the amount of feedback is small.

以下、本考案に係る実施例を図面を参照しつつ
詳述する。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

第1図及び第2図は本考案に係る高周波回路装
置であり、チユーナにおけるUHF帯RF信号の増
幅回路部分を示している。図において、UHF帯
チユーナ1は複数個のシールド区画室2〜5を上
下のシールドカバー6,7と仕切板8〜10とに
より構成される。このうち区画室3はUHF帯RF
信号の増幅回路であり、各区画室を横切つて配置
された絶縁基板11にプリント配線によつて形成
されている。
FIGS. 1 and 2 show a high frequency circuit device according to the present invention, and show an amplification circuit portion of a UHF band RF signal in a tuner. In the figure, a UHF band tuner 1 includes a plurality of shield compartments 2 to 5 formed by upper and lower shield covers 6 and 7 and partition plates 8 to 10. Of these, compartment 3 is UHF band RF
This is a signal amplification circuit, and is formed by printed wiring on an insulating substrate 11 placed across each compartment.

区画室3の高周波増幅回路装置は絶縁基板11
上に配置された増幅素子12やコイル13の回路
素子を裏面側の配線パターン14に半田15によ
つて接続して構成している。この回路構成におけ
る本考案の特徴は、これらの回路素子のリード用
挿通孔16の周辺部又は部品を絶縁的に保持する
必要のある部分17を除く表面側及びプリント配
線パターン14とその周辺部分を除く裏面側に各
略全体を覆うような導電パターン18と19とが
形成され、これらのパターン18と19が半田2
0と21によつて仕切板8〜10に接続され、ア
ースパターンを形成していることにある。すなわ
ち、他の区画室2,4が絶縁基板11上に直接回
路素子を配置するのに対し、区画室3の高周波増
幅回路では絶縁基板11の両面にアース用導電パ
ターン18と19を介して回路素子12,13が
配置される。
The high frequency amplification circuit device in the compartment 3 is an insulating substrate 11
The circuit elements such as the amplifying element 12 and the coil 13 arranged on the top are connected to the wiring pattern 14 on the back side by solder 15. The feature of the present invention in this circuit configuration is that the surface side, excluding the area around the lead insertion hole 16 of these circuit elements or the area 17 where it is necessary to hold the component insulatively, and the printed wiring pattern 14 and its surrounding area are Conductive patterns 18 and 19 are formed on the other side of the back surface so as to cover almost the entire surface of each conductive pattern, and these patterns 18 and 19 are connected to the solder 2.
0 and 21 to form a ground pattern. In other words, while the other compartments 2 and 4 have circuit elements placed directly on the insulating substrate 11, in the high frequency amplification circuit of the compartment 3, the circuit elements are placed on both sides of the insulating substrate 11 via grounding conductive patterns 18 and 19. Elements 12 and 13 are arranged.

上記構成において、高周波増幅素子12の
FETはアース端子が確実に接地されると共にそ
のリード間又は他の導電体との間に生ずるストレ
ー容量が極めて小さくでき入出力間の不要な結合
又は帰還を防ぐ。従つて、AGC動作における利
得の満足な減衰特性を得ることができる。すなわ
ち、本来アースすべき部分が高周波的にも完全に
アースされ出力側から入力側への帰還、又は入力
側から出力側への不所望な結合が除去されキンク
バツクの小さなUHF帯用高周波回路が提供でき
る。
In the above configuration, the high frequency amplifying element 12
The FET's ground terminal is reliably grounded, and the stray capacitance that occurs between its leads or with other conductors is extremely small, thereby preventing unnecessary coupling or feedback between input and output. Therefore, it is possible to obtain satisfactory gain attenuation characteristics in AGC operation. In other words, the part that should originally be grounded is completely grounded in terms of high frequency, and feedback from the output side to the input side or undesired coupling from the input side to the output side is eliminated, providing a high frequency circuit for the UHF band with small kink back. can.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案に係る高周波増幅回路の要部部
分断面図、第2図は第1図の回路素子を除いた状
態の平面図である。 3……区画室、8〜10……仕切板、11……
絶縁基板、12,13……回路素子、18,19
……導電パターン、20……半田。
FIG. 1 is a partial cross-sectional view of a main part of a high-frequency amplifier circuit according to the present invention, and FIG. 2 is a plan view of the circuit with the circuit elements shown in FIG. 1 removed. 3... Compartment room, 8-10... Partition plate, 11...
Insulating substrate, 12, 13...Circuit element, 18, 19
...Conductive pattern, 20...Solder.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 絶縁基板に回路素子をプリント配線し仕切板を
配設してシールド区画したチユーナにおいて、
UHF帯回路のうち少なくともRF増幅又は減衰用
回路素子が配置される前記絶縁基板の対応位置の
表裏両面部分にこの部分の略全体を覆う導電パタ
ーン形成し、このパターンを前記シールド区画の
仕切板に接続して接地したことを特徴とする高周
波回路装置。
In a tuner where circuit elements are printed on an insulating board and partitioned into shield sections by arranging partition plates,
A conductive pattern covering almost the entire area is formed on both the front and back surfaces of the insulating substrate at the corresponding position where at least the RF amplification or attenuation circuit element of the UHF band circuit is arranged, and this pattern is applied to the partition plate of the shield section. A high frequency circuit device characterized by being connected and grounded.
JP1100879U 1979-01-30 1979-01-30 Expired JPS6121880Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1100879U JPS6121880Y2 (en) 1979-01-30 1979-01-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1100879U JPS6121880Y2 (en) 1979-01-30 1979-01-30

Publications (2)

Publication Number Publication Date
JPS55109958U JPS55109958U (en) 1980-08-01
JPS6121880Y2 true JPS6121880Y2 (en) 1986-07-01

Family

ID=28824641

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1100879U Expired JPS6121880Y2 (en) 1979-01-30 1979-01-30

Country Status (1)

Country Link
JP (1) JPS6121880Y2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6320157Y2 (en) * 1981-05-29 1988-06-03
JPS58133988U (en) * 1982-03-01 1983-09-09 ミツミ電機株式会社 composite circuit device
JP7207801B1 (en) * 2021-09-16 2023-01-18 イメージニクス株式会社 Signal processor and support plate
JP7112785B1 (en) * 2021-09-16 2022-08-04 イメージニクス株式会社 signal processor

Also Published As

Publication number Publication date
JPS55109958U (en) 1980-08-01

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