JPS61218224A - Frequency divider circuit - Google Patents

Abstract

PURPOSE:To improve a high frequency characteristic by making a bias voltage of a D-FET at the input side identical. CONSTITUTION:D-FETs 22-24 and 28-30 constitute NOR gates 31, 33, D-FETs 25-27 constitute an OR gate 32 and D-FETs 24, 26, 30 are active load resistors. Through the constitution above, since input terminals (a, b) and (c, d) are connected in parallel, an equal input characteristic is obtained and since no element forming a feedback resistor at the source side exists, the high frequency characteristic is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement of a frequency divider circuit for a synthesizer used, for example, in a several GHz band.

For example, when a receiver with an intermediate frequency of 140 MHz receives waves between frequencies 5 and 5.5 GH2O, the oscillation frequency of the receiving local oscillator needs to vary between 4.86 and 5.36 GHz, and these The frequency stability of the waves must be high. In such cases, a synthesizer is often used that can synthesize and output the required frequency by dividing and multiplying the output of a highly accurate reference crystal oscillator.

FIG. 3 is a block diagram of a 2-frequency divider composed of master-slave type D-FFs, and FIG. 4 is a time chart of FIG. 3. Note that the numbers in FIG. 4 indicate the waveforms of the corresponding portions in FIG. 3.

Therefore, the operation shown in FIG. 3 will be explained with reference to FIG. 4.

In Fig. 3, the signal shown in Fig. 4-■ applied to the terminal IN passes through a D-type flip-flop (hereinafter abbreviated as D-FF) 1 and is divided into two as shown in Fig. 4-■. The resulting signal is taken out to the terminal of D-FF2.

On the other hand, a signal with a phase difference of 180 degrees from that in Figure 4-■ is applied to the terminal CK of this D-FP 2 as shown in Figure 4-■, so a signal as shown in Figure 4-■ is applied from the terminal OUT. A 2-frequency wave is obtained.

Here, 3 indicates an inversion gate.

When such a frequency divider by two is used in the above-mentioned synthesizer, a frequency divider with fewer restrictions on operating conditions is desired.

[Conventional technology]

FIG. 5 shows a circuit diagram of a conventional example of the D-FF shown in FIG.

As shown in the figure, the D-FF is a combination of two components 12 each consisting of AND gates 4 and 6 and a NOR gate 5.

FIG. 6 shows a truth diagram of the circuit diagram shown in FIG.

As shown in the figure, when the terminal CK is 1, the same value as D is the terminal Q
However, when J is 0, the value of D when CK is 1 is held and output from terminal Q.

Note that Qn-1 indicates the previous state.

FIG. 7 shows a circuit diagram when the component 12 shown in FIG. 5 is constructed as a depletion type Shosotky barrier field effect transistor (hereinafter abbreviated as D-PET) on a GaAs substrate.

As shown in the figure, D-FETs 7 and 8 and D-FETs 9 and 1
0 and the AND gates 4 and 6, and the NOR gate 5 is formed at the part where the drains of the D-FETs 8 and 9 are connected in common, +VDD and -Vss are respectively the power supply voltages, 11 is the load resistance, and the terminals a% d When the logic at and

In the figure, D-FETs 7 and 8 and D-FETs 9 and 10
are connected in series, so for example, when both terminals a and b are at Ov, drain current flows through D-FETs 7 and 8 and D
The drain voltage of -FET7 is supposed to be -Vss, but in reality it is -Vs because the internal resistance of D-FET8 is not 0.
The value is biased toward the + side of s, which differs from the design value.

Therefore, in order to set the drain voltage of the D-FET 7 to -Vss, the voltage at point a must be set to, for example, +0.5V instead of Ov, so a level shift circuit must be added to terminals a and b.

[Problem that the invention seeks to solve]

As explained above, since different bias voltages must be applied to terminals a and b, operating conditions are restricted and the degree of freedom in circuit design is restricted.

Furthermore, by adding a level shift circuit, there are two problems: high frequency characteristics are degraded due to actance components generated in this circuit in a high frequency band.

(Means for solving the problem) The above problem is solved by using a D-FF as a first and a second NOR gate, and a first OR gate that takes the OR of the outputs of the first and second NOR gates. and the outputs of the OR gates of the second component, which are the same as the first component, are added to the second NOR gates of the second and first components, respectively, and the outputs of the OR gates of the second NOR gates of the second and first components are Add a clock to one side,
A first NOR gate of the first component is configured to receive an inverted signal and a clock, and a first NOR gate of the second component is configured to receive an inverted clock and a non-inverted signal. , a NOR gate having a configuration in which the first and second sources and drains of two PETs are connected in parallel and a load resistor is connected to the drains, and the third and fourth sources and drains of two FETs are connected in parallel, respectively. This problem is solved by the frequency dividing circuit of the present invention configured using OR gates connected in parallel and having a load resistor connected to the source.

[Effect]

In the present invention, by configuring the logic gates constituting the D-PF with OR gates and NOR gates, the D-FF can be configured with all D-FETs connected in parallel.

Conventionally, the input section was composed of D-FETs connected in series, which required different bias voltages and deteriorated high frequency characteristics. However, in the present invention, since the input section is composed of D-PETs connected in parallel, a level shift circuit is not required and the same bias voltage can be applied.

Therefore, constraints on operating conditions are improved, the degree of freedom in design is expanded, and high frequency characteristics are improved.

〔Example〕

The contents of the present invention will be specifically explained below with reference to illustrated embodiments. Note that the same reference numerals indicate the same objects throughout the figures.

FIG. 2 shows a D-FF circuit diagram of an embodiment of the present invention.

As shown in the figure, D-FF has Noah gates 14 to 17. It is composed of OR games H8, 19 and inverting gates 20, 21, and its operation is the same as that in the truth diagram of FIG.

That is, (1) When CK is 1, the terminal C of the agate 15 among the components surrounded by the dotted line
becomes 1, so the terminal ``of the NOR gate 15 becomes O, which inquires about the terminal d. Therefore, the output Q of the OR gate 18 becomes
is in the same state as terminal e.

On the other hand, since the terminal of the NOR gate 14 is 0, if the terminal is O, the terminal e outputs 0, and if it is 1, the terminal e outputs 1.
The output Q of the OR gate 18 changes in the same state as the terminal.

Similarly, for the NOR gates 16 and 17 and the OR gate 19, the output Q of the OR gate 19 is the inverted state of D.

(When 21CK is 0, the terminals of the NOR gates 14 and 17 become 1 due to the inversion gate 20, so the terminal e of the OR gate 18.19 becomes 0, regardless of the terminal a of the NOR gates 14 and 17.
Q and Q are in the same state as the terminals of OR gates 18 and 19.

On the other hand, the terminals C of the NOR gates 15 and 16 become 0, and the terminals f of the OR gates 18 and 19 become 0.
This is the inverted state of terminal d.

Therefore, an R5-FF is configured by the NOR gates 15 and 16, and if Q is 1 when CK=1, that state is maintained regardless of the value of D.

As a result, the circuit shown in FIG. 2 satisfies the truth diagram shown in FIG. 6.

FIG. 1 shows a circuit diagram of an embodiment of the present invention.

The figure shows a circuit diagram when the components indicated by dotted lines in Fig. 2 are composed of D-FETs, and D-FETs 22 to 24
and 28-30, Noah gates 31 and 33, D-FE
O at T25-27.

Consists of Agate 32, D-FET 24.26.30
is the active load resistance.

With this configuration, the input terminals a and b and C and d are all parallel, so they have equal input characteristics, and since there is no element that would act as a feedback resistance on the source side, high frequency characteristics are also improved.

〔Effect of the invention〕

As explained in detail above, the present invention provides D −
Since the bias voltages of the FETs are now the same, restrictions on operating conditions are improved, the degree of freedom in pattern design is increased, and high frequency characteristics are improved.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a D-FF circuit diagram of an embodiment of the invention, Fig. 3 is a block diagram of a frequency divider by 2, and Fig. 4 is a diagram of a D-FF circuit diagram of an embodiment of the invention. Fig. 5 is a circuit diagram of a conventional D-FF example, Fig. 6 is a truth diagram of a D-FF, and Fig. 7 is a D-FF circuit diagram in which the components shown in Fig. 5 are mounted on a GaAs substrate.
- Shows a circuit diagram when configured with FETs. In the figure, 22 to 30 are D-PET. 3L 33 indicates Noah Gate, 32 indicates Or Gate. yF+ concave, v-3 criminal spear 4 figure

Claims (1)

[Claims] When a D-type flip-flop is constructed of field effect transistors on a semiconductor substrate, the D-type flip-flop is
first and second NOR gates configured such that the first and second sources and drains of the two field effect transistors are connected in parallel, and a load resistor is connected to the drains; A first component constituted by an OR gate that takes the OR of the outputs of the first and second NOR gates in a configuration in which the sources and drains of the third and fourth sources are connected in parallel, and a load resistor is connected to the sources. and the output of the OR gate of the second component, which is the same as the first component, is applied to the second NOR gate of the second and first components, respectively, and the output of the OR gate of the second NOR gate, which is the same as the first component, is applied to the second NOR gate of the second component and the output of the OR gate of the second component, respectively, and the is added, and the first component of the first component is
The inverted signal and clock are applied to the NOR gate of the second
A frequency dividing circuit characterized in that the frequency dividing circuit is configured such that an inverted clock and a non-inverted signal are applied to the first NOR gate of the component.