JPS6121608A - Print filter - Google Patents

Print filter

Info

Publication number
JPS6121608A
JPS6121608A JP59142724A JP14272484A JPS6121608A JP S6121608 A JPS6121608 A JP S6121608A JP 59142724 A JP59142724 A JP 59142724A JP 14272484 A JP14272484 A JP 14272484A JP S6121608 A JPS6121608 A JP S6121608A
Authority
JP
Japan
Prior art keywords
inductor
frequency
capacitor
circuit
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59142724A
Other languages
Japanese (ja)
Other versions
JPH0334684B2 (en
Inventor
Chihiro Kawaguchi
川口 千廣
Akira Onizuka
鬼塚 昌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP59142724A priority Critical patent/JPS6121608A/en
Publication of JPS6121608A publication Critical patent/JPS6121608A/en
Publication of JPH0334684B2 publication Critical patent/JPH0334684B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01Frequency selective two-port networks
    • H03H7/0115Frequency selective two-port networks comprising only inductors and capacitors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01Frequency selective two-port networks
    • H03H7/17Structural details of sub-circuits of frequency selective networks
    • H03H7/1708Comprising bridging elements, i.e. elements in a series path without own reference to ground and spanning branching nodes of another series path
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01Frequency selective two-port networks
    • H03H7/17Structural details of sub-circuits of frequency selective networks
    • H03H7/1741Comprising typical LC combinations, irrespective of presence and location of additional resistors
    • H03H7/1775Parallel LC in shunt or branch path
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01Frequency selective two-port networks
    • H03H7/17Structural details of sub-circuits of frequency selective networks
    • H03H7/1741Comprising typical LC combinations, irrespective of presence and location of additional resistors
    • H03H7/1783Combined LC in series path
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • H03H2001/0021Constructional details
    • H03H2001/0078Constructional details comprising spiral inductor on a substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Filters And Equalizers (AREA)

Abstract

PURPOSE:To realize desired characteristics by providing a tap to an inductor of one set of parallel resonance circuit inserted in series with an input/output terminal in an FM radio receiver and adopting simple circuit constitution where a capacitor is connected between the tap and ground to produce an attenuating poles at high frequencies. CONSTITUTION:The circuit is constituted by selecting values of an inductor L2 and capacitors C2, C4 so that the tap 5 is provided to the inductor L2 of the 2nd parallel resonance circuit inserted in series with the input/output terminal 1, the capacitor C4 is added between the tap 5 and ground 2, the 1st attenuation pole is produced in a frequency range of nearly 1.2 time to 1.6 time of the high frequency cut-off frequency f2 of pass band and the 2nd attenuation pole is produced in the frequency range of nearly 1.9 time to 3 times of the cut-off frequency f2, and the frequency band between the 1st attenuation pole and the 2nd attenuation pole is used as the pass band. The figure shows the circuit constituted by printing a circuit pattern comprising an inductor and capacitor to both sides of a dielectric board 8.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、F’Mラジオ受信機のアンテナとチューナと
の間に挿入するバンドパスフィルタに用いられるプリン
トフィルタに関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a printed filter used as a bandpass filter inserted between an antenna and a tuner of an F'M radio receiver.

従来例の構成とその問題点 アンテナとチューナの間に挿入するバンドパスフィルタ
の要求特性は、通過帯域で使用される周波数の約2倍の
周波数領域で、減衰量が20〜30dB程度必要とされ
る。たとえは、使用される周波数が76 MHz 〜1
08 MHzであれは、高域側の要求される減衰量は、
約150屍七へ一230旙tの周波数領域で20〜30
dB程度である。したかって、フィルタとしては高域側
に減衰極があって、高域(1411力ツトオフ周波数f
2以上の減衰部の傾斜か、負をも′のが良い。
Conventional configuration and its problems The required characteristics of the bandpass filter inserted between the antenna and the tuner are that the attenuation should be about 20 to 30 dB in a frequency region that is approximately twice the frequency used in the passband. Ru. For example, if the frequency used is 76 MHz ~ 1
At 0.08 MHz, the required attenuation amount on the high frequency side is
Approximately 150 corpses - 20-30 in the frequency range of 230 pm
It is about dB. Therefore, as a filter, there is an attenuation pole on the high frequency side, and the high frequency (1411 power cut-off frequency f
It is preferable that the slope of two or more damping parts is negative.

そこで、部品点数が少なく高域1111に減衰極がある
ハンドハスフィルタに、第4図に示す回路がある。第4
図において、1は入力端子、2はアース端子、3は出力
端子である。Ll(I′iインダクタ、C1はコンデン
サで第1の並列共振回路を構成している。L2はインダ
クタ、C2はコンデンサで第2の並列共振回路を構成し
ている。 C3はコンデンサである。
Therefore, a circuit shown in FIG. 4 is available as a hand-held filter with a small number of parts and an attenuation pole in the high frequency range 1111. Fourth
In the figure, 1 is an input terminal, 2 is a ground terminal, and 3 is an output terminal. Ll(I'i) is an inductor, C1 is a capacitor and constitutes a first parallel resonant circuit. L2 is an inductor, and C2 is a capacitor and constitutes a second parallel resonant circuit. C3 is a capacitor.

第5図は、第4図の出力特性を示した特性曲線図である
。flは低域側カットオフ周波数、fl1は使用される
下限の周波数、fl2 は使用される上限の周波数、f
2は高域側カットオフ周波数、f3は高域側減衰極の周
波数を示しである。この特性は、高域側の2f′1(下
限使用周波数f′1の2倍の周波数)から2f′2(上
限使用周波数f′2の2倍の周波数〕の周波数範囲で減
衰量が少なく、2f′2の周波数になるにつれ減衰量が
10〜16dB程度になり、上述の要求特性を満足する
ことができない。
FIG. 5 is a characteristic curve diagram showing the output characteristics of FIG. 4. fl is the lower cutoff frequency, fl1 is the lower limit frequency used, fl2 is the upper limit frequency used, f
2 indicates the cutoff frequency on the high frequency side, and f3 indicates the frequency of the attenuation pole on the high frequency side. This characteristic has a small amount of attenuation in the frequency range from 2f'1 (twice the lower limit usable frequency f'1) to 2f'2 (twice the upper limit usable frequency f'2), As the frequency increases to 2f'2, the amount of attenuation increases to about 10 to 16 dB, making it impossible to satisfy the above-mentioned required characteristics.

特性を満足させるためには、バンドパスフィルタを複鞄
段縦続接続をすれば良いが、部品点数が大巾に多くなる
ので、価格が高くなると共に小形化かできないという問
題が生じる。
In order to satisfy the characteristics, bandpass filters may be connected in series in multiple stages, but this increases the number of parts, resulting in an increase in price and the problem that only miniaturization is possible.

発明の目的 本発明は簡単々回路にて前記問題点を触法することを目
的とする。
OBJECTS OF THE INVENTION It is an object of the present invention to overcome the above-mentioned problems with a simple circuit.

発明の構成 本発明は、前記目的達成の為、誘電体基板上に入力端子
、出力端子、アース端子を設け、前記入力端子と並列に
第1のインダクタと第1のコンデンサからなる第1の並
列共振回路を被着形成し、入力端子と直列に第2のイン
ダクタと第2のコンデンサからなる第2の並列共振回路
を一組被着形成し、前記第2のインダクタは線条のパタ
ーンをヘリカル状に巻かれてなり、該インダクタのパタ
ーンの一部と対向して斜めに重合する線条のアースパタ
ーンを設け、該線条のアースパターンの静電結合によっ
て、前記第2のインダクタとアース端子間にコンデンサ
を形成して成るものである。
Structure of the Invention In order to achieve the above-mentioned object, the present invention provides an input terminal, an output terminal, and a ground terminal on a dielectric substrate, and provides a first parallel connection consisting of a first inductor and a first capacitor in parallel with the input terminal. A resonant circuit is deposited, and a second parallel resonant circuit consisting of a second inductor and a second capacitor is deposited in series with the input terminal, and the second inductor has a linear pattern formed in a helical manner. A wire ground pattern is provided which is wound into a shape and overlaps diagonally with a part of the inductor pattern, and the second inductor and the ground terminal are connected by capacitive coupling of the wire ground pattern. A capacitor is formed between them.

実施例の説明 以下第1図〜第3図を参照して本発明の一実施例を1i
51!1」jする。
DESCRIPTION OF THE EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.
51!1"j.

第1図は本発明一実施例のプリントフィルタの回路図で
あし、本回路は、従来例で示した第4図回路中の入出力
端子1に直列に挿入された第2の並列共振回路のインダ
クタL2にタップ5を設けこのタップ5とアース2間に
コンデンサC4を付加して、通過帯域の高域側カットオ
フ周波数f2の約1.2倍から1.6倍程度の周波数範
囲に第1の減衰極を、更に、カットオン周波数f2の約
1.9倍から3倍程度の周波数範囲に第2の減衰極か生
じるように、インタクタL2.コンデンサc2.c4の
値を選択して構成し、第1の減衰極と第2の減衰量を2
0〜35d13にすることができるものである。
Fig. 1 is a circuit diagram of a printed filter according to an embodiment of the present invention, and this circuit consists of a second parallel resonant circuit inserted in series with the input/output terminal 1 in the circuit of Fig. 4 shown in the conventional example. A tap 5 is provided in the inductor L2, and a capacitor C4 is added between the tap 5 and the ground 2, and a first inductor is provided in the frequency range of about 1.2 to 1.6 times the high-side cutoff frequency f2 of the passband. The intactor L2. Capacitor c2. Select and configure the value of c4 to set the first attenuation pole and the second attenuation to 2
It can be set to 0 to 35d13.

但し2f′1は、下限使用周波数f′1 02倍の周波
数で、2J/?は上限使用周波数f/2の2倍の周波数
を示している。
However, 2f'1 is a frequency that is 02 times the lower limit usable frequency f'1, which is 2J/? indicates a frequency twice the upper limit usable frequency f/2.

以後、fl、f2. fl1.f’2の前に添付された
数字はfl、f2.fl1.fl2  の何倍であるか
を表すものとする。
From then on, fl, f2. fl1. The numbers attached before f'2 are fl, f2. fl1. Let it represent how many times fl2 it is.

以下、破線にて囲んだ枠4内の回路について詳細に説明
する。第1図のL3.L4.c4をY−Δ変換して6−
7間の直列アームのインピーダンス2を求めると と表わすことができる。
Hereinafter, the circuit within the frame 4 surrounded by the broken line will be described in detail. L3 in Figure 1. L4. Y-Δ conversion of c4 to 6-
The impedance 2 of the series arm between 7 and 7 can be expressed as follows.

減衰極はインピータンス2が最大になる周波数で生じる
のであるから、この周波数を求めると1  ro2C4
C2Σ=。
Since the attenuation pole occurs at the frequency where impedance 2 is maximum, finding this frequency is 1 ro2C4
C2Σ=.

よシ となる。f4 は第1の減衰極を生じる周波数で、f5
は第2の減衰極を生じる周波数である。
It becomes good. f4 is the frequency that produces the first attenuation pole, and f5
is the frequency that produces the second attenuation pole.

そこで、所望の特性を得るために、周波数fが約12f
2〜1.6f2程度の周波数範囲に、丑だ、周波数f5
を杓1.9J’2〜3f2程度の周波数範囲になるよう
に、コンデンサc4.c2の値を02〉q(L3−L4
の場合)の条件で選択する。そして、心安に応じてイン
ダクタL3.L4を調整すると良いO 第1の減衰極と第2の減衰極の間は阻止帯域になるのて
、その帯域中をせ1くすると減衰量は多くなる。たとえ
は、通過帯域の周波数が70〜12014(z程度のフ
ィルタであれは、周波数f4は140〜1’90MHz
程度に、周波数f5を230〜350 MHz程度に設
定すると、f4とf5の間が阻止帯域となり第2図に示
す出力特性が実現でき、上述の要求特性を満足すること
かできる。
Therefore, in order to obtain the desired characteristics, the frequency f should be approximately 12f.
In the frequency range of about 2 to 1.6 f2, the frequency f5
The capacitor c4. The value of c2 is 02〉q(L3-L4
). Then, depending on your peace of mind, inductor L3. It is a good idea to adjust L4. The area between the first attenuation pole and the second attenuation pole forms a stop band, so if the band is narrowed to 1, the amount of attenuation will increase. For example, if the passband frequency is 70 to 12014 (about z), the frequency f4 is 140 to 1'90 MHz.
If the frequency f5 is set to about 230 to 350 MHz, a stop band will be formed between f4 and f5, and the output characteristics shown in FIG. 2 can be realized, thereby satisfying the above-mentioned required characteristics.

次に、第1図の回路を平面回路で構成することを考える
と、コンデンサC4は等測的に構成できる。平面回路の
構成を第3図に平面図で示した。
Next, considering that the circuit of FIG. 1 is constructed as a planar circuit, the capacitor C4 can be constructed isometrically. The configuration of the planar circuit is shown in a plan view in FIG.

第3図は、誘電体基板8の両面にインダクタやコンデン
サ等の回路パターンを被着形成して構成されている。
In FIG. 3, circuit patterns such as inductors and capacitors are formed on both sides of a dielectric substrate 8.

第3図の実線は、誘電体基板8のA面側に、点線は3面
側に被着形成した回路パターンを示しである。
The solid line in FIG. 3 shows the circuit pattern formed on the A side of the dielectric substrate 8, and the dotted line shows the circuit pattern formed on the third side.

第3図の9は第1図の端子1のパターンで、第3図の1
0は第1図の端子2のパターンTある。
9 in Figure 3 is the pattern of terminal 1 in Figure 1;
0 is pattern T of terminal 2 in FIG.

第3図の11.12はインダクタL1を形成するコイル
パターンでスルーホール13に、l:っテ、11と12
か接続されている。第1図のコンデンサC1は、王にパ
ターン9.10の対向部で形成きれている。
11.12 in Fig. 3 is the coil pattern forming the inductor L1, and it is connected to the through hole 13, l:tte, 11 and 12.
or connected. The capacitor C1 in FIG. 1 is formed entirely by the opposite portion of the pattern 9.10.

第1図のインダクタL3は、第3図のコイルパターン1
4に略相当し、第1図のインダクタL4は第5図のコイ
ルパターン15に略相癌している。
The inductor L3 in FIG. 1 is the coil pattern 1 in FIG.
4, and the inductor L4 in FIG. 1 is substantially in phase with the coil pattern 15 in FIG.

14.15はスルーホール18で接続きれていも第1図
のコンデンサC2は01の値に比較して小さな容量値で
あるために、主にコイルパターン14゜15の対向部分
で等測的に形成されている。
Even though 14.15 can be connected through the through hole 18, the capacitor C2 in Fig. 1 has a small capacitance value compared to the value of 01, so it is mainly formed isometrically at the opposing portions of the coil patterns 14 and 15. has been done.

コイルパターン14.j5の一部か斜めに対向している
のは、コンデンサC2,インダクタL3.L4の値を調
整するためである。(静電的、磁気的結合を′A整する
。) 第1図のタッグ5は、第3図の19に略相幽している。
Coil pattern 14. Parts of j5 are diagonally opposed to capacitor C2, inductor L3. This is to adjust the value of L4. (Adjust the electrostatic and magnetic coupling.) The tag 5 in FIG. 1 is approximately parallel to the tag 19 in FIG. 3.

第1図のコンデンサC4は、第3図の・・ターン19と
線条のアースパターン2Qの対向部分と、パターン20
の静電結合によって等測的に形成されている。パターン
20及び対向しているパターンが斜めになっているのは
、タッグ5に相轟する位置とパターン2Qの長さを調整
して、静電結合の値を設定するだめである。
The capacitor C4 in FIG.
is formed isometrically by the electrostatic coupling of . The reason why the pattern 20 and the opposing pattern are oblique is that the value of capacitive coupling can be set by adjusting the position where the pattern 20 resonates with the tag 5 and the length of the pattern 2Q.

第3図の16は第1図の出力端子3のパターンである。Reference numeral 16 in FIG. 3 is the pattern of the output terminal 3 in FIG.

コンデンサC3はパターン16.17の対向部分で形成
きれている。
Capacitor C3 is completely formed in the opposing portions of patterns 16 and 17.

このように、第1図の回路は容易に平面回路で構成でき
る利点かある。
As described above, the circuit shown in FIG. 1 has the advantage that it can be easily constructed as a planar circuit.

発明の詳細 な説明したように、入出力端子に直列に挿入された一組
の並列共振回路のインダクタにタップを設け、コンデン
サをタップとアースm1に接続した簡単な回路構成で、
高域fllに二つの減衰極を生じさせることかできる。
As described in detail, the invention has a simple circuit configuration in which a tap is provided to the inductor of a set of parallel resonant circuits inserted in series to the input/output terminals, and a capacitor is connected to the tap and the ground m1.
It is possible to generate two attenuation poles in the high frequency band.

この二つの減衰極間が阻止帯域となシ、所望の特性を実
現することができるほか、付加したコンデンサの値は、
前記1組の並列共振回路を構成するコンデンサの容量に
比べ、小さくて良いから小形化には障害にならない。
Since the stopband is between these two attenuation poles, the desired characteristics can be achieved, and the value of the added capacitor is
Since the capacitance may be smaller than the capacitance of the capacitor constituting the pair of parallel resonant circuits, it does not pose an obstacle to miniaturization.

しかも、平面回路で実現すれはタップとアース間に接続
されたコンデンサは等価回路で構成できるので、見かけ
上部品点数の増加にならない利点がある。
In addition, since the capacitor connected between the tap and the ground can be constructed using an equivalent circuit when realized using a planar circuit, there is an advantage that the number of parts does not appear to increase.

才だ、回路パターンの対向部分のパターンを斜めにする
ことで、簡単に静電的、あるいは磁気的な結合状態を変
えることができ、回路定数が容易に実現できる利点もあ
る。
By slanting the opposing parts of the circuit pattern, the electrostatic or magnetic coupling state can be easily changed, and the circuit constants can be easily realized.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す回路図、第2図は第1
図の出力特性図、第3図は第1図を平面回路で実流しだ
パターン図、第4図は従来のバンドバスンイルタの回路
図、第5図は第4図の出力特性図である。 1・・・・・入出力端子、2・・・・アース、5・・ 
タップ、8・・・・誘電体基板、9・・・・・入出力端
子パターン、1o゛・・・アース端子パターン、11.
12゜14.16・・・ コイルパターン、13.18
・・・スルーホール、16・川・・出力端子パターy。
Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
Figure 3 is a pattern diagram obtained by actually applying Figure 1 to a planar circuit, Figure 4 is a circuit diagram of a conventional bandpass filter, and Figure 5 is an output characteristic diagram of Figure 4. . 1...Input/output terminal, 2...Earth, 5...
Tap, 8...Dielectric substrate, 9...Input/output terminal pattern, 1o゛...Earth terminal pattern, 11.
12゜14.16... Coil pattern, 13.18
...Through hole, 16. River...Output terminal putter y.

Claims (1)

【特許請求の範囲】[Claims] 誘電体基板上に入力端子、出力端子、アース端子を設け
、前記入力端子と並列に第1のインダクタと第1のコン
デンサからなる第1の並列共振回路を被着形成し、入力
端子と直列に第2のインダクタと第2のコンデンサから
なる第2の並列共振回路を一組被着形成し、前記第2の
インダクタは線条のパターンをヘリカル状に巻かれてな
り、該インダクタのパターンの一部と対向して斜めに重
合する線条のアースパターンを設け、該線条のアースパ
ターンの静電結合によって、前記第2のインダクタとア
ース端子間にコンデンサを形成したことを特徴とするプ
リントフィルタ。
An input terminal, an output terminal, and a ground terminal are provided on a dielectric substrate, and a first parallel resonant circuit consisting of a first inductor and a first capacitor is deposited and formed in parallel with the input terminal, and in series with the input terminal. A second parallel resonant circuit including a second inductor and a second capacitor is formed by depositing a second parallel resonant circuit, the second inductor is formed by winding a filament pattern in a helical shape, and the second inductor has a linear pattern wound in a helical shape. A printed filter characterized in that a linear ground pattern is provided that faces the part and overlaps diagonally, and a capacitor is formed between the second inductor and the ground terminal by electrostatic coupling of the linear ground pattern. .
JP59142724A 1984-07-10 1984-07-10 Print filter Granted JPS6121608A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59142724A JPS6121608A (en) 1984-07-10 1984-07-10 Print filter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59142724A JPS6121608A (en) 1984-07-10 1984-07-10 Print filter

Publications (2)

Publication Number Publication Date
JPS6121608A true JPS6121608A (en) 1986-01-30
JPH0334684B2 JPH0334684B2 (en) 1991-05-23

Family

ID=15322105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59142724A Granted JPS6121608A (en) 1984-07-10 1984-07-10 Print filter

Country Status (1)

Country Link
JP (1) JPS6121608A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62128111A (en) * 1985-11-28 1987-06-10 株式会社村田製作所 Lc complex component
US5513875A (en) * 1991-09-09 1996-05-07 Hitachi Construction Machinery Co., Ltd. Lockable suspension system for a work vehicle having a stabilizing link
JPWO2018100918A1 (en) * 2016-12-04 2019-10-17 株式会社村田製作所 Multilayer LC filter

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62128111A (en) * 1985-11-28 1987-06-10 株式会社村田製作所 Lc complex component
JPH0450728B2 (en) * 1985-11-28 1992-08-17 Murata Manufacturing Co
US5513875A (en) * 1991-09-09 1996-05-07 Hitachi Construction Machinery Co., Ltd. Lockable suspension system for a work vehicle having a stabilizing link
JPWO2018100918A1 (en) * 2016-12-04 2019-10-17 株式会社村田製作所 Multilayer LC filter

Also Published As

Publication number Publication date
JPH0334684B2 (en) 1991-05-23

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