JPS61212121A - Digital multi-valued data transmission equipment - Google Patents

Abstract

PURPOSE:To decode exactly a multi-valued data even in case a signal level is varied, by providing a means for separating threshold data and a digital multi-valued data which are obtained by a digitizing means, and a means for storing a new threshold data which is obtained every prescribed period. CONSTITUTION:From a memory part 6, a data TH1 of a threshold '1' is supplied to a comparator 7a, a data TH2 of a threshold 2 is supplied to a comparator 7b, and a data TH3 of a threshold is supplied to a comparator 7c. By these three pieces of comparators 7a-7c, the respective thresholds and input data are compared, and as a result of their comparison, by decoding the obtained data of 3 bits by a decoder 7d, a data of 2 bits for realizing a quadruple value is obtained. Three groups of data which are obtained from the comparing circuit are inputted to a majority circuit 10, and the data of the most value is outputted. The data of 2 bits outputted from the majority circuit concerned is supplied to a 2 8 converting part.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to high-density recording of information on a recording medium such as a magnetic tape or an optical disk using digital multi-value data, and when using digital multi-value data The present invention relates to a digital multilevel data transmission device that is applied when transmitting information at a high transmission speed.

[Summary of the invention]

The present invention provides a digital multi-value data transmission device in which a threshold signal of a digital multi-value signal is added to the digital multi-value signal at regular intervals and transmitted, and a reproduction side obtains the threshold signal. Digital multi-value data is decoded based on threshold data.

[Conventional technology]

2. Description of the Related Art In recording or transmitting digital data, methods of using multi-value data have been known to increase recording density and transmission speed.

For example, 8-bit data is divided into 4 parts of 2 bits each, and each of these 2 bits is converted into digital multi-value data having one of the four levels of quantization level θ to 3, which is equivalent to binary data. The recording density can be doubled by recording in a time-width section, and the transmission speed can be doubled by transmitting the digital multilevel data at the same time intervals as binary data. Similarly, by dividing 8-bit data into two parts of 4 bits each, the recording density and transmission speed can be quadrupled. However, in this case, the recorded signal has 16 levels, making it difficult to determine the level during reproduction. Practically, it is appropriate for digital multi-value data to have up to about 8 values (3 bits).

As a device that uses such digital multi-value data,
The applicant has developed a digital signal recording device that first converts 8-bit data into 9-bit data, divides it into three parts of 3 bits each, converts each into an analog signal, and records it as an 8-value recording signal (Patent Application No. 107,980/1989). is proposed. In this apparatus, the 8-value recording signal is further converted into a video signal and recorded on a video track of a magnetic tape using a VTR or the like.

Incidentally, in order to decode multi-value data, a plurality of multi-value level thresholds are required. For example, 2-bit multi-value data requires 3 thresholds, and 3-bit multi-value data requires 7 thresholds.
requires several thresholds. Bucoding is performed by comparing this threshold value with multivalued data.

Generally, in this type of device, the transmission level of the multilevel data signal is defined, and the threshold value is also determined accordingly.

This threshold is constant.

[Problem that the invention seeks to solve]

The level of the transmitted multilevel data signal can be varied by passing it through a circuit system such as a VTR (for example, by passing it through a circuit system such as a VTR) or by passing it through a transmission line.

In conventional transmission devices of this kind, the threshold value is fixed, so that if data is decoded from a signal that has undergone fluctuations based on this threshold value, there is a problem that data errors occur during decoding.

For example, as shown in Figure 7A, if an 8-value signal with levels from 0 to 7 is sent out, and the linearity of the circuit system that passes this signal is poor, the 8-value signal as shown in Figure 7B will appear. The step height of the signal changes.

Since the threshold indicated by the dotted line in the one-way diagram is constant, if the step height of the signal is too small or too large compared to the threshold interval, an error will occur in the decoded data. In the figure, underlined numbers indicate erroneous decoding. Furthermore, even if the step height of the signal is constant, even in the case of C in the same figure where the overall level is small, the threshold value is constant, so
Errors occur in the decoded data.

The present invention has been made in view of these problems, and provides digital multi-value data transmission that allows multi-value data to be correctly decoded even when the signal level fluctuates due to the characteristics of the recording system, transmission path, etc. The purpose is to provide equipment.

[Means for solving problems]

In order to achieve the above-mentioned object, the present invention includes means for adding a threshold signal of the digital multi-level signal to the digital multi-level signal at regular intervals and transmitting the signal. Further, means for digitizing the signal sent out by the means, means for separating the threshold data and digital multi-value data obtained by the digitizing means, and a new threshold obtained at each fixed period. The device includes means for storing value data, and means for decoding the digital multi-value data into binary digital data based on the stored threshold data.

[Effect]

In the present invention, the signal sent out by the sending means is digitized by the digitizing means and separated into threshold data and digital multi-value data by the separating means. The threshold data obtained at each fixed period is stored by the storage means, and the decoding means compares the stored threshold data with the digital multi-value data. Value data is decoded into binary digital data.

〔Example〕

Hereinafter, a transmission apparatus according to the present invention will be described with reference to the drawings, in which a large number of people simultaneously input Japanese language, convert it into digital multi-value data, and record it on a video track of a videotape using a VTR.

FIG. 2 is a block diagram showing the configuration of the recording system of this embodiment. In the figure, multiplexer 21 has 22 channels of input. Therefore, this device can record up to 22 Japanese languages at the same time.

The multiplexer 21 is an input channel CHI.

CH2...Audio signals input to CH22 are multiplexed in time series and sent to the A/D converter 22. The Φ converter 22 converts the multiplexed audio signal into 8-bit digital data and outputs it to the encoder section 23. This encoder section 23 uses a buffer memory or the like to change the sending order of input 8-bit data according to a fixed rule. By performing this processing, even if data errors occur in temporally concentrated areas due to burst noise, for example, these data errors will be dispersed to some extent when the playback side restores the original transmission order. In the transmission of image data, audiovisual noise can be effectively suppressed.

The output of the encoder section 23 is input to an 8->2 conversion section 24 which divides the 8-pit data into four parts of 2 bits each. The output of the converter 24 is output to a mixing circuit 25 in 2-bit units. ``This mixing circuit 25 converts the input 2 bits into 3 bits and adds a data header at regular intervals. Here, the constant period is set to the horizontal synchronization period of the television. In addition, in one of the horizontal synchronization periods, threshold data of levels 11, 3, and 5 are inserted as thresholds out of the 8-value levels that can be realized with 3-bit data at a cycle corresponding to the vertical synchronization period. . Regarding the relationship between this 3-bit data and threshold data, the third
It is shown in the figure. Originally, 0 to 3 can be expressed with 2 bits.
As shown in the figure, the 3-bit data corresponds to the four values 000, 010, 100°110 in binary. On the other hand, the threshold value data is 001.011 in binary.

Three values, 101, are set.

The 3-bit data output from the mixing circuit 25 is D/
After being converted into analog data by the A converter 26, the signal is input to the video signal converter 27. This video signal converter 27 adds horizontal and vertical synchronization signals to the input analog signal, converts it into a video signal, and then transfers this video signal to the VTR 2.
Output to 8.

The waveform of the video signal is as shown in FIG. 4, for example. In the figure, horizontal synchronization period a is the first horizontal synchronization period immediately after the vertical synchronization signal, and threshold data is inserted in this period. After the horizontal synchronization period, 4-valued data is inserted. Also, a data header is added to the beginning of each horizontal synchronization period to indicate that data will follow.

The video signal is recorded on a video tape by the VTR 28. In the recording system of this embodiment, the multivalued audio data is recorded on the video track of the videotape.

Next, the reproduction system of the apparatus of this embodiment will be explained based on the block diagram of the reproduction system shown in FIG. In the same figure, the above V
The video signal output from TR2B is first input to the decoding processing section 50. The decoding processing unit 50 is an A/D transformer 5
A control unit 50bst that detects a synchronization signal etc. from the 0a1 video signal and controls the memory etc., a decoding circuit unit 5oc that decodes multi-valued audio data into binary data based on threshold data and outputs it in 2-bit parallel form. It is composed of etc. The detailed configuration and operation of the decoding processing section 5o will be described later.

The 2-bit parallel data output from the decoding processing section 50 is converted into 8-bit parallel data in the 2→8 conversion section 51. The 8-bit data strings output multiple times by the 2→8 converter 51 are obtained by changing the sending order according to a certain rule in the above-mentioned recording system. This data string is converted to the original order in the decoder section 52 and input to the channel selection circuit 53. Data of one channel out of the above-mentioned 22 channels is outputted to the D/A converter 54 by selection in the channel selection circuit 53 . The D/A converter 5
The audio signal output from 4 is output to the speaker 56 via the amplifier 55, and the audio is reproduced.

Next, the configuration and operation of the decoding processing section 50 will be explained in detail. FIG. 1 is a block diagram showing a detailed configuration of the decoding processing section 50, and an input terminal 1 is supplied with a video signal from the VTR 28. This video signal is converted into 8-bit digital data by the A/D converter 50a. Further, a synchronization circuit 2 detects vertical and horizontal synchronization signals from the video signal, and these synchronization signals are supplied to a control circuit 4, and a header separation circuit 3 detects a data header from the video signal. A signal is supplied to the control circuit 4. The control circuit 4 controls the switch 5 and the memory section 6 based on the vertical and horizontal synchronization signals and the header detection signal. That is, during the first horizontal synchronization period immediately after the vertical synchronization signal, the switch 5 is connected to the memory section 6 side, and at the same time, the memory section 6 is controlled to adjust the threshold value inserted in this first horizontal synchronization period. Store data. Three pieces of threshold data are stored for each threshold value. That is, three pieces of data for threshold 1, three pieces of data for threshold 2, and three pieces of data for threshold 3 are stored. This process is performed for each vertical synchronization signal.

After the vertical synchronization signal, from the second horizontal synchronization period until the next vertical synchronization signal, the switch 5 is connected to the comparator circuits 7, 8, and 9 having the same configuration. This comparison circuit 7 consists of three 8
Bit comparator 7aj7b17c and 3 bits 2
A decoder 7d decodes into bits, and data obtained by digitizing a four-level signal is inputted to these comparators 7"+7b and 7c via the switch 5.

Further, data THI of threshold value 1 is supplied from the memory section 6 to the comparator 7a, and the comparator 7a is supplied with data THI of threshold value 1.
Data TH2 of threshold value 2 is supplied to b, and data TH3 of threshold value 3 is supplied to the comparator 7C. These three comparators 7a, γb, and γC compare their respective thresholds with the input data, and the 3-bit data written as a result of these comparisons is decoded by the decoder 7d, thereby realizing 4 values. Get bit data.

As mentioned above, since the memory section 6 stores three pieces of data for each threshold value, three comparison circuits are used to obtain three sets of 2-bit data. These three sets of data are input to the majority circuit 10, and the data with the largest value is output. The majority circuit outputs 2
The bit data is supplied by the 2→8 conversion gate. This majority circuit can reduce the data error rate.

Furthermore, since the decoding processing section 50 stores threshold data for each vertical synchronization signal, when the video signal supplied to the input terminal 1 fluctuates, the threshold value also changes accordingly. The relative relationship between the threshold value and the signal remains constant.

Such an operation will be explained based on FIG. 6.

FIG. 6 shows the level for three bits of the video signal supplied to the input terminal 1 and the level for three bits of the threshold value.

First, under normal conditions, the signal (a) t
The D step height is constant, and the step height of the threshold value (b) is also constant. Assume that each threshold value fluctuates in the step height of the signal due to signal deterioration, etc., as shown in FIG. The memory section 6 stores threshold data for each vertical synchronization signal.

Therefore, the step height of the threshold level also changes as shown in (b), and each threshold is maintained at the center of the levels of the signal on both sides. Therefore, the above comparison circuit γ,8
, 9, etc. can decode multivalued data without errors.

Next, if the level of the video signal becomes small as shown in FIG. As shown in FIG. 3, each threshold value is kept at the center of the levels of the signals on both sides of the signal. Therefore, in this case as well, the comparator circuits 7°, 8.9, etc. can decode without error.

This decoding processing unit 50 performs decoding based on the threshold value that changes according to the fluctuation of the input signal, and also employs the majority circuit 10 described above, so that the decoding error rate at the time of decoding is suppressed as much as possible. be able to. Therefore, the apparatus of this embodiment can correctly decode multi-level data even if there is a level fluctuation in the video signal due to factors such as the characteristics of the circuit system of the VTR 2B, temperature changes, and the like.

As a result, the device of this embodiment is capable of recording the languages of up to 22 countries using the VTR 28 and then selecting and reproducing the language of a specific country, which has a good S/N ratio. You can get a good playback sound.

Further, a transmission path may be used between the VTR 28 and the decoding processing section 50 or between the VTR 28 and the video signal converting section 27. In this case, even if the signal fluctuates due to the characteristics of the transmission path, the multilevel data can be correctly decoded without being affected by the fluctuation, and reproduced sound with a good S/N ratio can be obtained.

Furthermore, even when a transmission device is configured by connecting a recording system and a reproduction system using a transmission line without going through the VTR 28, multilevel data can be correctly decoded and reproduced sound with a good S/N ratio can be obtained. I can do it. Such a device can be used, for example, at a multi-party conference, etc., by inputting the speaker's language into multiple input channels by interpreting it into the language of each country, and then selecting the language of a specific country on the playback side. It can be used for conference systems, etc.

〔Effect of the invention〕

As described above, the present invention obtains threshold data at regular intervals from a signal sent out by adding a threshold signal to a digital multi-level signal at regular intervals, and sets the threshold value. Decode digital multi-value data based on value data. At this time, if the level of the signal changes, the threshold data also changes accordingly, and the relative relationship between the signal and the threshold is kept constant, which prevents errors from occurring during decoding. . Therefore, even if the signal level varies depending on the characteristics of the circuit system, the characteristics of the transmission path, etc., digital multi-level data can be correctly decoded, and the intended purpose of the present invention can be achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a decoding processing unit which is a part of the reproduction system of an embodiment to which the digital multilevel data transmission device of the present invention is applied, and FIG. 2 is a block diagram of the recording system of the above embodiment. be. FIG. 3 is a correspondence diagram between data that can realize the four-value level used in the above embodiment and its threshold value.
FIG. 4 is a video signal waveform diagram output from the recording system. FIG. 5 is a block diagram of the reproduction system of the above embodiment. FIG. 6 is a diagram showing the correspondence between the input video signal level and the threshold value in the decoding processing section. FIG. 7 is a diagram showing the correspondence between a general 8-valued bell signal and a threshold value. 1... Input terminal 2... Synchronous circuit 3...
Header separation circuit 4... Control circuit 5... Switch 6... Memory section 7.8.9... Comparison circuit 10... Majority circuit 21... Multiplexer 22, 50 a-=A/D Converter 23...Encoder 24...8→2 conversion section 2
5...Mixing circuit 26.54...D/A converter 27...Video signal converter 28...VTR50.
...Decryption processing section 50b...Control section 50c...
Decode circuit patent applicant: Sony Corporation agent, patent attorney: Koike Mimuki, Tamura Sakae

Claims (1)

[Claims] means for adding a threshold signal of the digital multi-value signal to a digital multi-value signal at a constant period and transmitting the signal; means for digitizing the signal sent by the means; means for separating threshold data and digital multi-value data; means for storing new threshold data obtained at each predetermined cycle; A digital multi-value data transmission device comprising means for decoding multi-value data into binary digital data.