JPS61208247A - Flat pack ic - Google Patents

Flat pack ic

Info

Publication number
JPS61208247A
JPS61208247A JP4889885A JP4889885A JPS61208247A JP S61208247 A JPS61208247 A JP S61208247A JP 4889885 A JP4889885 A JP 4889885A JP 4889885 A JP4889885 A JP 4889885A JP S61208247 A JPS61208247 A JP S61208247A
Authority
JP
Japan
Prior art keywords
printed board
leads
positioning
flat pack
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4889885A
Other languages
Japanese (ja)
Inventor
Yoshihiro Sasaki
佐々木　吉弘
Zen Mizuno
水野　繕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4889885A priority Critical patent/JPS61208247A/en
Publication of JPS61208247A publication Critical patent/JPS61208247A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Abstract

PURPOSE:To conduct positioning positively by bending partial terminal leads at a right angle, projecting the terminal leads to sections lower than other terminal leads and fitting the partial terminal leads into positioning holes for a printed board. CONSTITUTION:Terminal leads 1a-1d positioned at the four corners of a flat pack IC main body 3 in a plurality of terminal leads 2 are used as leads for positioning the main body 3 on a printed board 4. Positioning holes 5..., which are arranged in electrode pads 4a... row soldering the leads 2 and into which the leads 1a-1d are fitted, are formed to the printed board 4. Consequently, when the leads 1a-1d for the main body 3 are inserted into the holes 5 for the printed board 4, the main body 3 is mounted onto the printed board 4. Accordingly, positioning is conducted positively.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、電子機器装置等に使用されるフラットパック
ＩＣの端子リードの形状に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the shape of a terminal lead of a flat pack IC used in an electronic device or the like.

〔従来の技術〕[Conventional technology]

近年、回路の高密度化と共に、フラットパックＩＣを利
用したプリント板への直接ハンダ付けによる高密度実装
が急増している。フラットパックＩＣを実装するには、
プリント板の電極パッドとフラットパックＩＣの端子リ
ードとの位置合せを行ってプリント板上にフラットパッ
クＩＣを位置決めし、電極パッドに端子リードを直接ハ
ンダ付けしてプリント板にフラットパックＩＣを実装さ
せていた。In recent years, as the density of circuits has increased, high-density packaging using flat pack ICs by direct soldering to printed circuit boards has rapidly increased. To implement flat pack IC,
Position the flat pack IC on the printed board by aligning the electrode pads on the printed board with the terminal leads of the flat pack IC, and then solder the terminal leads directly to the electrode pads to mount the flat pack IC on the printed board. was.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、上述した従来のフラットパックＩＣの実
装方法では、フラットパックＩＣの高密度実装化のため
、端子リードピッチが非常に狭くなっており（約１．２
７〜０．６３５　）、位置決めが難かしく、また端子リ
ードの極くわずかな曲りによって、平滑性がない場合に
は、リードの浮きが生じ位置決めは非常に難かしくなる
という欠点があった。However, in the conventional flat pack IC mounting method described above, the terminal lead pitch has become very narrow (approximately 1.2
7 to 0.635), positioning is difficult, and if the terminal lead is not smooth due to a very slight bend, the lead may float, making positioning very difficult.

本発明は前記問題点を解消するもので、実装時における
プリント板上でのフラットパックＩＣの位置決めを容易
に行うことができるようにしたフラットバックＩＣを提
供するものである。The present invention solves the above-mentioned problems and provides a flat-back IC that allows easy positioning of the flat-pack IC on a printed board during mounting.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

本発明はフラットパックＩＣ本体より横向きに張り出し
た端子リードを有し、該端子リードをプリント板の電極
パッドに直接ハンダ付けしてフラットパックＩＣ本体を
プリント板に実装するフラットバックＩＣにおいて、一
部の端子リードを直角に折曲し、該端子リードを他の端
子リードの高さ位置より下方に突き出し、これをプリン
ト板上でのフラットパックＩＣ本体の位置決め用リード
として用い、かつプリント板に前記位置決め用リードを
嵌合する位置決め孔を設けたことを特徴とするフラット
パックＩＣである。The present invention relates to a part of a flat-back IC that has a terminal lead extending laterally from the flat-pack IC body, and in which the terminal lead is directly soldered to an electrode pad of a printed board to mount the flat-pack IC body on the printed board. Bend the terminal lead at a right angle, protrude it below the height of the other terminal leads, and use it as a lead for positioning the flat pack IC body on the printed board. This is a flat pack IC characterized by having a positioning hole into which a positioning lead is fitted.

〔実施例〕〔Example〕

以下、本発明の実施例を図によって説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第２図（α）、第３図に示すように、フラットパックＩ
ＣはフラットパックＩＣ本体３よシ横向きに張り出した
端子リード２．・・・・・・を有し、端子リード２とプ
リント板４の電極パッド４αとの位置合せを行ってプリ
ント板４上にフラットパックＩＣ本体３を位置決めし、
端子リード２と電極ノ々ツド４ｃＬとを直接ハンダ付け
してプリント板４にフラットパックＩＣ本体３を実装す
るものである。As shown in Figure 2 (α) and Figure 3, flat pack I
C is a terminal lead 2 that extends sideways from the flat pack IC body 3. ..., and positions the flat pack IC body 3 on the printed board 4 by aligning the terminal leads 2 and the electrode pads 4α of the printed board 4,
The flat pack IC body 3 is mounted on the printed board 4 by directly soldering the terminal leads 2 and the electrode notches 4cL.

第１図において、本実施例は複数本の端子ＩＪ−ド２の
うち、フラットパックＩＣ本体３の四角に位置する端子
リード１α〜１ｄを直角に折曲してこれを他の端子リー
ド２の高さ位置より下方に突き出し、該端子リード１α
〜１ｄをプリント板４上でのフラットパックＩＣ本体３
の位置決め用リードとして用いる。一方、プリント板４
には、フラットパックＩＣ本体３の端子リード２をハン
ダ付けする電極パッド４ｃＬ、・・・列内に配置して、
前記位置決め用リードｌ（Ｚ〜１ｄを嵌合する位置決め
用孔５．・・・・・・を設ける。また、リード１α〜１
ｄはプリント板４の孔５への挿入を容易にするために、
その先端が細い形状にしてあり、一方位置決め用孔５は
フラットバックＩＣ搭載側にはランドを設けずに、反対
面にのみランド６を設けたランドレススルホールにて製
作する・ 実施例において、フラットパックＩＣをプＩＪ　７ト板
に実装するには、プリイト板４上で位置決め用孔５とフ
ラットパックＩＣ本体３の位置決め用リード１ｃＬ〜１
ｄとの位置合せを行って、リード１α〜ｌｄを孔５内に
挿入し、リードｌα〜１ｄの背部１′を位置決め用孔５
の口縁５ａに当接させる。本実施例によれば、位置決め
用リード１α〜ｌｄとして、端子リード列のうち一部の
端子リードを用い、かつプリント板４には電極パッド列
内に配置して、位置決め用孔５を設けであるため、リー
ドｌｒＬ〜１ｄを孔５内に嵌合することによシ、部端子
リード２と電極パッド化との位置合せがなされ、プリン
ト板４上にフラットパックＩＣ本体３が位置決めされる
。In FIG. 1, the present embodiment bends terminal leads 1α to 1d located in the squares of the flat pack IC main body 3 at right angles among the plurality of terminal IJ-doards 2, and bends them at a right angle. The terminal lead 1α protrudes below the height position.
~1d on the flat pack IC body 3 on the printed board 4
Used as a positioning lead. On the other hand, printed board 4
, electrode pads 4cL, to which the terminal leads 2 of the flat pack IC body 3 are soldered, are arranged in a row.
A positioning hole 5 into which the positioning lead l (Z~1d) is fitted is provided.
d to facilitate insertion into the hole 5 of the printed board 4;
Its tip has a narrow shape, and the positioning hole 5 is manufactured as a landless through hole with no land provided on the side where the flat back IC is mounted and a land 6 provided only on the opposite side. To mount the pack IC on the flat pack IC 7 board, connect the positioning holes 5 and the positioning leads 1cL to 1 of the flat pack IC main body 3 on the board 4.
d, insert the leads 1α to ld into the holes 5, and insert the back parts 1' of the leads lα to 1d into the positioning holes 5.
5a of the mouth. According to this embodiment, some of the terminal leads in the terminal lead row are used as the positioning leads 1α to ld, and the positioning holes 5 can be provided in the printed board 4 by disposing them within the electrode pad row. Therefore, by fitting the leads lrL to 1d into the holes 5, the terminal leads 2 and the electrode pads are aligned, and the flat pack IC body 3 is positioned on the printed board 4.

したがって、フラットパックＩＣ本体３のリードｌａ〜
１ｄをプリント板４の孔５に挿入すれば、端子リード２
と電極パッド化との位置ずれなく、確実に位置合せした
状態でハンダ付けを行ってフラットパックＩＣ本体３を
プリント板４上に実装できるＯ 〔発明の効果〕 以上説明したように本発明によるフラットパックＩＣに
は次の効果がある。すなわち、（１）ハンダ付時にフラ
ットパックＩＣは位置決めして固定されるため、位置合
せは確実に行うことができる。Therefore, the leads la~ of the flat pack IC body 3
1d into the hole 5 of the printed board 4, the terminal lead 2
The flat pack IC main body 3 can be mounted on the printed circuit board 4 by soldering in a state where the electrode pads and the electrode pads are reliably aligned without misalignment. Pack IC has the following effects. That is, (1) since the flat pack IC is positioned and fixed during soldering, alignment can be performed reliably.

（２）フラットパックＩＣの２本以上の端子リードを位
置決め用として用いであるので、プリント板への挿入性
は問題にならない。(2) Since two or more terminal leads of the flat pack IC are used for positioning, insertability into the printed board is not a problem.

（３）２本以上の位置決め用端子リードに合う箇所のみ
位置決め用孔を設けるので、プリント板のパターン設計
上の配線密度等の影響は殆ど無い。(3) Since the positioning holes are provided only at locations that fit two or more positioning terminal leads, there is almost no influence on the wiring density, etc. on the pattern design of the printed board.

（４）プリント板に設ける位置決め用孔は数個でよいた
め、コスト上も影響は無い。(4) Since only a few positioning holes are required on the printed board, there is no impact on cost.

（５）位置決め用孔はランドレスとするが、その孔はＩ
Ｃの固定のみに用い、フラットパックＩＣとの電気接続
はランドレススルホール以外の部分のプリント板上のパ
ッドを使ってハンダ接続により行うので、ランドレスス
ルホールの信頼性は十分にある。(5) The positioning hole is landless, but the hole is I
The landless through-hole is sufficiently reliable because it is used only for fixing C, and the electrical connection with the flat pack IC is made by soldering using pads on the printed board in areas other than the landless through-hole.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明のフラットパックＩＣをプリント板に実
装した状態を示す断面図、第２図（、ｚ）は同平面図、
（ｂ）は同底面図、第３図は本発明のフラットパックＩ
Ｃを示す斜視図である。 ｌα−１ｄ・・・位置決め用リード　２・・・端子リー
ド３・・・フラットバックＩＣ本体　　４　・・プリン
ト板５・・・位置決め用孔 特許出願人　　日本電気株式会社 第１図FIG. 1 is a sectional view showing the flat pack IC of the present invention mounted on a printed board, FIG. 2 (, z) is a plan view of the same,
(b) is a bottom view of the same, and Fig. 3 is a flat pack I of the present invention.
FIG. lα-1d...Positioning lead 2...Terminal lead 3...Flat back IC body 4...Printed board 5...Positioning hole Patent applicant NEC Corporation Figure 1

Claims (1)

【特許請求の範囲】[Claims] （１）フラットパックＩＣ本体より横向きに張り出した
端子リードを有し、該端子リードをプリント板の電極パ
ッドに直接ハンダ付けしてフラットパックＩＣ本体をプ
リント板に実装するフラツトパツクＩＣにおいて、一部
の端子リードを直角に折曲し、該端子リードを他の端子
リードの高さ位置より下方に突き出し、これをプリント
板上でのフラットパックＩＣ本体の位置決め用リードと
して用い、かつプリント板に前記位置決め用リードを嵌
合する位置決め孔を設けたことを特徴とするフラツトパ
ツクＩＣ。(1) Some flat pack ICs have terminal leads extending laterally from the flat pack IC body, and the terminal leads are directly soldered to the electrode pads of the printed board to mount the flat pack IC body on the printed board. The terminal lead is bent at a right angle, the terminal lead is protruded below the height of the other terminal leads, and this is used as a lead for positioning the flat pack IC body on the printed board, and the terminal lead is used for positioning the flat pack IC body on the printed board. A flat pack IC characterized by having a positioning hole into which a lead is fitted.
JP4889885A 1985-03-12 1985-03-12 Flat pack ic Pending JPS61208247A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4889885A JPS61208247A (en) 1985-03-12 1985-03-12 Flat pack ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4889885A JPS61208247A (en) 1985-03-12 1985-03-12 Flat pack ic

Publications (1)

Publication Number Publication Date
JPS61208247A true JPS61208247A (en) 1986-09-16

Family

ID=12816083

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4889885A Pending JPS61208247A (en) 1985-03-12 1985-03-12 Flat pack ic

Country Status (1)

Country Link
JP (1) JPS61208247A (en)

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