JPS61208244A - Package for depriving silicon semiconductor chip of heat - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates generally to removing heat from semiconductor chips, and more particularly to mounting and encapsulation systems for high density semiconductor chips.

BACKGROUND OF THE INVENTION The large scale integration of circuits onto semiconductor chips has resulted in high density circuits in relatively small geometries. As the geometry becomes smaller, the operating temperature of the chip increases. This is because there are many elements on the chip that dissipate heat,
This is also an additive effect due to their proximity.

This heat is easily extracted from circuits with low density. However, as density increases, this additive effect becomes even more significant because the amount of heat generated per unit area increases unless the thermal resistance between the circuit and the heat sink is reduced accordingly.

Conventional packaging schemes for low cost semiconductor devices use some form of mounting substrate that defines the lead pattern for bonding the chip to it and also provides a mounting surface.

Depending on the type of chip attached to this surface as well as its intended use, the attachment can change the thermal properties of the surface. For example, in consumer applications, the temperature extremes encountered in packaged chips are lower than in military packaging. Therefore, in military applications, the balance of thermal properties between the chip and mounting surfaces becomes even more important.

If the mounting is such that the coefficient of thermal expansion of the circuit differs significantly from that of the chip, the chip may be subjected to undesirable stresses during temperature cycling. Therefore, it is desirable that the coefficients of thermal expansion of both the chip and the mounting surface be as close as possible.

Another factor that makes mounting surfaces desirable is their high thermal conductivity. This is necessary to reduce the temperature drop between the temperature of the active surface of the chip and the periphery of the mounting surface.

Higher reliability is achieved by lowering the surface temperature of the chip. Current installations use materials such as alumina oxide and various alloys for the surfaces. Although alumina oxide has relatively good thermal conductivity, its coefficient of thermal expansion is about 60% greater than that of silicon, a common material from which semiconductor chips are made. A thermal expansion mismatch between the silicon chip and the mounting surface can create significant stresses due to large temperature fluctuations during temperature cycling of the mounted device.

If these stresses are not controlled, they can lead to cracking of semiconductor chips.

Due to various mounting conditions on surfaces, there is a need for mounting on surfaces that have appropriate thermal conductivity and a coefficient of thermal expansion close to that of the semiconductor chip to be mounted thereon.

Traditional packaging schemes for low cost semiconductor devices use plastic encapsulation and lead frame construction. In this structure, a semiconductor chip is attached to a lead frame, wires are bonded to it, and then encapsulated in plastic. The primary heat transfer path is from the chip through the plastic to the exterior of the package or to an external heat sink. From a reliability standpoint, it is important to minimize the surface temperature of the chip. To this end, it removes heat from the semiconductor chip and transfers this heat to the surface of the package, where it is finally dissipated. This is usually facilitated by attaching a heat spreader to the lead frame/semiconductor chip. A heat spreader is utilized to spread the heat generated by the semiconductor chip over a larger surface area and volume.

This larger surface area allows for more efficient heat transfer to the surroundings, but the volume provides a greater heat capacity relative to this entire volume.

Due to the thermal expansion mismatch between the silicon chip and its surrounding packaging material, significant stresses can be generated by large temperature fluctuations during temperature cycling of the packaged device. If these stresses are not controlled,
This may cause strain cracks in semiconductor chips. For this reason, the material used as the heat spreader must have a thermal expansion that is balanced with that of the silicon chip.

Because of the problems described above with the encapsulation of semiconductor chips, there is a need for improved materials and methods for extracting heat from the semiconductor chip and transferring that heat to and removal from the surface of the package.

SUMMARY OF THE INVENTION The present invention provides a mounting surface for mounting silicon semiconductor chips. The mounting surface includes a substrate having a coefficient of thermal expansion approximately similar to that of silicon. The substrate is made of silicon carbide by conformally coating graphite platelets with silicon carbide so that they are coplanar with the top layer.

An interconnect pattern is formed on one side of the silicon carbide substrate, and chips are adhered to selected portions of the pattern. The thermal resistance in this selected area between the chip and the substrate is very small and the flow of heat between the chip and the substrate is not restricted.

In another embodiment of the invention, a planar pattern is formed in the graphite platelet portion of the substrate.

A conformal coating of silicon carbide reflects this planar pattern. This planar pattern forms a well for receiving the semiconductor chip, so that the top surface of the chip is lower than the rest of the interconnect pattern.

The present invention (another embodiment) also provides a package that protects a silicon semiconductor chip while reducing its surface temperature. The package has a lead frame electrically interconnected with the chip, which has a mounting section for mounting the chip thereon. A heat spreader is located on the opposite side of the chip, adjacent to the lead frame mounting section, and is made of silicon carbide. Thermal fraction devices have a much larger surface area than the chip, and have a larger effective surface area from which heat can be dissipated. Silicon carbide has a coefficient of thermal expansion roughly similar to the silicon in the chip. The chip, lead frame and heat spreader are encapsulated within a plastic layer, with the heat spreader being completely encapsulated and the lead frame extending outwardly therefrom for interconnection with the exterior of the package.

In yet another embodiment of the invention, a second heat spreader is placed at a predetermined distance above the chip.

A second heat spreader is also encapsulated within the plastic layer, creating a shorter thermal path through the plastic from the active side of the chip. The second heat spreader has a significantly larger surface area than the chip.

In order that the invention and its advantages may be better understood, reference will now be made to the drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a perspective view of a mounting board 10 with a lead pattern defined thereon is shown.

The lead pattern consists of an attachment pad 12 and a plurality of metal leads 14 extending radially outwardly from the attachment pad 12 and electrically isolated therefrom. Leads 14 may be deposited onto substrate 10 by vacuum deposition methods or may be attached by screening. semiconductor chip 16
However, it is installed on top of the pad 12, and the bonding
It is interconnected to lead 14 by wire 18 . A lead 20 is attached to the lead 14 at the periphery of the substrate 10 and is disposed downwardly at right angles to the surface of the substrate 100. The installation shown in Figure 1 is in the form of a 16-bin dual in-line package (DIR).

FIG. 2 shows a cross-sectional view of the mounting substrate 10 and the chip 16. Although not shown in the figures, a lid is used to cover the chip 16 and isolate it from the outside environment. This cover is attached using ordinary adhesive and provides some degree of airtightness. During operation, semiconductor chip 16 acts as a heat source. The chip 16 is attached to the pad 12 using an adhesive such as a gold preform or gold-filled polyimide.
mounted on. This is a low thermal resistance material and the mounting provides good heat transfer between the chip 16 and the pad 12. Because the mounting pad 12 is relatively thin and the mounting is deposited onto the substrate 10, this provides an inherently high thermal resistance path for heat dissipation.

At a temperature lower than the surface temperature of the chip 16, the mounting substrate 10 can act to have sufficient surface area. If possible, it is desirable that the surface temperature of the active portion of the chip be the same as the temperature around the mounting substrate 10. However, there is always a certain amount of thermal resistance between the periphery of the mounting substrate 10 and the active surface of the chip 16. The chip 16 and the mounting utilize materials with low thermal resistance to minimize thermal resistance between the outer surface of the substrate 10. For installation, the thermal resistance of the board 10 is chip 1.
The active surface of 6 and the mounting determine the temperature difference between the thermally conductive surface of substrate 10. The surface of the chip 16 and its mounting are on the substrate 10.
As long as the thermal resistance between it and the outer surface of the material is small, the temperature difference therebetween is extremely small. Since the mounting substrate 10 has a significantly larger surface area than the chip 16, the effective surface area for heat dissipation can be significantly increased. By increasing this effective area, the 1ca generated by chip 16
The amount of heat in watts per +2 can be distributed over a large area and effectively removed therefrom, which results in a lower temperature of the chip and a corresponding increase in the reliability of the chip.

If the temperature differential between the active surface of the chip 16 and the peripheral surface of the mounting substrate is not minimized, reliability problems may occur during operation of the device. By making the mounting substrate 10 from a material with low thermal resistance, the surface temperature of the chip 16 can be further lowered, thereby increasing reliability.

Another important point that occurs during temperature cycling is the relative expansion and contraction between the chip 16 and the mounting substrate 10.

Typically, silicon has a coefficient of thermal expansion of 4.2X10'/
'C. If the substrate 10 used for mounting does not have a coefficient of thermal expansion similar to that of silicon, stress will be applied to the chip 16.

This stress can cause reliability problems in the form of strain cracks and the like. Therefore, it is desirable that the mounting substrate 10 be made of silicon or other material having a coefficient of thermal expansion similar to that of the material from which the chip 16 is made. In addition to the coefficient of thermal expansion, it is also important to have high thermal conductivity.

In the preferred embodiment, the semiconductor material used for the chip is silicon and the material used for the mounting substrate 10 is graphite platelets 22 with a conformal coating 24 of silicon carbide.

This material is described in U.S. Pat. No. 3,250,322;
．． No. 391,016 and No. 3.317.356 by Texas Instruments, Inc. in the conventional manner described in US Pat.

Both of these US patents are assigned to the applicant. Graphite platelets 22 are placed substantially within the vacuum chamber and silicon carbide is deposited thereon by a chemical vapor deposition method. Silicon carbide is formed by the reaction of silicon tetrachloride with the thermal decomposition of hydrocarbons. graphite plate 22
will be the substrate for this deposition.

The graphite platelets 22 are a material that can be processed to form any shape required for the mounting substrate 10.

On the other hand, silicon carbide is relatively expensive to process, polish, etc., and is therefore a relatively expensive material when used by itself. The coefficient of thermal expansion of silicon carbide is 4.5x10-6/'
C, and the thermal conductivity is 1 watt/α℃ to 5 watts/
apr "C.The coefficient of thermal expansion of graphite is 6.3X10
-6/'C, and the thermal conductivity is 1.7 Watts/[alpha]C.

Silicon carbide is a binary alloy composed of the elements silicon and carbon. The strong covalent bonding of these light elements within the cubic crystal structure results in materials with very high thermal conductivity due to phonon conduction. A phonon is defined as a quantum with elastic energy. In comparison, heat transfer in metallic materials is primarily carried out by electrons.

Diamond-phase carbon is an excellent conductor of heat, rated at 20 watts/°C (roughly 5 times better than steel), but it is very expensive and has a low coefficient of thermal expansion (1,
2x10'/'C), making the low cost mounting used for silicon chips unsuitable for use as substrates.

For mounting, if silicon carbide is used for the substrate 10, the chip 16
It has excellent thermal balance with respect to silicon material and has high thermal conductivity. Additionally, silicon carbide is a semi-insulating material, which makes wire 18, lead 14 and lead 2
This is important in preventing an electrical short circuit when the 0 comes into contact with a surface.

Silicon is also non-corrosive, so mounting is recommended for substrate 10.
Corrosion problems between the wires and other metal parts such as bonding wires, leads 20, and metallization of the chip are eliminated. Another property of silicon carbide that is desirable from a manufacturing standpoint is that it has a hard surface. This surface is smooth to allow for reliable deposition of leads 14 and attachment pads 12, and this surface has very high drag resistance.

From a handling point of view, this is also of some importance.

Additionally, silicon carbide provides a surface for mounting the chip with very low alpha particle emission.

This is due to the fact that the chemical vapor phase growth of silicon carbide can be performed without trace elements that release alpha particles.

The silicon carbide layer and attachment deposit a thin layer of dielectric material, such as silicon dioxide 25, over the substrate 10 to further improve the isolation between the pads 12 and leads 14.

This provides excellent isolation without degrading the thermal conductivity properties of the various layers or their relative coefficients of thermal expansion.

In FIG. 3, an alternative embodiment mounting board is shown and the same reference numerals are used throughout the drawings to refer to like parts. The mounting substrate 26 consists of graphite platelets 28 covered with a conformal coating 30 of silicon carbide and a layer of silicon dioxide. A well 32 is formed in the graphite platelet 28 for receiving the semiconductor chip 16. Since silicon carbide layer 30 is formed conformally, well 34 is formed therein. The mounting is such that the pads 12 are placed in the wells 34 so that the surface of the chip 16 is low relative to the rest of the circuit. The other parts of the circuit are the lead frames 14 which are mounted outside of the wells 34 and whose mounting is at a higher plane than the pads 12.

By utilizing graphite in the small plate 28, a well 3 is formed therein.
2 is easy to process. However, graphite has certain undesirable properties, such as "flaking", making the attachment to silicon chip 16 unsuitable for use as a surface. As mentioned earlier, although silicon carbide is a desirable surface, its undesirable property is its lack of processability. Any type of planar pattern can be placed and then a conformal coating 35 of silicon carbide placed thereon.

Another embodiment of the invention for mounting the tip 16 is shown in FIG. For installation, the board 36 is a small graphite plate 3.
8, consisting of a conformal coating of silicon carbide 40 and a layer of silicon dioxide 42.

An orifice 44 is located within the graphite platelet and a silicon carbide layer 40 extends downwardly therein at portion 46.

The orifice 44 is formed in the graphite platelet 38 during manufacture, and the platelet 38 is then conformally coated with silicon carbide so that the orifice 44 is formed in the portion 46.
so that it is coated with This allows the mounting to occur between the top and bottom surfaces of the substrate 36 throughout the orifice 4.
8 is formed.

Chip 16 is mounted on top of mounting pad 50. Attachment pad 50 is separated from silicon carbide layer 40 by silicon dioxide 1142.

Chip 16 is coupled to circuit interconnects 52 using bond wires 54 . Circuit interconnect 52 is a metal layer deposited over the surface of silicon dioxide layer 42 and may serve to interconnect with other portions of the circuit (not shown). A further metallization layer 56 is provided and interconnected with the chip 16 using bonding wires 58.

The metallization layer 56 is formed on the top surface of the mounting substrate 36, on the portion 46 of the silicon carbide layer 40 that conformally coats the orifice 44 in the graphite platelet 38, and on the lower portion of the mounting substrate 36. will be deposited. this is"
It is called a "plated through hole". This allows the upper and lower surfaces of the mounting board 36 to be electrically connected.

For example, metallization layer 56 may represent a ground plane. By using an orifice 44 located within the graphite platelet 38, a ground plane can be placed anywhere on the surface of the mounting board 36 by placing the orifice within the graphite platelet 38. . This reduces the conductive path and associated inductance. This is important for high speed switching applications, video applications as well as high frequency applications.

In summary, we have provided a composite substrate for mounting semiconductor chips. The composite substrate consists of graphite platelets with a conformal coating of silicon carbide thereon. Silicon carbide has the same coefficient of thermal expansion as a silicon semiconductor chip. A metallization pattern for interconnecting the chip is disposed on the surface of the semiconductor chip, and an insulating layer is provided between the chip and the substrate.

FIG. 5 shows a perspective view of semiconductor chip 10 mounted on lead frame 12 and heat spreader 14. In FIG. Semiconductor chip 10 is bonded to lead frame 12, and lead frame 12 is then bonded to heat spreader 14. The lead frame 12 is of a type called a dual in-line package (DIR).

FIG. 6 shows a chip 10 encapsulated and mounted in a plastic package, and a lead frame 1.
2 and a cross-sectional view of the heat dispersion device 14 are shown. The package consists of an upper part 16 and a lower part 18. The upper and lower portions 16,18 are formed using conventional encapsulation techniques.

To explain the operation of the embodiment shown in FIGS. 5 and 6, the semiconductor chip 10 acts as a heat source. Lead frame 12 is made of a relatively thin alloy. Lead frame 12 and chip 10 are attached to heat spreader 14 using the same adhesive. The adhesive used to attach chip 10 to lead frame 12 and lead frame 12 to heat spreader 14 is a gold preform or silver filled polyimide. This is a material with low thermal resistance and provides good heat conduction between the chip 10 and the heat spreader 14.

Heat spreader 14 may serve to provide a sufficient mass at a temperature lower than the surface temperature of chip 10. chip 10
Use materials with low thermal resistance to ensure adequate flow of heat from the plastic package to the outside surface of the plastic package. The thermal resistance of heat spreader 14 determines the temperature drop between the active surface of chip 10 and the outer surface of the plastic package.

As long as the thermal resistance θJC between the surface of the chip 10 and the outer surface of the plastic package is small, the temperature difference from the surface of the chip to the surface of the package is small. Furthermore, heat dispersion device 1
Since chip 4 has a significantly larger surface area than chip 10, the available surface area for heat dissipation can be increased considerably, which reduces the thermal resistance θ between the surface of the plastic package and the surroundings. useful for. θ,. and θ. .

The total thermal resistance between the chip and the surroundings θJA = θ, since both A and A are reduced by the heat spreader. +θcA decreases significantly. This reduction in the thermal resistance between the surface of the chip and the ambient conditions means that the temperature of the chip decreases and the reliability of the chip increases correspondingly exponentially. .

An important issue during temperature cycling is the relative expansion and contraction between the chip 10 and the lead frame 12 and heat spreader 14 of FIGS. 5 and 6.

Typically, silicon has a coefficient of thermal expansion of 4.2 x 10'/
'C. If the heat spreader 14 does not have a coefficient of thermal expansion similar to silicon, stress will be applied to the chip 10. As a result of this stress, reliability problems in the form of strain cracks and the like are common. Therefore, it is desirable to make heat spreader 14 from silicon or a material with a coefficient of thermal expansion similar to the material from which chip 10 is made. In addition to the coefficient of thermal expansion, it is also important to maintain the thermal conductivity at a high value.

In this embodiment, the semiconductor material used for chip 10 is silicon and the material used for heat spreader 14 is graphite platelets with a conformal coating 20 of silicon carbide. This material is disclosed in U.S. Patent No. 3,250.322,
No. 3,391,016 and No. 3,317.356
(both of which are manufactured by Texas Instruments, Inc.) according to the conventional methods described in No. Briefly, graphite platelets are placed in a vacuum chamber and silicon carbide is deposited thereon by a chemical vapor deposition method. The reaction between silicon tetrachloride and the thermal decomposition of hydrocarbons forms silicon carbide.

Graphite platelets 20 serve as the substrate for this deposition.

The graphite platelets 20 provide a workable material to form any shape required for the heat spreader 14. On the other hand, silicon carbide is relatively difficult to process, polish, etc., and is a relatively expensive material when used alone. The coefficient of thermal expansion of silicon carbide is 4.5×10'/'C, and the thermal conductivity is 1
watts/α°C to 5 watts/ax”c. The thermal conductivity of graphite is 1.7 watts/cm'C and the coefficient of thermal expansion is 6.3XIO'/'C.

Silicon carbide is a binary alloy consisting of the elements silicon and carbon. The strong covalent bonds of these light elements within the cubic crystal structure create materials with very good thermal conductivity through phonon conduction. A phonon is defined as a quantum with elastic energy. In comparison, heat transfer through metallic materials is performed primarily by electrons. Diamond-phase carbon is an excellent conductor of heat with a power rating of 20 watts/att'
C (approximately 5 times better than steel), but its cost is very high and its coefficient of thermal expansion is small (1.2X10
'/'C), making it unsuitable for use as a low-cost heat dispersion device for silicon chips.

The use of silicon carbide in the heat spreader of FIGS. 5 and 6 provides excellent thermal balance to the silicon material of the chip 10 and provides high thermal conductivity. Additionally, silicon carbide is a semi-insulating material, which is important in preventing the leads of lead frame 12 from shorting together through heat spreader 14. Silicon carbide is also non-corrosive, so there are no corrosion problems between the heat spreader 14 and other metal parts within the package, such as bonding wires, leadframes, and metallization of the chip. Another desirable property of silicon carbide is that it has a hard surface during manufacture. This surface is smooth and allows the lead frame 12 to be reliably attached, and has high scratch resistance. From a handling perspective, this is also of some importance.

Another embodiment of the heat dispersion device 14 is shown in FIG. 7, with the same reference numerals used for the same parts.

The heat dispersion device i14 is provided with a plurality of through holes 24. During manufacturing, such holes are formed in the graphite platelets 20, and the platelets 20 are then bonded to silicon carbide [122
Coat with. It is easier to form the holes 24 in the graphite platelets 20 than to form them in the silicon carbide layer 22 at a later point. A conformal layer 22 of silicon carbide forms a coating 26 along the sides of each hole 24 . In a preferred embodiment, the heat distribution bag @14 is approximately 5cm long.
Il, width 1.3 mm, thickness 0.0'7501. The thickness of the graphite platelets 20 is approximately 0.025aR and the thickness of the conformal coating is approximately 0.0251. The diameter of the holes 24 after coating with a conformal layer 22 of silicon carbide is approximately 0.125 cIR.

FIG. 8 shows a cross-sectional view of the heat distribution device 14 of FIG. 7 with through-holes 24, in which the same reference numerals are used for the same parts as before. The upper portion 16 and lower portion 18 of the encapsulated package are interconnected through an orifice 24 by a plastic plug 28 . By using orifice 24,
The provision of attachment points between the upper portion 16 and the lower portion 18 results in a structurally more robust package.

Another embodiment of the invention is shown in cross-section in FIG. 9, in which the same reference numerals are used for the same parts. A heat spreader 30 is disposed within upper portion 16 and spaced a predetermined distance from the top surface of chip 10 and lead frame 12 . The heat dispersion device 30 is
It is constructed similarly to heat spreader 14 in that it has a conformal coating 32 of silicon carbide formed over graphite platelets 34 . Holes 36 are provided in the heat distribution device 30 .

By locating the heat spreader 30 above the plane of the chip 10, the length of the thermal path between the top surface of the chip 10 and the heat sink source is shortened. Since plastic has a thermal conductivity of approximately 0.01 watt/α°C, from the top surface of the chip 10,
Whatever the shape, it is important to minimize the length of the thermal path to the 7 heat sink or heat spreader. This effectively provides another path for removing heat from semiconductor chip 10.

Figure 10 shows another example of a heat dispersion bag lol! 3B is shown. A trough 40 is located in the center of the heat distribution device 38 with an orifice 42 passing through the distribution device. Orifice 42 is similar to orifice 24 of FIG. The heat spreader 38 is made of a conformal layer 44 of silicon carbide on top of graphite platelets 46. Furthermore, an insulating layer 48 of silicon oxide is disposed on the conformal layer of silicon carbide! ! has been done.

Silicon oxide layer 48 becomes an electrically insulating layer.

FIG. 11 shows a cross-sectional view of the heat dispersion device 38 with a semiconductor chip 50 mounted thereon. The central chip attachment located within the trough 40 includes a portion 52 and two bonding leads 54, 56 located near the chip 50.
A lead frame made of Chip 50 is coupled to bonding pads 56 by bonding wires 58 and bonding wires 60
is coupled to bonding lead 54 by.

The trough 40 can be used to support bonding leads 54, 56, which are a portion of the lead frame and are positioned slightly higher than the central portion 52. The use of silicon oxide insulating layer 48 prevents shorts between bonding leads 54 and 56.

To form the trough 40, a trough 62 is first formed in the graphite platelets 46 and then a conformal layer 44 of silicon carbide is formed.
deposit on it. As previously mentioned, the use of graphite for the substrate or platelet 46 provides a relatively easy to process medium for fabricating various dimensions into the substrate. This allows any number of dimensions or patterns to be formed in the substrate before silicon carbide is deposited thereon.

In summary, for use in encapsulated semiconductor devices,
A heat dispersion device is provided that increases its effective surface area. The heat spreader is made of graphite platelets with a conformal layer of silicon carbide deposited thereon. Silicon carbide has both a high thermal conductivity and a coefficient of thermal expansion that is compatible with the chip. This not only prevents stress cracking of the silicon chip during temperature cycling, but also effectively removes heat from the semiconductor chip.

Although the preferred embodiment has been described in detail, it is to be understood that various substitutions and changes may be made within the scope of the invention as defined by the claims.

In connection with the above description, the following sections are further disclosed.

(1) A package for removing heat from a silicon semiconductor chip, comprising a lead frame electrically interconnected with the chip and the outside of the package, the chip being attached to the lead frame, and further , a heat spreader disposed adjacent to the chip, the lead frame disposed between the chip and the heat spreader, the heat spreader being made of silicon carbide and disposed adjacent to the chip; the heat spreader has a coefficient of thermal expansion approximately similar to that of the chip, and the heat spreader is bonded to the lead frame to reduce thermal resistance therebetween. a plastic layer formed around the chip, the heat spreader and the lead frame, the plastic layer encapsulating the heat spreader so that the heat spreader is completely encapsulated; A package with a lead frame extending outwardly therefrom to interconnect between the chip and the exterior of the package.

(2) In the package described in item (1), the lead frame is, but is not necessarily limited to, a lead frame of a dual in-line package.

(3) In the package described in item (1), the silicon carbide of the heat dispersion device is disposed on a graphite substrate, and the silicon carbide coats the graphite substrate in the same shape.

(4) In the package described in paragraph (1), a secondary heat dispersion device is disposed above the chip, facing the heat dispersion device, and the plastic layer is arranged between the secondary heat dispersion device and the chip. a package, the secondary heat dissipating device having a surface area significantly larger than the chip and distributing heat received from the chip to its periphery through plastic disposed therebetween;

(5) In the package according to paragraph (1), an orifice is arranged in the heat dispersion device so that the plastic encapsulation layer can be placed through it. , a package that improves the structural integrity of the package.

(6) In the package according to paragraph (3), a topographical pattern is formed in the graphite substrate, and the isoform coating of silicon carbide is the same as the topographical pattern, and the topographical pattern is the same as the topographical pattern. A package designed to reflect on the surface of the heat dispersion device.

(7) In the package described in paragraph (6), the topographical pattern has a trough that receives a portion of the lead frame below the semiconductor chip, and the trough covers the surface of the semiconductor chip with the lead frame. The package allows the burr to be kept at the same height as the rest of the frame.

(8) In a package for supporting a silicon semiconductor chip and minimizing its surface temperature, a mounting section for mounting the chip thereon and for electrically interconnecting with the active surface of the chip. a lead frame having a plurality of interconnect leads for electrically interconnecting the chip and the exterior of the package; an attachment of the lead frame on a side opposite the chip is disposed adjacent to the portion; and a heat spreader having a surface area significantly greater than the surface area of the chip, the heat spreader consisting of graphite platelets with a conformal coating of silicon carbide disposed thereon; silicon has a thermal expansion coefficient approximately equal to that of the silicon of the semiconductor chip, a through orifice is provided in the heat dissipation device, and the heat dissipation device is bonded to the mounting portion of the lead frame. a means for reducing thermal resistance therebetween; formed around and encapsulating the chip, the heat spreader and the lead frame so that the heat spreader is completely encapsulated and the lead frame is encapsulated; and a plastic layer extending outwardly so as to connect with the exterior of the package, the plastic being placed within the orifice interconnecting the plastic on either side of the heat spreader. A package that enhances the structural integrity of the package.

(9) The package of paragraph (8), wherein the orifice is formed within the graphite platelet and the silicon carbide conformally coats the inside of the orifice.

(10) In the package described in item (8), a trough is formed on the surface of the heat dispersion device adjacent to the part where the lead frame is attached, and the part where the lead frame is attached is The package is arranged at a lower height than the rest of the lead frame when mounted on the dispersion device.

(11) In the package according to paragraph (10), the trough is formed within the graphite platelet, and the conformal layer of silicon carbide is conformal to the trough formed within the graphite platelet. A certain package.

(12) In the package described in item (8), the heat dispersion device includes a secondary thermal splitting device disposed above the chip on the opposite side of the lead frame, and A dispersion device is encapsulated within said plastic layer and said two
The heat spreader receives heat from the chip through the plastic layer and has a surface area significantly larger than the chip.

(13) The package of paragraph (8), wherein a thin layer of electrically insulating material is disposed over the heat dissipating device.

(14) A method for packaging a silicon semiconductor chip and lowering the surface temperature of the chip, wherein the chip is placed on a lead frame, the lead frame being an interconnect between the active surface of the chip and the exterior of the package. the lead frame and attached chip are mounted on a silicon carbide layer, the silicon carbide layer having a significantly larger surface area than the chip; encapsulating the material within a plastic layer.

(15) In the method described in item (14), further, a secondary heat dispersion device is arranged on one side above the chip on the opposite side of the lead frame from the heat dispersion device, and the secondary heat dispersion device is mounted at a predetermined distance from the top surface of the chip and is encapsulated by the plastic so that heat radiated from the top surface of the chip through the plastic is absorbed by the secondary heat spreader; A method in which the secondary heat spreader has a significantly larger surface area than the chip.

(16) The method described in paragraph (15) further includes providing a plurality of orifices in the heat dispersion device to allow the encapsulating material to flow therebetween, thereby improving the structural integrity of the package. How to increase perfection.

(17) An apparatus for attaching a silicon semiconductor chip, which includes a substrate having a thermal expansion coefficient close to that of silicon, the substrate being made of silicon carbide, and further comprising: an interconnection layer formed on the substrate; a connection pattern; and means for adhering the chip to a selected portion of the pattern, wherein the thermal resistance at the selected portion is extremely small between the chip and the substrate; A device that prevents heat flow from being restricted.

(18) The device according to item (17), wherein the substrate has a surface area larger than the surface area of the chip.

(19) The apparatus of paragraph (17), wherein the interconnection pattern comprises a metallization pattern deposited on the surface of the substrate and for adhering to the chip by the adhering means. A device that has a selected area of .

(20) In the device according to paragraph (11), the silicon carbide of the substrate is disposed on graphite platelets, and the silicon carbide conformally coats the graphite platelets. Device.

(21) In the apparatus of paragraph (20), a topographical pattern is formed in the graphite platelets, and the conformal coating of silicon carbide is isomorphic to the topographical pattern, and the topographical pattern is is reflected on the surface of the substrate.

(22) In the apparatus according to paragraph (21), the topographical pattern forms a well near the area to which the chip is bonded by the bonding means, and the surface of the semiconductor chip is in contact with the interconnection pattern. A device designed to be closer to a flat surface.

(23) In the apparatus of paragraph (17), the substrate has a through-hole orifice, the interconnect pattern is located on a side of the chip opposite to the side to which the chip is bonded, and An apparatus having an interconnection pattern disposed on an inner surface to interconnect both sides of the substrate.

(24) The device according to paragraph (17), comprising insulating means disposed between the substrate and the interconnect pattern.

(25) An apparatus for mounting silicon semiconductor chips, having a substrate having a coefficient of thermal expansion close to that of the chip, the substrate being made of graphite platelets conformally coated with silicon carbide. further comprising: a mounting pad disposed in a predetermined position on the surface of the substrate for attaching a chip thereto; means for adhering the chip to the mounting pad; and a mounting pad disposed on the substrate; an electrically conductive interconnect pattern enabling the chip to be interfaced with circuitry external to the substrate; and means for interfacing the chip with the interconnect pattern.

(26) The apparatus of paragraph (25), wherein a topographical pattern is formed within the graphite platelets, and the silicon carbide coating is conformal to the topographical pattern.

(21) In the apparatus of paragraph (26), the topographic pattern defines a well in the plane of the substrate near the mounting pad, and the top surface of the chip is in the plane of the interconnect pattern. The device is placed closer to the

(28) The apparatus of paragraph (25), further comprising: a metallization pattern located on an opposite side of the substrate from the interconnection pattern; , an orifice disposed through the substrate and interconnecting opposite sides thereof, the orifice being formed in the graphite platelet and conformally coated with silicon carbide; a metallization pattern disposed on an inner surface of the orifice and on a lower surface of the substrate; device having a metalized portion and an interconnecting metallization layer.

(29) The apparatus of paragraph (25), wherein the attachment comprises a layer of insulating material disposed between the pad and the substrate and between the metallization pattern and the substrate.

(30) The device according to item (29), wherein the insulating layer is made of silicon dioxide.

(31) In a method for attaching a semiconductor chip, a mounting pad is placed on a substrate having a coefficient of thermal expansion close to that of the chip, and a silicon carbide layer is placed on the surface of the substrate. placing an interconnect pattern on the surface of the substrate, and bonding the chip to a pad, the pad having a very low thermal resistance. The way you have it.

(32) The method of paragraph (31), wherein the attaching further comprises the step of disposing an insulating layer between the pad and the substrate and between the interconnect pattern and the substrate.

(33) The method of paragraph (31), further comprising the step of forming a topographical pattern in the graphite platelet before conformally coating the substrate with silicon carbide, the topographical pattern A method in which the pattern is reflected on the surface of the board.

(34) In the method described in item (31), further disposing a metallized layer on the lower surface of the substrate facing the chip, forming an orifice in the substrate, and forming an orifice on the inner surface of the orifice. A method comprising forming a metal layer to enable interconnection between a metallized bottom surface of the substrate and selected portions of the interconnect pattern.

[Brief explanation of drawings]

FIG. 1 is a perspective view of a semiconductor chip mounted on a substrate with a limited lead pattern, FIG. 2 is a cross-sectional view of the substrate, and FIG. 3 is another embodiment in which the chip is mounted in a well. FIG. 4 is a cross-sectional view of an alternative embodiment of the invention with orifices in the substrate; FIG. 6 is a cross-sectional view of the encapsulated device; FIG. 7 is a cross-sectional view of the heat dispersion device with holes therein; FIG. 8 is a cross-sectional view of the heat dissipation device with holes therein. FIG. 9 is a cross-sectional view of an encapsulated device with a heat dispersion device with holes on both sides of the attached chip; FIG. 10 is a cross-sectional view of an encapsulated device with a recessed device; FIG. 11 is a sectional view of the heat dispersion device and the lead frame. Explanation of main symbols 12: Mounting pad 14: Lead frame 16: Chip 22: Small graphite plate

Claims (1)

[Claims] A package for removing heat from a silicon semiconductor chip, the package having a lead frame electrically interconnected with the chip and the outside of the package, the chip being attached to the lead frame, and further comprising: a heat spreader disposed adjacent to the chip, the lead frame being disposed between the chip and the heat spreader, the heat spreader being made of silicon carbide and having a surface area larger than the surface area of the chip. the heat spreader has a coefficient of thermal expansion approximately approximating the coefficient of thermal expansion of the chip, and further includes means for bonding the heat spreader to the lead frame to reduce thermal resistance therebetween. a plastic layer formed around the chip, the heat spreader and the lead frame, the plastic layer being encapsulated such that the heat spreader is completely encapsulated and the lead frame is encapsulated; a package extending outwardly therefrom to provide interconnection between the chip and the exterior of the package;