JPS6120477A - Double scanning television receiving set - Google Patents

Abstract

PURPOSE:To enable to avoid vertical movement of a picture due to changing of mode by providing a mode changing circuit, making correction of vertical position of a picture interlocking withe changing of mode and thereby suppressing vertical movement of the picture due to changing of mode. CONSTITUTION:In the case where the same vertical synchronizing signal is used in respective mode, a picture formed by video signals SN1 and Si is formed higher than a picture formed by a video signal SN1' by 1/4 scanning line interval and 5/4 scanning line interval interlace respectively. However, when video signals SN1', SN1 and Si are supplied to an image receiving tube, signals VD2B, VD2A and VD1 are supplied from a delay circuit 29 to a deflecting circuit 30. Accordingly vergical position is corrected to form a picture formed by video signals SN1 and Si in the lower position of a picture formed by the video signal SN1 by 1/4 scanning line interval and 5/4 scanning line interval in interlace respectively. Accordingly, picture made by video signals SN1', SN1 and Si are formed conformably.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a double scan television receiver which is supplied with a non-interlaced video signal and is capable of non-interlaced display.

BACKGROUND TECHNOLOGY AND PROBLEMS Generally, in a screen display using an interlaced method, when the number of scanning lines is 525, one field is composed of 262.5 lines, and screen flicker is suppressed by transmitting this at 60 Hz. Further, in order to obtain vertical resolution, the next field is scanned with a shift of ten scan line intervals.

However, in this case, even though macroscopically the number of images is 60 per second, microscopically one scanning line lights up every five seconds, and the display cycle is six seconds.

Therefore, the light emission of this one scanning line flickers, which is visually perceived as so-called flicker. That is, line flicker exists.

In order to reduce this line flicker, the display period of one scanning line may be made shorter than six seconds.

Therefore, conventionally, a double-scanning Te1novision receiver has been proposed in which, for example, double-speed scanning is performed at twice the horizontal frequency. In this case, the display period for both lines is 4 seconds, and screen flicker and line flicker are not felt.

In order to perform double-speed scanning in which the horizontal frequency is doubled, the interlaced video signal is converted into a non-interlaced video signal in which the horizontal wave number is doubled and is supplied to the picture tube.

This conversion method is also described in Japanese Unexamined Patent Publication No. 59-40771, and a border method is proposed in FIGS. 1 and 2 that uses a line memory.

First, the system shown in Figure 1 predicts that the video signal of the previous scanning line and the next scanning line are the same, and uses the video signal of the previous scanning line as it is as an interpolation signal. It is a method of value prediction.

In the figure, (1) indicates an input terminal, and an interlaced video signal Si (shown in FIG. 3A) is supplied to this input terminal fi+. Further, (2) and (3) are line memories, respectively, and the read speed is twice the write speed.

In addition, (4th and (5th) are respective changeover switches, and
Its state is switched every H (one horizontal period), and when the changeover switch (4) is switched to one side of notes January 2) and (3), the changeover switch (5) is switched to the other side. In this case, the video signal Si supplied to the input terminal (11) is written to memo January 2) and (3) alternately for each IH, and the memo January 2) and (3)
The IH portion of the video signal written to the previous IH is read out twice from the other memory (3) and (2) to the IH that is written to one of the IHs, and this is sent to the output terminal (
6). Therefore, in this case, the output terminal (6) is supplied with the video signal 5NI (shown in FIG. 3B) with the horizontal frequency doubled, in which the video signal of each scanning line of the video signal Si is repeated twice with a period of +H. ) is obtained.

In addition, what is shown in Figure 2 is that the video signal of the scanning line that should be interpolated is predicted to be the arithmetic average of the video signals of the scanning lines before and after it, and this video signal is used as the interpolation signal, which is the so-called average value. It is a method of prediction.

In the figure, (2A) and (38) are line memories, respectively, (4A) and (5A) are changeover switches,
In FIG. 1, the Neo, memories (2) and (3), and selector switches (4) and (5) operate in the same way. Therefore, two consecutive video signals are obtained from the changeover switch (5A) with a period of video signal strength of each scanning line of the input video signal Si<4H. This video signal is supplied directly and via a delay line (7) having a delay time of +H to an adder (8). The adder (8) outputs the sum of these two video signals, which is adjusted to the 10th level by the level 11 adjuster (9) and then supplied to the output terminal (6). Therefore, in this case, the output terminal (6) includes the video signal of each scanning line of the video signal St, this video signal, and the following video signal.
A video signal 5ur in which the horizontal frequency is doubled and the video signal is the arithmetic average of the two video signals and is obtained alternately every +H.
(illustrated in FIG. 3C) is obtained.

If the video signals SNI and Snose thus obtained are supplied to the picture tube and double-speed scanning is performed, the surface flicker and line flicker as described above will not be felt.

However, the above video signals SNI and Sai
A double-scan television receiver that uses double-speed scanning has the following drawbacks.

First, when using the video signal SNI whose interpolated signal is obtained by the previous value prediction method shown in Figure 1, two scanning lines of the same video signal continue, so the component in the diagonal direction has a step-like shape. becomes. This is not obvious when it is a still image, but
In moving images, the viewer's eyes follow the movement, which causes a considerable deterioration in image quality. This increases as the screen size increases.

In addition, in Figure 2, the video signal No. 18 SNr whose interpolated signal was obtained by the Bozu average value prediction method is used, the video signal of the interpolated scanning line is the arithmetic average of the scanning lines before and after it. Therefore, due to this integral action, for example, the step-like appearance of the component in the diagonal line direction is alleviated compared to the example in FIG.

However, this video signal Ssr is the video signal Ssr obtained in the example of FIG. The signal SNI is further filtered through a vertical low-pass filter (
+? ) is) te+ ), so
The step response in the vertical direction deteriorates, and the vertical resolution deteriorates compared to the example shown in FIG.

That is, the step response of the scanning line on the /l-A' cotton line of the screen as shown in FIG. 4 is as shown in FIG. In FIG. 5, "°ζ, 10" corresponds to the scanning line of the odd field, and "x" corresponds to the scanning line of the even field. The one shown in figure B is the first
This is when the video signal sN, whose interpolation signal was obtained by the previous value prediction method shown in the figure, is used, and it rises at two lines. On the other hand, the one shown in Figure C is a video signal SNr whose interpolated signal is obtained by the average value prediction method shown in Figure
This is when using 3 lines. Moreover, what is shown in FIG. 2A is a case where an interlaced video signal Si is used.

As described above, according to the prior value prediction method as shown in FIG. 1, the components in the diagonal direction, such as the side EF of the diagonal pattern shown in FIG. 7, become stepwise, thereby causing image quality deterioration.

On the other hand, according to the neo-average prediction method shown in FIG. 2, this image quality deterioration is alleviated due to the integral effect, but the resolution in the vertical direction is degraded. For example, when considering a window frame pattern as shown in FIG. 6, the resolution of sides AB and CD deteriorates, resulting in so-called "blur".

In this way, the previous value prediction method shown in Figure 1 and the average value prediction method shown in Figure 2 each have their drawbacks, and conventionally these two modes have not been combined based on the image properties. It is proposed to switch accordingly.

However, if the two modes are simply switched, the image will move up and down due to the switching, giving the viewer an unpleasant feeling. That is, the positions indicated by arrows in FIG. 3B and C overlap the corresponding maximum brightness positions, but when the same vertical synchronization signal is used in the two modes, Signal 3N+
The image is formed upward by ten scan line intervals in the interlace. Therefore, the image moves up and down when the mode is switched.

Note that the maximum brightness position corresponding to the arrow 141 for the third prisoner is also shown, but if the same vertical synchronization signal is used as described above, for example, the image based on the video signal SNf will be different from the image based on the video signal Si. is formed upward by the horizontal scan line spacing in the interlace. Therefore, for example, when switching between images based on the video signals Ssr and St, the images also move up and down.

OBJECTS OF THE INVENTION In view of the above, the present invention is designed to avoid vertical movement of an image due to mode switching.

Summary of the Invention In order to achieve the above object, the present invention corrects the vertical position of an image in conjunction with mode switching to suppress vertical movement of the image caused by mode switching. Therefore, vertical movement of the image due to mode switching is avoided.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIG.

In the figure, am is an antenna, (11) is a tuner,
(12) is an intermediate frequency amplifier, (13) is a video detection circuit, and an interlaced video signal Si (shown in FIG. 3A) is obtained from the detection circuit (13).

This video signal St is converted into a digital signal by an A/D converter (14) and then supplied to a double speed conversion circuit (15). This conversion circuit (15) includes a memory (RAM) (15a) and (1) having a storage capacity of 9 for one horizontal period (IH).
5b), changeover switches (15c) and (15d). The selector switch <15c) is switched to the memory (15a) and (15b) side for each IH, while the selector switch (15d) is switched to the opposite side.

In addition, a write clock pulse is supplied to the memory selected by the changeover switch (15c), and a readout clock pulse of twice the frequency is supplied to the memory whose power is selected by the changeover switch (15d). is supplied.

The video signal Si is transferred to l via the changeover switch (15c).
Memory (15a) and (15b) for 18 minutes every H
is supplied to the memory (15) for writing.
b) and (Is, +), the 18-minute video written to the IH immediately before II1jj- is +I] with a period of 2
It is read out several times in succession, and this is the changeover switch (15d).
). In other words, this changeover switch (15
d), the signal of each scanning line of the video signal Si is a video signal 5NI (Fig. 3B
) is obtained. That is, this video signal Si is
Alternatively, the scanning line signal of t&) is used as an interpolation signal.

Switching of the changeover switches (15c) and (15d), writing to and reading from memories (15a) and (15b) are controlled by a control circuit (16). This control circuit (16)
is supplied with a horizontal synchronization signal (ID) and a vertical synchronization signal VD separated from the video signal St by a synchronization separation circuit (17), and is controlled based on these signals.

The video signal SNI obtained from the changeover switch (15d) is supplied to the fixed terminal on the A side of the changeover switch (18).

Further, this video signal SNI is directly supplied to an adder (19), and is also supplied directly to a delay line (20) having a delay time of +H.
) to an adder (19), and the output signal from this adder (19) is then sent to a level adjuster (21).
After the signal is divided by the level, it is supplied to the fixed terminal on the B side of the changeover switch (18). In other words, this fixed terminal on the B side has
A video signal 5Ni (shown in FIG. 3C) that alternates every +H between the signal of each scanning line of the video signal sI and the arithmetic average of the two signals, this signal and the signal of the scanning line following this signal. is obtained. In other words, this video signal SNf is an interpolated signal obtained by arithmetic averaging W of the previous and subsequent scanning lines.

In addition, the signal obtained from the changeover switch (18) is D/A
After being converted into an analog signal by the converter (22), it is supplied to the B side fixed terminal of the changeover switch (23). Further, the video signal si is supplied from the video detection circuit (13) to the fixed terminal on the A side of the changeover switch (23). Then, ζ, the signal obtained from this changeover switch (23) is sent to the amplifier (2
4) to the °C picture tube (25).

Further, in FIG. 8, the control circuit (16) outputs pulse signals PH and P2H synchronized with the horizontal synchronizing signal HD and having frequencies that are once (fo) and twice (2f'H) the horizontal frequency, respectively, The signals are supplied to fixed terminals on the A side and B side of the changeover switch (26), respectively. This changeover switch (2
6) is connected to the aforementioned changeover switch (23), and when the changeover switch (23) is switched to the A side and the B side, the changeover switch (26) is also switched to the A side and the B side.

The pulse signal obtained from this changeover switch (26) is supplied as a horizontal synchronizing signal to a horizontal deflection circuit (27), and this deflection circuit (27) supplies a horizontal deflection signal to a deflection coil (28).

Further, in FIG. 8, the vertical synchronization signal V obtained from the synchronization separation plane 1ifi (17) is supplied to the vertical deflection circuit (30) via the delay circuit (29), and this deflection circuit (3
0) supplies a vertical deflection signal to the deflection coil (28).

Here, the delay circuit (29) is configured as shown in FIG. 9, for example. In the same figure, <31a), (31b
), (31c) and (31d) are D flip-flops, and the vertical synchronizing signal Vt+ (101st MI
(shown in Figure C) is supplied. Also, flip-flops (3
The signals obtained at the Q# children of
1c) and (31d). Also,
The terminal (35) is supplied with a pulse signal P7H (shown in Figure 1B) obtained from the control circuit (I6), and after being inverted by the inverter (36), the flip-flops (31a) and (31b) and (31c) as a clock signal. In addition, the most significant bit (MS) of the read address is connected to the terminal (37) by the control circuit (1G).
A signal Psss (!!810 shown in FIG. A) of I3) is supplied, which is supplied to the flip-flop (31d) as a clock signal. Note that the signal PMSB may be supplied to the terminal (35). With the above configuration,
At the Q terminal of the flip-flop (31a), a signal VD1 that appears to be distorted as shown in Figure 10 is obtained, and the flip-flop (31a)
As shown in figure E, the signal VD2^ delayed by IH from the signal VDI is obtained at the Q terminal of 31c), and furthermore, the signal VD2^ delayed by IH from the signal VDI is obtained at the Q terminal of the flip-flop (31cl).
Signal ■fn delayed by H from D1
No. VD2B is obtained. These signals V Di % V
D28 and VD2B are supplied to the switch circuit (3B). This switch circuit (38) has switching switches (18) and (23) from terminals (39) and (40), respectively.
Switching information 311m and S 123 are supplied. The output of the switch circuit (38) is a signal MDI when the changeover switch (23) is switched to the A side.
However, when the selector switch (23) is switched to the B side and the selector switch (18) is switched to the A side, the signal VD2A is output, and when the selector switch (23) is switched to the B side, the selector switch (18) is switched to the B side. When switched to , the signal VD2B is obtained respectively. and,
These signals are obtained at the terminal (41), which is used as the output of the delay circuit (29).

The example in FIG. 8 is configured as described above, and has a changeover switch (23
) is switched to the A side, the interlaced video signal Si is supplied to the picture tube (25), and the changeover switch (26) is switched to the A side and the pulse signal PM is supplied to the deflection circuit (27). The picture tube (2
5), an interlaced image is displayed using the video signal St.

Further, when the changeover switch (23) is switched to the B side and the changeover switch (1B) is switched to the A side, the non-interlaced video signal SNI is supplied to the picture tube (25), and the changeover switch ( 26) is switched to the 13 side, and the pulse signal P2M is sent to the deflection circuit (27
), the picture tube (25) receives the video signal SN.
A non-interlaced image is displayed using I.

Further, when the changeover switch (23) is switched to the B side and the changeover switch (18) is switched to the B side, the picture tube (25) is supplied with a non-interlaced video signal S'SHF, and Changeover switch (2
6) is switched to the 13 side and the pulse signal P2)1 is supplied to the deflection circuit (27), so that a non-interlaced image is displayed on the picture tube (25) by the video signal SNf.

By the way, as mentioned above, when the same vertical synchronization signal is used in each mode, li! due to the video signal 5IIC! Images based on the video signals SNI and SI are formed above the image by ten scanning line intervals and ten scanning line intervals 4-1, respectively, in the interlace.

However, in the example of FIG. 8, the video signals SNi, S
When NI and SI are supplied to the picture tube (25), the delay circuit (29) sends the husband signal VD28 to the deflection circuit (30).
%VD2^ and VDI are supplied as vertical synchronization signals. Therefore, the vertical position of the image based on the video signal SNi is corrected so that the images based on the video signals SNI and Si are formed on one side by an interval of 10 scanning lines and an interval of + scanning line in interlacing, respectively. Therefore, the video signal SN
Images by F, SNI and St are formed in unison.

Therefore, according to the example shown in FIG. 8, even if the mode is changed using the changeover switches (23) and (18), there is no vertical movement of the image, and there is no fear of causing discomfort to the viewer.

Next, FIG. 11 shows another embodiment of the present invention.

The example in FIG. 11 uses a two-beam type picture tube, that is, a picture tube in which two electron beams are scanned simultaneously in the vertical direction with an interval of ten times the scanning line interval for fluorescence enhancement. This is an example of non-interlaced display. In FIG. 11, parts corresponding to those in FIG. 8 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

The video signal Si obtained from the video detection circuit V8 (1, 3) is supplied via an amplifier (42) to the first cathode 1 associated with the first electron beam of the C picture tube (43).

Further, this video signal St is supplied to the fixed terminal on the B side of the changeover switch (44).

Further, this video signal Si is directly supplied to an adder (45) and is connected to a delay line (46) having a delay time of IH.
) to the adder (45). This adder (
The output signal of 45) is set to an odd level by the level adjuster (47) and is supplied to the fixed terminal on the C side of the selector switch (44). is said to be electrically floating.

The signal obtained from the changeover switch (44) is sent to the amplifier (48).
) to the second electron beam F K 2 of the picture tube (43).

Further, the horizontal synchronizing signal HD obtained from the synchronizing branch circuit (17) is supplied to a water type deflection circuit (49), and the horizontal deflection signal is supplied from this deflection circuit (49) to the deflection coil (50).

Further, the vertical synchronization signal Vo obtained from the synchronization separation circuit (17) is the CI! of the changeover switch (51). This vertical synchronizing signal VD is supplied to the fixed terminal of the C changeover switch (51) via a delay line (52) having a delay time of 1H.
) is supplied to the fixed terminal on the B side of the delay line (52).
The signal is supplied to the fixed terminal on the A side of the changeover switch (51) via a delay line (53) having a delay time of +H. The changeover switch (51) is the changeover switch (44)
When the selector switch (44) is switched to the A side, B side and C side, the selector switch (51) is also switched to the A side, B side and C side. .

A signal obtained from the changeover switch (51) is supplied as a vertical synchronization signal to a vertical deflection circuit (54), and the deflection circuit (54) supplies a vertical deflection signal to the deflection coil (50).

The example in FIG. 11 is constructed as described above, and when the changeover switch (44) is switched to the A side, the current scanning line signal of the video signal 3i is applied to the first cathode of the picture tube (43). At the same time, the second cathode 2 has a scanning line (
No. 11 will not be supplied in any way. Therefore, an interlaced image is displayed on the picture tube (43) by the first electron beam.

Further, when the changeover switch (44) is switched to the B side, the video signal S is applied to the first cathode Ki of the picture tube (43).
The current scanning line signal of the video signal Si is supplied to the second cathode 2 as well as the current scanning line signal of the video signal Si. Therefore, at this time, the previous (or 18t) scanning line signal is supplied as an interpolation signal, and a non-interlaced image is displayed by the first and second electron beams.

Further, when the changeover switch (44) is switched to the C side, the video signal S is applied to the first cathode of the picture tube (43).
The current scanning line signal of i is supplied, and at the same time, a signal obtained by averaging the current scanning line signal and the scanning line signal before IH is supplied to the second cathode.

Therefore, at this time, an arithmetic average of the preceding and succeeding scanning lines is supplied as an interpolation signal, and a non-interlaced image is displayed by the first and second electron beams.

By the way, in this case, assuming that the same vertical synchronization signal is used, the display when the changeover switch (44) is switched to the A side, the B side, and the C side, that is, ■ interlaced display, ■
In both non-interlaced display where a previous (or subsequent) scanning line signal is supplied as an interpolation signal, and non-interlaced display where an arithmetic average of the previous and subsequent scanning line signals is supplied as an O-interpolation signal, the image position is It will be different. That is, FIG. 12 A, B, and C show the image displays of display ■, ■, and @, respectively, where "□" indicates the black level, roJ indicates the white level, and "Yu" indicates the intermediate level. It shows. The positions indicated by arrows in the same figure indicate the corresponding maximum brightness positions, and as is clear from this, the images with displays ■ and ■ are different from the image with display O due to the ten scanning line spacing in interlacing and It is formed upward by ten scan line intervals.

However, in this example in Fig. 11, the changeover switch (4
4) is switched to the A side, the 8th case, and the C side, respectively, the changeover switch (51) is switched to the A side, the B side, and the C side, respectively, and the vertical synchronization signal V, ) is delayed by +H, respectively.
A signal obtained by delaying the vertical synchronizing signal VD by +H and the vertical synchronizing signal VD are respectively used as vertical synchronizing signals in a vertical deflection circuit (54).
supplied to Therefore, for 1illIII of display O, the images of display ■ and 0 are formed on one side by ten scanning line intervals and three scanning line intervals in interlacing, respectively. Therefore, the images of display O1■ and ■are formed in agreement.

Therefore, according to the example in FIG. 11, the changeover switch (44
) Even if the mode is switched by switching the mode, the image does not move up and down (there is no risk of causing discomfort to the viewer).

In the above-described embodiment, the vertical synchronization signal is delayed and the vertical position of the image is corrected, but the vertical position may be corrected by adding a DC component to the vertical deflection signal.

Effects of the Invention As is clear from the embodiments described above, according to the present invention, the vertical position of the image is corrected in conjunction with the display mode switching, thereby suppressing the vertical movement of the image caused by the mode switching. Therefore, vertical movement of the image due to mode switching is avoided, and there is no possibility of causing discomfort to the viewer.

[Brief explanation of the drawing]

Figures 1 and 2 are configuration diagrams showing conventional examples, and Figures 3--
7 is a diagram for explaining each, FIG. 8 is a block diagram showing an embodiment of the present invention, FIG. 9 is a block diagram showing an example of a delay circuit, and FIG. 10 is a diagram for explaining the same. , FIG. 11 is a block diagram showing another embodiment of the present invention, and FIG. 12 is a diagram for explaining the same. (13) is a video detection circuit, (15) is a double speed conversion circuit (1
7) is a synchronous separation circuit, (18) (23) and (26
) are changeover switches, (25) is a picture tube, (28) is a deflection coil, (29) is a delay circuit, and (30) is a vertical deflection circuit. Figure 2 Figure 3

Claims (1)

[Claims] In a double-scan television receiver that is supplied with an interlaced video signal and displays non-interlaced images, the scanning line signal before or after the current scanning line is used as an interpolation signal, or the scanning line signal before and after the current scanning line is arithmetic. The present invention is characterized in that a mode switching circuit is provided to switch whether the averaged value is used as an interpolation signal, and the vertical position of the image is corrected in conjunction with the mode switching to suppress vertical movement of the image caused by the mode switching. A double-scan television receiver.