JPS61203552U - - Google Patents
Info
- Publication number
- JPS61203552U JPS61203552U JP1985088038U JP8803885U JPS61203552U JP S61203552 U JPS61203552 U JP S61203552U JP 1985088038 U JP1985088038 U JP 1985088038U JP 8803885 U JP8803885 U JP 8803885U JP S61203552 U JPS61203552 U JP S61203552U
- Authority
- JP
- Japan
- Prior art keywords
- external lead
- lead electrodes
- groove
- semiconductor device
- held
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000008188 pellet Substances 0.000 claims description 2
- 239000011521 glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Description
第１図は本考案の一実施例を示す断面図、第２
図は従来の半導体装置を示す断面図である。 １……半導体ペレツト、２，３……外部導出リ
ード、４，５……スラグリード電極、６，７……
アウタ―リード、８，９……Ｖ溝、１０……ガラ
ス管。
図は従来の半導体装置を示す断面図である。 １……半導体ペレツト、２，３……外部導出リ
ード、４，５……スラグリード電極、６，７……
アウタ―リード、８，９……Ｖ溝、１０……ガラ
ス管。
Claims (1)
- 半導体ペレツトを一対の外部導出リード電極に
より挾着した半導体装置において、前記外部導出
リード電極の側面にＶ溝を形成することを特徴と
する半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985088038U JPS61203552U (ja) | 1985-06-11 | 1985-06-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985088038U JPS61203552U (ja) | 1985-06-11 | 1985-06-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61203552U true JPS61203552U (ja) | 1986-12-22 |
Family
ID=30640803
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985088038U Pending JPS61203552U (ja) | 1985-06-11 | 1985-06-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61203552U (ja) |
-
1985
- 1985-06-11 JP JP1985088038U patent/JPS61203552U/ja active Pending