JPS6120218B2 - - Google Patents

Info

Publication number
JPS6120218B2
JPS6120218B2 JP53047732A JP4773278A JPS6120218B2 JP S6120218 B2 JPS6120218 B2 JP S6120218B2 JP 53047732 A JP53047732 A JP 53047732A JP 4773278 A JP4773278 A JP 4773278A JP S6120218 B2 JPS6120218 B2 JP S6120218B2
Authority
JP
Japan
Prior art keywords
control
computer
opening
closing operation
holding circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53047732A
Other languages
Japanese (ja)
Other versions
JPS54140435A (en
Inventor
Terunobu Myazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4773278A priority Critical patent/JPS54140435A/en
Publication of JPS54140435A publication Critical patent/JPS54140435A/en
Publication of JPS6120218B2 publication Critical patent/JPS6120218B2/ja
Granted legal-status Critical Current

Links

Description

【発明の詳細な説明】 本発明は電力系統制御の計算機による直接制御
装置に係り、特に計算機が異常時に於ける制御信
頼度の向上に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a computer-based direct control device for power system control, and particularly to improving control reliability when the computer is abnormal.

一般に計算機が設置される電気所の環境は通常
の状態に於ては支障ないが、系統事故、例えば雷
による1線地絡事故時等は、電気所構内のアース
線へ大電流が流れ、従つてアース点電位が異常に
上昇し計算機等の弱電機器に対して好ましくな
く、特にそのような条件下に於ては計算機が異常
動作する可能性がある。
Generally speaking, the environment of electrical stations where computers are installed does not pose any problems under normal conditions, but in the event of a system fault, such as a one-wire ground fault due to lightning, a large current flows to the ground wire within the electrical station premises, causing As a result, the earth point potential rises abnormally, which is unfavorable for weak electrical equipment such as computers, and particularly under such conditions, computers may operate abnormally.

このため、電力系統制御装置等に計算機を使用
する場合は万一、計算機が異常となつても制御出
来ることが必要である。
Therefore, when using a computer in a power system control device or the like, it is necessary to be able to control the computer even if it becomes abnormal.

本発明は最も制御を必要とする時に、最もきび
しい環境条件下に置かれる計算機が、万一異常動
作しても必要最少限の系統制御を確保するように
した計算機による直接制御方式である。
The present invention is a direct control method using a computer that ensures the minimum necessary system control even if a computer operating abnormally is placed under the most severe environmental conditions when control is most needed.

以下、その具体例について電力系統分離時に於
ける周波数低下対策としておこなう負荷しや断方
式に例をとり詳細説明をおこなう。
Hereinafter, a detailed explanation will be given of a specific example of this method, taking as an example a load shedding and disconnection method that is used as a countermeasure against frequency drop when power systems are separated.

第1図に示すように、電力系統A,Bが連系線
Tにより連系して運転されている時、連系線Tに
事故が発生し、A,B両系統が分離された場合に
は、Bの系統内に於ては連系線Tを通して送られ
ていた電力PTが不足しB系統に於ける周波数が
低下する。周波数の低下は周知の如くタービン発
電機のタービン翼の振動等の点からこれを防止す
る必要があり、B系統に於ては緊急に負荷しや断
をおこなつて発電力の不足を解消し、周波数の回
復をはかる事が通常行なわれている。即ち、B系
統内に於ける発電機G1〜Goによる発電量の総和
に等しくなるような負荷線のみを残して他をしや
断すればよい。
As shown in Figure 1, when power systems A and B are operated interconnected by interconnection line T, if an accident occurs on interconnection line T and both systems A and B are separated, In this case, the power P T sent through the interconnection line T in the B system becomes insufficient, and the frequency in the B system decreases. As is well known, it is necessary to prevent a decrease in frequency from the viewpoint of vibrations of the turbine blades of the turbine generator, etc., and in the B system, load and disconnection are carried out urgently to resolve the shortage of power generation. , frequency recovery is usually performed. That is, it is only necessary to leave only the load lines that are equal to the total amount of power generated by the generators G 1 to G o in the B system and cut off the others.

第2図aは従来からおこなわれている制御フロ
ーを示すもので一定時間毎に計算をスタートさ
せ、系統が分離されていない時は連系線T、負荷
線L1〜Lo等各点の潮流量を取込み、これをもと
に最適なしや断負荷線を算出する。算出方法とし
ては例えば、連系線Tの汐流PTに見合う負荷線
汐流の組合せとする。
Figure 2a shows the conventional control flow. Calculations are started at regular intervals, and when the system is not separated, each point of the interconnection line T, load lines L 1 to L o , etc. Capture the tidal flow and calculate the optimum load line and disconnected load line based on this. The calculation method is, for example, a combination of load line tides that match the tide flow P T of the interconnection line T.

このようにして算出した制御対象負荷線を記憶
しておく。以上の事を時々刻々変化す汐流分布に
対して一定周期でおこない、最新の汐流分布にも
とづく最適負荷しや断回線グループのみを記憶し
ておき系統事故等による系統分離時は事前に算
出、記憶してある負荷線を直ちにしや断する。
The control target load line calculated in this manner is stored. The above steps are performed at regular intervals for the ever-changing tidal current distribution, and only the optimum load and disconnection groups based on the latest tidal current distribution are memorized and calculated in advance when the system is separated due to a system accident, etc. , immediately disconnect the memorized load line.

通常負荷線のしや断回路は第2図bに示すよう
に系統分離時閉路する(即ちトリガー信号)接点
1と、系統周波数が低下した時閉路する(即ちフ
エイルセーフ信号)接点2と、事前に算出し、記
憶されている接点3とを直列回路として各回線の
しや断器へ、しや断信号を送出している。
Normally, as shown in Figure 2b, a load line break circuit is connected to contact 1, which closes when the system is separated (i.e., a trigger signal), and contact 2, which closes when the system frequency decreases (i.e., a fail-safe signal). The calculated and stored contact point 3 is used as a series circuit to send a disconnection signal to each line disconnector.

このような従来の制御装置に於て、最適制御回
線の算出をおこなう計算機部分が異常となつた時
に不必要な制御がおこなわれるのを防止するた
め、従来第2図bでは、接点4を開路して直ちに
制御回路をロツクしていた。
In such a conventional control device, in order to prevent unnecessary control from being performed when the computer part that calculates the optimal control line becomes abnormal, the conventional control device in Fig. 2b opens the contact 4. The control circuit was immediately locked.

即ち、定常時に於ける計算機の異常により誤つ
た回線が記憶されている状態で制御指令が発せら
れのを、あらかじめ防止するため直ちに制御装置
の出力部分をロツクしていた。
That is, the output section of the control device is immediately locked in order to prevent a control command from being issued in a state where an incorrect line is stored due to an abnormality in the computer during normal operation.

このような事は、一般に計算機制御装置に於て
良く用いられている方法であるが、電力系統の電
気所に於ける系統制御装置等、に於ては前述の如
く最も制御を必要とする時に計算機が異常となり
易いため、従来の装置に対するロツク方式では不
具合であつた。
This is a method that is commonly used in computer control equipment, but as mentioned above, in system control equipment at electrical stations in power systems, it is often used when control is most needed. Since computers are prone to malfunctions, conventional locking methods for devices have been inconvenient.

本発明は、以上の点に鑑みて成されたもので、
その目的とするところは計算機異常時にも確実に
制御できる制御方式を提供するものである。
The present invention has been made in view of the above points, and
The purpose is to provide a control method that can be reliably controlled even when a computer malfunctions.

本発明においては計算機等装置の主要部が異常
時には、外部記憶用の回路のみを直ちにロツク
し、制御回路は一定時間(制御に必要な時間)の
后、ロツクする事により、必要最少限の制御を確
保しようとするものである。
In the present invention, when there is an abnormality in the main part of a computer or other device, only the external storage circuit is immediately locked, and the control circuit is locked after a certain period of time (time required for control), thereby minimizing necessary control. The aim is to ensure that

第3図は、本発明の一実施例を示す回路図であ
る。同図aに於て、10はデイジタル計算機で系
統条件やデータが入力部11を介して演算部
CPUへとりこまれる。CPUでは前述の汐流計算
によ最適回線が算出され、これを出力部12を介
して出力リレー13,13′へ出力する。
FIG. 3 is a circuit diagram showing one embodiment of the present invention. In the same figure a, 10 is a digital computer, and the system conditions and data are inputted to the calculation unit via the input unit 11.
It is taken into the CPU. The CPU calculates the optimal line by the above-mentioned tidal flow calculation, and outputs it to the output relays 13, 13' via the output section 12.

尚、16はCPU異常時に働らくリレーであ
る。同図bにおいて14は外部記憶用メモリー
で、例えばキープリレーが用いられる。14Cは
キープリレーの動作コイル、14Rは復帰用コイ
ルである。
Note that 16 is a relay that operates when the CPU is abnormal. In FIG. 1B, reference numeral 14 denotes an external storage memory, for example, a keep relay is used. 14C is a keep relay operating coil, and 14R is a return coil.

今、キープリレーを制御対象回線数だけ用意し
ておき、最適しや断回線の算出結果、しや断対象
となつた回線に対応するキープリレーのみを動作
状態とする。
Now, keep relays are prepared as many as the number of lines to be controlled, and only the keep relays corresponding to the lines that are subject to disconnection are put into operation based on the calculation result of the optimum line disconnection.

このため、14には計算機からの動作指令用接
点13a1と復帰指令用接点13a2が図のよう
に接続され一定時間毎のCPU演算結果を外部メ
モリー14に記載させておく、16は計算機が異
常時に動作する出力リレーであり、16a及び1
6bはリレー16が動作或いは、他の計算機異常
検出回路によつて閉する接点で平常時、16bが
閉路、16aが開路している。
For this reason, a contact 13a1 for operation commands and a contact 13a2 for return commands from the computer are connected to 14 as shown in the figure to record the CPU calculation results at regular intervals in the external memory 14. It is an output relay that operates, and 16a and 1
6b is a contact that is closed by the operation of the relay 16 or by another computer abnormality detection circuit, and under normal conditions, 16b is closed and 16a is open.

接点1a,1bは第2図bで述べたと同様の制
御指令のトリガー接点で、例えば系統分離時に1
aが閉、1bが開路する。
Contacts 1a and 1b are trigger contacts for control commands similar to those described in Fig. 2b, and for example, when the system is separated,
A is closed and 1b is open.

制御指令回路(第3図b右側シーケンス)は、
第2図bの場合と同様にトリガー信号1aと、フ
エイルセーフ信号2と、キープリレー14のリレ
ー14Cにより閉され、リレー14Rにより開さ
れるしや断器の操作接点3と、順序制御接点18
とより構成される。そして本発明においてはタイ
マー17の常閉限時復帰接点17bが接続され
る。常、13a1,13a2、14より成る記憶
回路は各操作接点3ごとに夫々設けられている。
この結果本発明によれば、従来はCPU異常時等
により直ちに接点4によつてしや断器制御指令回
路をロツクしていたものを、タイマー17の常閉
接点17bの働らきにより一定時限の間はロツク
せず、健全時にキープリレーに保持してある制御
対象回線を制御した后ロツクする。
The control command circuit (right sequence in Figure 3b) is
As in the case of FIG. 2b, the trigger signal 1a, the fail-safe signal 2, the operation contact 3 of the breaker which is closed by the relay 14C of the keep relay 14 and opened by the relay 14R, and the sequence control contact 18
It consists of In the present invention, the normally closed time limit return contact 17b of the timer 17 is connected. Usually, a memory circuit consisting of 13a1, 13a2, and 14 is provided for each operating contact 3, respectively.
As a result, according to the present invention, the normally closed contact 17b of the timer 17 locks the disconnection control command circuit for a fixed period of time, whereas in the past, the disconnection control command circuit was immediately locked by the contact 4 in the event of a CPU abnormality. It does not lock for a while, but locks after controlling the controlled line held in the keep relay when it is healthy.

尚、例えばキープリレーに保持してある回線に
対して一度に制御せず幾つかのグループに分けて
順次制御する場合一定時間毎に順次18,18′
接点を閉路させて制御する。このような場合は制
御対象数から決る所要最大時限后にタイマー17
を動作せればよい。
For example, if the lines held in a keep relay are not controlled all at once but are divided into several groups and controlled sequentially, 18 and 18' are sequentially controlled at regular intervals.
Control by closing the contacts. In such a case, the timer 17 is
All you have to do is make it work.

このように計算機異常時、直ちにロツクするの
は外部記憶回路のみとし、制御回路は制御に必要
な時間后、ロツクする事により健全時に於ける制
御対象回線の制御が必要最少限確保されることと
なる。この本発明によれば、計算機が最も誤動作
を起し易いときに、確実な制御が行なえる。
In this way, when a computer abnormality occurs, only the external storage circuit is locked immediately, and the control circuit is locked after the time required for control, thereby ensuring the minimum necessary control of the line to be controlled when the computer is in good condition. Become. According to the present invention, reliable control can be performed when the computer is most likely to malfunction.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は電力系統の構成図、第2図は本発明が
適用され得る従来方式による負荷しや断のフロー
としや断指令回路の1例を示す図、第3図は本発
明よる制御回路の実施例を示す構成図を示す。 3,3′……しや断器制御接点、1……トリガ
ー信号、2……フエールセーフ信号、17……タ
イマー、16……CPU異常検出接点、14……
キープリレー。
Fig. 1 is a diagram showing the configuration of an electric power system, Fig. 2 is a diagram showing an example of a load shedding command circuit and a flow of load shedding according to a conventional method to which the present invention can be applied, and Fig. 3 is a control circuit according to the present invention. 1 shows a configuration diagram showing an embodiment of the invention. 3, 3'...Shipping breaker control contact, 1...Trigger signal, 2...Fail safe signal, 17...Timer, 16...CPU abnormality detection contact, 14...
Keep relay.

Claims (1)

【特許請求の範囲】[Claims] 1 開閉動作をする機器を含む被制御部が健全で
ある時に、被制御部が異常となつた時に開閉動作
させるべき前記機器についての開閉操作指令を常
時計算し書き換え回路を介して出力して外部保持
回路に保持しておき、被制御部に実際に異常発生
した時前記の外部保持回路の保持内容にもとづい
て被制御部の前記の開閉動作をする機器に対して
開閉操作指令を与える計算機に於て、計算機異常
発生時直ちに外部保持回路の書き換えを阻止する
と共に、前記開閉動作機器が開閉動作するに要す
る一定時限経過してから前記外部保持回路をロツ
クし、記憶された開閉操作指令により前記機器が
開閉操作されることを阻止する事を特徴とする計
算機制御方式。
1. When the controlled part including the equipment that opens and closes is healthy, the opening/closing operation command for the equipment to be opened and closed when the controlled part becomes abnormal is constantly calculated, outputted via a rewriting circuit, and sent to the outside. A computer that is stored in a holding circuit and gives an opening/closing operation command to a device that performs the opening/closing operation of the controlled part based on the contents held in the external holding circuit when an abnormality actually occurs in the controlled part. When a computer error occurs, the external holding circuit is immediately prevented from being rewritten, and the external holding circuit is locked after a certain period of time required for the opening/closing operation device to operate, and the opening/closing operation command is stored. A computer control method characterized by preventing equipment from being opened or closed.
JP4773278A 1978-04-24 1978-04-24 Computer control system Granted JPS54140435A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4773278A JPS54140435A (en) 1978-04-24 1978-04-24 Computer control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4773278A JPS54140435A (en) 1978-04-24 1978-04-24 Computer control system

Publications (2)

Publication Number Publication Date
JPS54140435A JPS54140435A (en) 1979-10-31
JPS6120218B2 true JPS6120218B2 (en) 1986-05-21

Family

ID=12783505

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4773278A Granted JPS54140435A (en) 1978-04-24 1978-04-24 Computer control system

Country Status (1)

Country Link
JP (1) JPS54140435A (en)

Also Published As

Publication number Publication date
JPS54140435A (en) 1979-10-31

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