JPS61201510A - Semi-fixed delay line - Google Patents

Abstract

PURPOSE:To attain ease of adjustment of a delay time by providing an earth plate laminated on a substrate, >=2 insulating layers laminated on the earth plate and having different dielectric constant and a wire line laminated over the >=2 insulation layers. CONSTITUTION:The earth plate on the silicon substrate 6 is a superconductor made of niobium Nb formed by the thin film forming technology such as vacuum vapor deposition or sputtering. A wire line 1 having a projection 4 changed easily for its shape at its side face is formed on the plate 5 via the insulation layers, and the projection 4 and the wire 1 are thin superconductor films made of niobium Nb by using the thin film forming technology such as vacuum vapor deposition or etching. The 2nd insulation layer 2 between the projection 4 and the plate 5 is made of a material having a comparatively large dielectric constant such as pentoxide niobium Nb2O5 or strontium titanate SrTiO3. The 1st insulation layer 3 between the wireline 1 and the plate 5 is formed by using a material having a smaller dielectric constant than that for the 2nd insulation layer 2 such as silicon oxide SiO,SiO2 or polyethylene -CH2CH2-.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to delay lines.

(Prior art and its problems) In order for an electronic circuit to operate normally, delicate time relationships among various signals in the circuit must be set accurately. In particular, in logic circuits that require high-speed operation, if such settings cannot be made, it will be difficult to achieve high-speed operation.

A delay line is used for such settings because it allows fine adjustment of the delay time until the input signal is output.

FIG. 2 is a diagram showing the structure of a conventional delay line.

This is a distributed constant type delay line, and its delay time per unit length is given by /F. L and C are inductance and capacitance per unit length. Enameled wire 1 is placed on top of core 7 to increase L per unit length.
0 is tightly wound.

On this enamelled wire 10 there is an insulating layer 9, and further on this there is an outer conductor 8. (Written by Bessho, “Memory device engineering”,
Kyoritsu Shuppan, 1962, p. 176).

This delay line is mounted on the printed +-S board and used to adjust the signal propagation time between circuits. In use, the outer conductor 8 is grounded.

In recent monolithic ICs, there is a tendency to integrate more and more circuit components, and circuits that were configured on a printed circuit board including delay lines are now integrated as a single IC. In such an IC, in order to realize high-speed operation, it is necessary to adjust the signal delay within the IC. This adjustment is especially important in superconducting logic circuits that aim for ultra-high-speed operation.

However, the conventional delay line shown in FIG. 2 cannot be used in such an IC because it is difficult to integrate and it is difficult to change the delay time7. (Objective of the Invention) An object of the present invention is to provide a semi-fixed delay line that can be integrated with ultra high-speed logic such as a superconducting logic circuit and whose delay time can be easily adjusted after integration.

(Structure of the Invention) The present invention includes a grounding plate laminated on a substrate, two or more insulating layers having different dielectric constants laminated thereon, and two or more insulating layers having different dielectric constants.
A semi-fixed delay line comprising a line stacked over two or more insulating layers.

(Detailed explanation of configuration) The present invention will be described in detail below using the drawings.

FIG. 1 shows an example of the present invention, and FIG. 1(a) is a plan view, and FIG. 1(b) is a sectional view taken along the line AA' in FIG. 1 (al).

The ground plate 5 on the silicon substrate 6 is made of niobium (Nb) formed by thin film forming techniques such as vacuum evaporation and sputtering.
) and other superconductors. On this ground plate 5, with an insulating layer in between, a line 1 having protrusions 4 whose shape can be easily changed on the side surface is placed.
is formed. This protrusion 4 and the line 1 are also made of niobium (Nb).
It is a thin film of a superconductor such as, and is made using thin film formation techniques such as vacuum evaporation and etching. The second insulating layer 2 between the protrusion 4 and the ground plate 5 is formed of a material with a relatively large dielectric constant, such as niobium pentoxide (Nb, 0.) or strontium titanate (SrTiO=). The first insulating layer 3 between the line 1 and the grounding plate 5 is made of silicon oxide (870, 840,), polyethylene (-CH, CH, -), etc., which has a lower dielectric constant than the material forming the second insulating layer 2. made of materials. To create a structure in which the second insulating layer 2 is partially buried in the first insulating layer 3 as described above, there are various methods such as a step-off process.

(Embodiment) A delay line having such a configuration outputs an input signal after a delay time determined by 8Q. Here, l is the length of the delay line, μ is the magnetic permeability of the insulating layer, and ε is the effective dielectric constant of the insulating layer. The width of the track is X, the width of the protrusion is X7, the first part of the track part
The dielectric constant of the insulating layer 3 is ε1, and the dielectric constant of the second insulating layer 2 at the protruding portion is 6. Then, the effective dielectric constant ε is ε=(ε+x1+ttxt)/(Xt+xt).

Note that the magnetic permeability μ is almost the same as the magnetic permeability in vacuum, and is 4 x
X l O(henry/m ).

The first insulating layer 3 has a dielectric constant ε of 30. lX10” (
farad/fn), the signal delay time per unit length I in the line portion is 6.1 s x 10-' (m/m).

The second insulating layer 2 has a dielectric constant ε of 4×10′ (fa
rad/m), the width of the track 1 is 5 x 10-' (m), and the width of the protrusion 4 is 5 x 1.
0' (m), then! =1485X10-12(
farad/rrI), and the signal delay time is 43.2
X10” (see/m).This delay line
If the length i is 100XIO' (m)tc, a signal delay time of 4.32X10-'' (g!c) can be generated.

The width X of the protrusion 4 is laser trifled.
The effective dielectric constant ε can be changed by cutting the material with Therefore, setting the delay time necessary for the operation of the high-speed logic circuit can be easily achieved.

(Effects of the Invention) As described above, the present invention provides a superconducting semi-fixed delay line which can be easily integrated together with a superconducting integrated circuit and whose delay time can be adjusted. can do.

In addition, in the above explanation, the case where the track 1 with the protrusion 4 was used was described, but the first,
A semi-fixed delay line can similarly be obtained by placing the contacting boundary of the second dielectric under the line and trimming one side of the line in a concave manner to change the effective dielectric constant.

In addition, although the above explanation deals with the case where superconductors are used in superconducting logic circuits and the lines and ground planes are superconductors, ordinary conductors can also be used in other high-speed logic circuits such as compound semiconductors as lines and ground planes. The effect of a semi-fixed delay line can be obtained even when used in

[Brief explanation of drawings]

FIG. 1 (al, (bl) is an explanatory diagram of an embodiment of the present invention, and FIG. 2 is an explanatory diagram of a conventional delay line. In the figure, 1...line, 2...second insulating layer, 3 -...first insulating layer, 4...protrusion, 5...ground plate, 6...substrate, 7
...Core, 8...Outer conductor, 9...Insulating layer, 10
...It is an enameled wire. Agent Patent attorney μτ −′, Houki 1 Figure (a) (b) −≦;242 Toto 2:

Claims (1)

[Claims] A semi-fixed delay characterized by comprising a grounding plate, two or more insulating layers having different dielectric constants laminated thereon, and a line laminated across the two or more insulating layers. line.