JPS61199397A - Loop circuit for channel - Google Patents

Abstract

PURPOSE:To obtain a loop circuit with small power consumption regardless of the source voltage of the channel by limiting the value of current flowing through the lines to a prescribed value and less when the voltage between the lines is below a specified voltage and by releasing the limitation when the voltage once exceeds the specified voltage, and thereby maintaining an approximately constant resistance. CONSTITUTION:In case the voltage between the signal line 100 and 200 rises, the base voltage of a transistor Q0 is limited by a reference diode ZD1, and the current of the transistor Q0 is also limited. That is, the loop circuit is limited in a state of the first limit-current. When a voltage lifting power source is connected between the signal lines 100 and 200 and the voltage between the two exceeds the specified value, a current flows through a reference diode ZD0 and a resistor R2, and a current is supplied to the base electrode of a transistor Q1 turning the transistor Q1 on. Consequently, the base voltage of the transistor Q0 is determined by resistors R0 and R1, and the current that flows through the transistor Q1. That is, the current flowing in the loop circuit is released from the limit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a communication path circuit for analog signals connecting between telephone exchanges, and particularly to a communication path loop circuit used in a trunk circuit. More specifically, the present invention relates to a communication loop circuit that has high impedance for AC signals and low resistance for DC signals.

〔overview〕

The present invention limits the current when the input voltage is below a reference voltage under normal conditions in a communication loop circuit that has high impedance for AC signals and low resistance for DC signals. Once this voltage exceeds the reference voltage due to use of the BB main power supply or other reasons, the current restriction is removed and the circuit configuration exhibits constant resistance characteristics, thereby reducing the power consumption of the loop circuit for the communication path. .

[Conventional technology]

FIG. 2 shows a circuit diagram of a first conventional speech path loop circuit.

In this conventional example, the loop circuit for the communication path (hereinafter simply referred to as the loop circuit) uses a special relay L for the communication path, which has a high impedance for AC signals and about 440Ω for DC signals. , signal line 10 connected to the line
It connected between 0 and 200. A varistor (2) was connected in parallel to this relay L to protect the contacts when DC is cut off in a counter device connected to terminals A and B via a line.

DC current from terminals A and B is connected to DC interrupting capacitor C.
It is shut off with 01C1.

FIG. 3 shows a circuit diagram of a second conventional speech path loop circuit.

In this example, an electronic circuit is used in place of the relay L of the first conventional example described above, and high AC impedance and low DC resistance are realized by the i-transistor QO.

The diode DO-03 constitutes a rectifier circuit that allows current to flow in the same direction to the transistor 00 even if the polarity of the DC voltage on the signal line 100, 200 is reversed. In other words, the current from the signal line 100 is passed through the diode D.
O, transistor 00, resistor R7 and diode D3
The current from the signal line 200 is caused to flow into the signal line 100 through the diode D2, the transistor QO1 resistor R7, and the diode D1.

By appropriately selecting the constants of the resistors RIO, R11, R7, capacitor CIO, and transistor 00, it is possible to obtain the same characteristics as the relay L in the first conventional example, that is, the characteristics of high AC impedance and low DC resistance. .

The constant voltage diode ZD10 is for controlling the current flowing through the loop circuit. When the DC current in the loop circuit increases, the voltage applied to the resistor R7 increases, increasing the base voltage of the transistor QO. The constant voltage diode Z010 keeps this base voltage at a constant voltage,
The current flowing through the loop circuit can be controlled. Therefore, this constant voltage diode ZD40 is connected to the signal line 10.
When an abnormal voltage between 0.200 and 0.200 is applied, excessive current is prevented from flowing through the transistor 00, and destruction of the transistor QO is prevented.

However, since the increase in the current flowing through this loop circuit is limited, the voltage applied to the loop circuit due to the difference in the line conditions of the signal lines 100 and 200 is directly applied to the transistor 00.
It is added between the collector and emitter of.

Therefore, the power applied to the transistor 00 increases.

Here, the power consumption of the loop circuit will be explained.

FIG. 4 is a diagram showing an example of use of the loop circuit.

The power supply 5 of the mandrel rank 3 of the exchange is connected to the output rank 1 of the exchange via the relay 4 and the signal line 101.201.
A current (1) is supplied to the loop circuit 2 provided in the circuit. The voltage of power supply 5 is 48V, and the resistance value of relay 4 is 440
It is Ω.

The power consumption W of the loop circuit 2 in the first conventional example, that is, when the relay L is used, is the signal '! ffA101.20
If line resistance RL of 1 is 0Ω, then W, -resistance of relay L x (line current IL)2. Here, the line current ■ is the resistance of relay 4 + the resistance of relay L, so = 1.31 [W] - song (1)
'.

Next, the power consumption W2 of the loop circuit 2 when using the second conventional example is determined. The current flowing through loop circuit 2 is 30 m.
When limited to A, the power consumption w2 is: W2 - voltage of power supply 5 x line current ■.

- (line current IL) 2 x resistance of relay 4 - 48 x 0.0
3-(0,03)2X440-1.444 [W]
-Song-(2).

In this way, the second conventional example consumes approximately 80% less power than the first conventional example. That is, by limiting the line current, the power consumption of the loop circuit 2 can be reduced.

The above explanation is based on the line resistance RL of the signal line 1.01.20+.
is small, but when the line resistance R is large, it is common to use the booster power supply 6 (BB main power supply to supply current to the J channel circuit. In this case, the loop circuit 2
The power consumption will be explained below.

The line resistance R, becomes the limit resistance using the booster power supply 61
The case of 200Ω will be explained as an example. The power supply voltage from the power supply 5 and the booster power supply 6 is 98V. In this case, the power consumption W of the loop circuit 2 using the first conventional example is W, - resistance of relay L x (line current 1.)''
(3+, and line current ■1 is ■, - resistor line resistance RL of power supply voltage relay 4 + resistance of relay L, so #0.977 CW: l -m--
-(3)'.

The power consumption W4 of the loop circuit 2 using the second conventional example is: W4 - Supply voltage x line current I.

-(Line current IL) 2X L・-4 resistance = 98X0.
03-0.032X440'-2,544(W)
-+41.

In this way, the second conventional example consumes approximately 260% more power than the first conventional example. That is, when the boosted power supply 6 is used, the power consumption of the loop circuit 2 increases due to the line current being limited.

As described above, the conventional loop circuit has the disadvantage that power consumption increases either when the boosted power supply is not used or when the boosted power supply is used.

SUMMARY OF THE INVENTION An object of the present invention is to provide a loop circuit for a communication path that consumes less power regardless of the power supply voltage of the communication path.

[Means for solving problems]

The loop circuit for a communication path of the present invention is connected to two lines between telephone exchanges, and has a high impedance for AC signals and a low resistance for DC signals. means for limiting the current flowing through the line to below a predetermined value when the voltage between the two lines is below a predetermined voltage; The present invention is characterized in that it includes means for releasing the restriction caused by the square rooting means and maintaining a substantially constant resistance value.

[Effect]

The communication line loop circuit of the present invention limits the current for the -48V power supply line, and provides constant resistance for the line connected to the boosted power supply. The current limiting mode and constant resistance mode are automatically switched.

〔Example〕

FIG. 1 is a circuit diagram of a communication path loop circuit according to an embodiment of the present invention.

The anode terminal of the diode Do and the cathode terminal of the diode DI are connected to the signal line 100.

The cathode terminal of diode Do is connected to the cathode terminal of diode D2, and the anode terminal of diode DI is connected to the anode terminal of diode D3. The anode terminal of diode D2 and the cathode terminal of diode D3 are connected to signal line 200.

The connection point between the cathode terminal of diode DO and the cathode terminal of diode D2 is resistor 1? one end of o, the cathode terminal of the constant voltage diode ZDO, and the transistor QO
Connected to the collector terminal of The other end of the resistor RO is connected to one end of the resistor V1, the cathode terminal of the constant voltage diode ZD], one end of the resistor R3, one electrode of the capacitor C3, and the cathode terminal of the constant voltage diode ZD2.

The anode terminal of the constant voltage diode ZDO is connected to one end of the resistor R2. The anode terminal of the constant voltage diode ZD2 is connected to the heath terminal of the transistor QO.

The emitter terminal of transistor QO is connected to one end of resistor R7. The other end of the resistor R1 is connected to the collector terminal of the old transistor and one end of the resistor R4. The other end of the resistor R4 is connected to the base terminal of the transistor 02. The other end of the resistor R2 is connected to the collector terminal of the transistor 01, one end of the resistor R6, one electrode of the capacitor C2, and one end of the resistor R5. The anode terminal of the constant voltage diode ZD1, the other end of the resistor R3, and the other end of the resistor R5 are
Connected to the collector terminal of transistor 02. The emitter terminal of the transistor Q1, the other end of the resistor R6, the other electrode of the capacitor C2, the emitter terminal of the transistor 2, the other electrode of the capacitor C3, and the other end of the resistor R7 are connected to the anode terminal of the diode D1 and the diode D3. is connected to the connection point with the anode terminal.

A case where a -48V line is connected to the signal lines 100 and 200 will be explained. In this case, when the contacts 300 on the signal line 100 are closed, three DC loop circuits are formed. The first DC loop circuit includes a diode Do or D
2, Resistor RO1 Grinding resistor R1, Resistor R4, Transistor 02
is formed by the base electrode of transistor Q2, the emitter electrode of transistor Q2, resistor R7 and diode D3 or Dl. The second DC loop circuit is a diode DO or D2
, transistor (10 collector electrodes, transistor Q
It is formed by an emitter electrode of O, a resistor 7 and a diode D3 or Dl. The third DC loop circuit includes a diode Do or D2, a resistor RO1, a constant voltage diode Z
D2, the base electrode of l-transistor QO, formed by resistor R7 and diode D3 or Dl. Here, current mainly flows through the second DC loop circuit.

Transistor 01 is in an off state in this state. This is because the capacitor C2 is connected to the base electrode of the transistor 01, so the transistor 02 is turned on before the transistor Q1 is turned on, and this state is maintained. That is, before the transistor Q1 is turned on by the current flowing to the base electrode of the transistor o1 via the resistors R3 and R5, the resistors R1 and R4
Transistor Q2 is turned on by the current flowing through the -...- sumi pole of transistor (]2, and therefore,
The potential of the base electrode of transistor Q1 is maintained low, and the off state is maintained.

In this state, if the voltage between the signal '+fA100 and the signal line 200 increases by 1, the constant voltage diode ZDI
This limits the base voltage of transistor QO, and further limits the collector current of transistor 00. That is, the loop circuit enters a state where the current limit is limited to the first limit current.

Next, a case will be described in which a booster power source is connected to the signal lines 100 and 200. When the voltage between the signal lines 100 and 200 exceeds a predetermined value, a current flows through the constant voltage diode ZDO and the resistor R2, and the current is supplied to the base electrode of the transistor o1. This turns on transistor OLD. When transistor Q1 turns on, this 1-
The collector voltage of transistor Q1 decreases, and the base voltage of transistor 02 decreases. Due to the drop in base voltage, transistor o2 is turned off. As a result, the base voltage of transistor Qo is determined by the current flowing through resistor RO, resistor R1, and transistor 01. That is, the restriction on the current flowing through this loop circuit is released.

Constant voltage diode ZD1 connected in parallel to resistor R11
By setting the voltage at which the constant voltage diode ZD2 conducts to be higher than the voltage at which the constant voltage diode ZD2 conducts, the current flowing through the transistor QO can be limited to the second limit current.

This second limiting current is used for limiting abnormal voltages, and the constant voltage diode ZD1,
If the value of ZD2 is set, this loop circuit exhibits constant resistance characteristics.

Here, it is assumed that the transistor Q1 is on, the transistor Q2 is off, and the constant voltage diode ZDI is not conductive. At this time, a current limited by the constant voltage diode 'ZD2 flows through the base electrode of the l transistor QO. Therefore, a larger current flows to the base electrode of the transistor QO than when the constant voltage diode ZDI is conductive, and a larger current also flows to the collector electrode of the transistor QO. Therefore, the constant voltage diode ZD1 may become non-conductive. Therefore, it is necessary to remember that the constant voltage diode ZD1 is momentarily conductive, that is, it is necessary to maintain the on state of the transistor 01.

In this way, the loop circuit for 1JT1 channel of the present invention is -
Current is limited for the 48V power supply line, and constant resistance characteristics are shown for the line connected to the boosted power supply. The current limiting mode and the constant resistance characteristic mode are automatically switched. As a result, the current is limited for the -48■ line, and a constant resistance value is exhibited when the additional power supply is connected. Therefore, the power consumption of the loop circuit for the communication line of the present invention is according to (2) 2 for a -48V line.
When connecting an additional power supply, follow (3) 2. Therefore, power consumption can always be kept at the lowest level.

〔Effect of the invention〕

As explained above, the communication path loop circuit of the present invention has the following features:
Power consumption can always be kept at the lowest level whether the booster power source is connected or not. Therefore, the amount of heat generated in high-density packaging can be reduced.
This has a great effect on ensuring the reliability of circuit components, especially semi-solid components.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a communication path loop circuit according to an embodiment of the present invention. FIG. 2 is a circuit diagram of a conventional communication path loop circuit. FIG. 3 is a circuit diagram of a conventional communication path loop circuit. FIG. 4 is a diagram showing an example of how the loop circuit is used. DOLDI, D2, D3, Dlo...Diode,
ROlRl, R2, R3, R4, R5, R6, R7, R
IOlRll...Resistance, ZDOlZDI, Zn2,
ZDIO... Constant voltage diode, QOlol, 02.
...Transistor, GO, CI...DC cutoff capacitor, C2, C3, CIO...Capacitor, L...
Relay, ■... Ballista, 1... Output rank, 2
... Loop circuit, 3 ... Input crank, 4 ... Relay, 5 ... Power supply, 6 ... Boosting power supply, 100.10
1.200.201...Signal line.

Claims (1)

[Claims] (1) In a communication line loop circuit that is connected to two lines between telephone exchanges and has high impedance for AC signals and low resistance for DC signals, means for limiting the current flowing through this line to a predetermined value or less when the voltage is below a predetermined voltage; and once the voltage between the two lines exceeds a predetermined voltage, the limiting means is used to limit the current flowing through the line to a predetermined value or less. 1. A loop circuit for a communication path, comprising means for releasing the resistance value and maintaining a substantially constant resistance value.