JPS61198912A - Delay circuit - Google Patents

Abstract

PURPOSE:To give a delay time required for a gate circuit or the like to the gate circuit by providing a circuit offering time constant change to the input and/or output of the gate circuit so as to reduce number of circuit elements. CONSTITUTION:A cathode of a diode D1 is connected to an output side of a resistor R2. A cathode of a diode D3 is connected to an output side of a resistor R6. Then the input leading/trailing time of the gate circuit G2 depends on a product between a resistance of the resistor R2 and series junction capacitance of the diodes D3, D4. The input leading/trailing time of the gate circuit G3 in the setting state of the time constant as above, the delay time from the input to the output is minimized. In changing the output voltage of a variable resistor RV1 toward 0V, the leading time and the trailing time are increased to increase the delay time between the input and output.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a delay circuit that incorporates the characteristics of a variable capacitance diode into circuit delay.

In digital logic circuits, signals are required to be input to the gate circuits at appropriate timings. For this purpose, means for producing a desired delay is generally employed in the gate circuit.

It is desirable that such means be able to provide the necessary delay with a small number of circuit elements.

[Conventional technology]

As shown in FIG. 2, a conventional delay circuit of this type includes a resistor R2, a capacitor C1, a variable capacitance diode D2%, and a resistor R at the input and output of the ECL gate circuit.
c, a capacitor C3 and a variable capacitance diode D4 are connected, and a voltage divided by a variable resistor RV is supplied to the anodes of these diodes D2 and D4 through a resistor R3 and a resistor R4, respectively. It is possible to adjust the delay time by adjusting the variable resistor RV1.

[Problem that the invention seeks to solve]

However, with the above means, if the required delay time cannot be obtained, the resistor R2, capacitor C1, and variable capacitance diode D2, and the resistor RG, capacitor C3, and variable capacitance diode D4 are added by the required number of stages. By doing so, we have adopted a technique that fills the gap. In this technique, the intended purpose can only be achieved by increasing the number of circuit elements. Such an increase in the number of circuit elements reduces the packaging density of integrated circuits.

[Means for solving problems]

The present invention provides a delay circuit designed to solve the above-mentioned problems, and the first means thereof is to connect a resistor connected between an input end and an output end, and a cathode of one of a pair of variable capacitance diodes. and a variable capacitance diode circuit whose other cathode is connected to the output terminal and a reference potential, and a bias voltage supply circuit which supplies a bias voltage to the anodes of both the variable capacitance diodes. is constructed by providing the circuit according to the first means at the input and/or output of a gate circuit.

[Effect]

According to the circuit of the present invention, by appropriately adjusting the bias voltage, the variable capacitance diode connected to the output terminal side is changed from a reverse bias state (low capacitance! 3) to a forward bias state (i.e., This can cause an increase in capacitance and eventually turn it into a resistive element.
The time constant can be changed significantly.

Therefore, by providing a circuit capable of exhibiting a time constant change as described above at the input and/or output of a gate circuit, it is possible to reduce the number of circuit elements and provide the delay time required by the gate circuit etc. to the circuit. can.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows an embodiment of the invention. This embodiment shows an example in which the present invention is applied to a gate circuit. This embodiment is shown in Figure 2, which shows the conventional circuit capacitor CI.

C3 is a variable capacitance diode D1. The characteristic part lies in the change to D3. That is, the cathode of diode D1 is connected to the output side of resistor R2, and its anode is connected to the anode of diode D2, and the cathode of diode D3 is connected to the output side of resistor R9, and its anode is connected to the anode of diode D4. It was connected.

The operation of the circuit configured in this way will be explained.

For convenience of explanation, suppose that the variable resistor RV is adjusted so that 1 appears at its output, then the variable capacitance diodes D1 to D4 are all reverse biased and the junction capacitance of the diodes D1 to D4 is minimized. Become. In this set state, the input rise and fall times of the gate circuit G2 are determined by the resistance value of the resistor R2 and the diode D.
1 and the series junction capacitance of D2 (time constant), and the input rise and fall time of the gate circuit G3 is determined by the resistor R.
It is determined by the product (time constant) of the resistance value of B and the series junction capacitance of diodes D3 and D4. In such a time constant setting state, the delay time from input to output is minimized.

When the output voltage of the variable resistor is changed from this setting state toward 0 volts, the reverse bias values of the diodes D to D4 become smaller, and their respective junction capacitances increase. Therefore, each of the above-mentioned time constants, that is, rise time and fall time, increases, and the delay time between input and output increases.

Further, as the output voltage of the variable resistor is changed toward O volts, the bias state of the diodes D1 and D3 changes from reverse bias to forward bias.

At this time, the diode D2. D4 remains reverse biased. When the diodes D1 and D3 are forward biased, the input time constant of the gate circuit G2 is the sum of the resistance value of the resistor R2 and the forward resistance value of the diode D, and the diode D.
The output time constant of gate circuit G2 is determined by the product of the sum of the resistance value of resistor R6 and the forward resistance value of diode D3, and the junction capacitance of diode D4, and is simply determined by the product of the junction capacitance of diode D4. The time constant is larger than when the variable capacitance diode is reverse biased.

The maximum delay time is obtained when the output voltage of the variable resistor RV is changed to 0 volts.

In the above embodiment, a two-stage configuration is used, including a delay circuit including a resistor R2 and variable capacitance diodes DI and D2, and a delay circuit including a resistor R6 and variable capacitance diodes D3 and D4, but this is due to the rise and fall characteristics. This is to offset the difference, thereby minimizing duty fluctuations between input and output and increasing delay time. Therefore, if the required characteristics can be satisfied even with a one-stage configuration, the present invention can be applied.

〔Effect of the invention〕

As explained above, according to the present invention, ■Delay time can vary significantly.

(2) Furthermore, by adopting a two-stage configuration, it is possible to obtain effects such as canceling out differences in rise and fall characteristics, reducing duty fluctuations between input and output, and causing a significant change in delay time.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional circuit. In the figure, R2, R3, R4, Rs are fixed resistances, RV
, are variable resistors, Dl to D4 are variable capacitance diodes, G
2 is a gate circuit.

Claims (2)

[Claims] (1) A resistor connected between an input terminal and an output terminal, a variable capacitance diode circuit in which one cathode of a pair of variable capacitance diodes is connected to the output terminal and the other cathode to a reference potential, and both of the variable capacitance diodes 1. A delay circuit comprising a bias voltage supply circuit that supplies a bias voltage to an anode of a capacitive diode. (2) A first resistor connected between the input terminal and the input of the gate circuit, and one cathode of the first variable capacitance diode pair connected to the input of the gate circuit, and the other cathode connected to the reference potential. a first variable capacitance diode circuit, a second resistor connected between the output of the gate circuit and the output terminal, and a second variable capacitance diode pair, with one cathode connected to the output terminal and the other connected to the output terminal. A second variable capacitance diode circuit whose cathode is connected to a reference potential, and a bias voltage supply circuit that supplies a bias voltage to the anode of each variable capacitance diode of the first and second variable capacitance diode circuits. A delay circuit featuring: