JPS61196315A - Power supply control system - Google Patents

Abstract

PURPOSE:To switch on a power supply when a service interruption is recovered by storing in a latch means a fact that the power supply was not switched on at a due time point in a power failure. CONSTITUTION:A time counter 4 counts the time by the clock given from an oscillator 5. When a comparator 6 detects in a power failure that coincidence is secured between the count value of the counter 4 and the value of a comparison register 3, a power supply ON latch 11 is set and the count value of the counter 4 is replaced and set at a level different from the value of the register 3. Thus a primary power supply 7 can be switched on according to the information on the latch 11 after the power failure is recovered since the information on the power supply ON remains at the latch 11 although no output of the comparator is available.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a power supply control method for a data processing device or a low-electronic device, and particularly to a power supply control method suitable for a device intended for automatic operation.

[Background of the invention]

As an automatic power-on method, for example, Japanese Patent Application Laid-Open No. 58-2088
As shown in Japanese Patent No. 25, a power control mechanism is known that includes a battery as an auxiliary power source for power-on and as a backup in case of a power outage.

However, if the power is not turned on at the power-on time due to a power outage, even if the power is restored, the power must be turned on manually, requiring operator intervention.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a power supply control method that makes it possible to perform a power-on operation after power is restored when there is a power outage at a preset power-on time.

[Summary of the invention]

The present invention is a battery-backed power control mechanism that
The system memorizes the fact that the power-on operation was performed when the power-on time has arrived in the middle of the day, and the power-on operation can be performed at the next time.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

In FIG. 1, a main power supply 7 is a power supply for the processing device 1, and an auxiliary power supply 9 is a power supply for the power supply control mechanism 2. The auxiliary power supply 9 is always a power control device regardless of whether the main power supply 70 is on or off! f) Power is being supplied to 2. However, in the event of a power outage, power cannot be supplied, so a backup battery 8 is provided, and in the event of a power outage,
5 so that power is supplied to the power supply control mechanism 2 from the battery 8.

The power supply control mechanism 2 is connected to the processing device 1 through an input/output interface 10 . The power supply side n mechanism 2 has a time counter 4, a comparison register 5, an oscillator 5, a comparator 6, and a power on latch 11. Via the input/output interface 10, the time counter 4 sets the current time, and the comparison register 3 sets the power on/off times as initial values.

The time counter 4 measures time using the clock from the oscillator 5, and compares it with the time counter 4! When the comparator 6 detects that the values in the registers 3 are the same, the power-on latch 11 is set. The power supply control mechanism 2 is powered by a backup battery 8 and an auxiliary power supply 9, so operation is guaranteed even when the main power supply 7 is off.Also, during a power outage, the main power supply 7 and the auxiliary power supply 9 are stopped, but the backup Operation is guaranteed by battery 8Ilc.

During a power outage, the comparator 6 detects that the values of the time counter 4 and the comparison register 3 have become the same, and after setting the power on latch 11, the value of the time counter 4 is updated and, unlike the value of the comparison register 3, the value of the comparison register 3 becomes the same. Even if the output of the power supply unit 6 disappears, the power-on information of the power-on latch 111C remains, so the main power supply 7 can be turned on based on the information of the power-on latch 11 after the power is restored.

FIG. 2 shows an example of system operation using the present invention.

First, manually turn on the power to the system (10
0). The input/output interface 10 sets the current time in the time counter 4, and sets the power-off time in the comparison register 3 (101). When time passes and the comparator 6 detects that the power-off time has elapsed, the input/output interface 12 generates an interrupt to the processing device 1. When the processing device 1 detects that the generated interrupt factor is the elapse of the power off time, it sets the power on time in the comparison register 3 using the input/output interface 10 (
102). Further, the processing device 1 turns off the main power source 7 via the power control interface 13 (1o3). After that, when a power outage occurs, it is assumed that the auxiliary power supply 9 is cut off (104). As described above, even if the power-on time elapses during a power outage, the power control mechanism 2 sets the power-on latch 11 with the output of the comparator 6 (106).

During a power outage, the contents of the power on latch are set to backup battery 8.
When the power is restored (107), the auxiliary power supply 9 is restored'! (108), the main power source 7 is turned on based on the held power-on information, and the processing device 1 is enabled to operate. The processing device 11 reads the value of the time counter 4 through the input/output interface 10 and compares it with the next power off time.
If the value of the time counter 4 has exceeded the power-off time, the next power-on time is set in the comparison register 3 by the input/output interface 10, and then the main power supply 7 is turned off by the power control interface 13. This method makes it possible to prevent unnecessary energization of the processing device 1.

〔Effect of the invention〕

According to the present invention, automatic power-on operation is guaranteed after power restoration after power failure, so there is an effect that automatic operation of the system becomes possible without operator intervention.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. The second factor is a flowchart showing an example of system operation using the present invention. DESCRIPTION OF SYMBOLS 1... Processing device, 2... Power control mechanism, 3... Comparison register, 4... Time counter, 5... Generator, 6... Comparator, 7... Main power supply , 8... Backup battery, 9... Auxiliary power supply, 11... Power on latch Fig. 1 Fig. 2

Claims (1)

[Claims] In a method in which power is controlled by a power control mechanism that performs time counting and instructs the power to be turned on at a preset time, the power control mechanism is backed up by a battery and the power is turned on when the power is turned on during a power outage. A power supply control method characterized in that a latch means stores information that a power-on operation has not been performed, and when power is restored, a power-on operation is performed according to the state of the latch means.