JPS61194377A - Phase matching circuit - Google Patents

Phase matching circuit

Info

Publication number
JPS61194377A
JPS61194377A JP3494285A JP3494285A JPS61194377A JP S61194377 A JPS61194377 A JP S61194377A JP 3494285 A JP3494285 A JP 3494285A JP 3494285 A JP3494285 A JP 3494285A JP S61194377 A JPS61194377 A JP S61194377A
Authority
JP
Japan
Prior art keywords
phase
reference signal
signal
receiving systems
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3494285A
Other languages
Japanese (ja)
Inventor
Kenji Kimori
木森 憲司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3494285A priority Critical patent/JPS61194377A/en
Publication of JPS61194377A publication Critical patent/JPS61194377A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01SRADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S13/00Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
    • G01S13/02Systems using reflection of radio waves, e.g. primary radar systems; Analogous systems
    • G01S13/06Systems determining position data of a target
    • G01S13/42Simultaneous measurement of distance and other co-ordinates
    • G01S13/44Monopulse radar, i.e. simultaneous lobing
    • G01S13/4436Monopulse radar, i.e. simultaneous lobing with means specially adapted to maintain the same processing characteristics between the monopulse signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Radar Systems Or Details Thereof (AREA)

Abstract

PURPOSE:To automatically perform phase matching between receiving systems and to make it possible to always detect an accurate azimuth angle and an accurate angle of elevation, by sending a reference signal to first, second and third receiving systems from a reference signal generation circuit and detecting the phase differences between the receiving systems. CONSTITUTION:A matching timing signal D1 is inputted to a reference signal generation circuit 24 and sample hold circuits 20, 21 from the outside during a time out of the data effective region within the pulse repeating period of radar. The reference signal generation circuit 24 generates a reference signal E1 in synchronous relation to said timing signal D1 to output the same to couplers 15, 16, 17. This reference signal E1 is supplied to phase detectors 13, 14 through first, second and third receiving systems. The outputs of the phase detectors 13, 14 are changed by the amplitude and phase difference of a binary signal and outputted as a fixed error if phase non-matching is present in the first, second and third receiving systems. Phase adjustment is performed on the basis of said error output by phase shifters 18, 19.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、モノパルスレーダ等に用いられ、方位角およ
び高低角を検出するための3つの受信系からなる角度検
出回路の各受信系間の固有の位相差を補正する位相整合
回路に関し、特に各受信系列間の位相差を自動的に補正
するよう改良した位相整合回路に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention is used in monopulse radar, etc., and is composed of three receiving systems for detecting azimuth angles and elevation angles. The present invention relates to a phase matching circuit that corrects inherent phase differences, and particularly to a phase matching circuit that is improved to automatically correct phase differences between each received sequence.

よく知られているように、モノパルスレーダ等に用いら
れる角度検出回路はアンテナ設定方向の左、右(L、R
)の対称位置の上、下(U、  L)に設けられた同一
のビーム特性を持ったレーダアンテナがそれぞれ目標物
体より受信した受信信号レベルを加算した和信号Σ(L
O+ RO)と、減算した差信号ΔAL (LO−RO
) 、ΔEL (Do−L(Th )の3つの信号を3
系列の受信系にそれぞれ入力し、和信号を基準として2
つの差信号との間の位相差を検出して目標物体の方位角
および高低角を検出している。
As is well known, the angle detection circuits used in monopulse radar etc.
) is the sum signal Σ(L
O+RO) and the subtracted difference signal ΔAL(LO-RO
), ΔEL (Do-L(Th))
Input each to the receiving system of the series, and use the sum signal as a reference.
The azimuth angle and elevation angle of the target object are detected by detecting the phase difference between the two difference signals.

この角度検出回路において、3系列の受信系間に固有の
位相差があると、受信信号間の位相差が異なった値とな
って検出され、正確な方位と高低角を得ることができな
くなる。
In this angle detection circuit, if there is a unique phase difference between the three receiving systems, the phase difference between the received signals will be detected as different values, making it impossible to obtain accurate azimuth and elevation angle.

そこで、受信系間の位相差をなくするため、各受信系の
固有位相差が0となるよう受信系を構成する受信回路の
個々について位相ズレをOとした後、再び受信系の総合
位相ズレを0とするよう受信回路の位相を補正調整して
いる。また、経年変化や環境変化によって発生する受信
系の位相ズレにおいても上記と同じ位相調整を行なって
いる。
Therefore, in order to eliminate the phase difference between the receiving systems, after setting the phase shift to O for each of the receiving circuits that make up the receiving system so that the unique phase difference of each receiving system becomes 0, the total phase shift of the receiving system is The phase of the receiving circuit is corrected and adjusted so that 0. Furthermore, the same phase adjustment as described above is also performed for phase shifts in the receiving system that occur due to aging or environmental changes.

この位相調整作業は多くの作業工数を必要とするため、
自動的に位相整合ができる位相整合回路が必要となった
This phase adjustment work requires a lot of man-hours, so
A phase matching circuit that can automatically perform phase matching became necessary.

〔従来の技術〕[Conventional technology]

第3図は従来の位相整合を説明するための角度検出回路
のブロック図、第4図はモノパルスレーダアンテナの動
作を説明するためのアンテナパターン図およびアンテナ
配置図である。
FIG. 3 is a block diagram of an angle detection circuit for explaining conventional phase matching, and FIG. 4 is an antenna pattern diagram and an antenna arrangement diagram for explaining the operation of a monopulse radar antenna.

第4図において、同一のビーム特性を持ったAI。In Figure 4, AI with the same beam characteristics.

A2およびBl、B2の4つのアンテナは、アンテナ設
定方向θOでアンテナビームの最大点の172出力レベ
ルで重畳するようアンテナ設定角度より左。
The four antennas A2, Bl, and B2 are placed to the left of the antenna setting angle so that they overlap at the 172 output level at the maximum point of the antenna beam in the antenna setting direction θO.

右の対称位置の上下に配置されている。いま、例えば、
目標物体27を4つのアンテナで受信すると受信レベル
は図示のごと< UL、 OR,LL、 LRとなる。
They are placed above and below the symmetrical position on the right. Now, for example,
When the target object 27 is received by four antennas, the reception levels become <UL, OR, LL, and LR as shown in the figure.

この受信信号の和Σ(LO+RO) 、方位角差ΔAZ
(LO−RO) 、高低角差ΔEL (00−LOo 
)の3つの信号を作成した後、第3図の3つの受信系の
それぞれに入力される。(但し、LO= UL + L
L、 RO= UR+ LR,UO−UR+ UL、 
LOo = L、R+ LLとなる。)各受信系は、第
1.第2.第3のミクサ回路1゜2.3で入力信号周波
数9G血を330MHzに逓降し、それぞれ第1.第2
.第3の中間周波増幅回路(以後IF回路と言う>4.
5.6により増幅し、第2のミクサ7.8.9で更に1
0MHzに逓降して第、2のIF回路10,11.12
で増幅して所定量のレベルとしてフェーズ検出器13.
14に出力する。
The sum of the received signals Σ(LO+RO), the azimuth difference ΔAZ
(LO-RO), elevation angle difference ΔEL (00-LOo
) are input to each of the three receiving systems shown in FIG. (However, LO = UL + L
L, RO= UR+ LR, UO-UR+ UL,
LOo=L, R+LL. ) Each receiving system has the first. Second. The input signal frequency of 9G blood is lowered to 330MHz by the third mixer circuit 1°2.3, and the input signal frequency of 9G is lowered to 330MHz. Second
.. Third intermediate frequency amplification circuit (hereinafter referred to as IF circuit)>4.
5.6 and further 1 in the second mixer 7.8.9.
Stepping down to 0MHz, the second IF circuit 10, 11.12
Amplify the signal to a predetermined level and output it to the phase detector 13.
Output to 14.

フェーズ検出器13および14は、各受信系より出力さ
れた10 M Hz帯域のΣ信号とΔAZ信号およびΣ
信号とΔEL信号のレベル差と位相差を検出し、Σ信号
を基準としてΔAZ信号およびΔEL信号の位相差が遅
れた場合はレベル差に対応した電圧を持った正電位の信
号を、その反対に、位相差が進んだ場合はレベル差に対
応した電圧を持った負電位の信号を出力し、目標物体の
方位角と高低角を検出している。
The phase detectors 13 and 14 detect the 10 MHz band Σ signal, ΔAZ signal, and Σ signal output from each receiving system.
The level difference and phase difference between the signal and the ΔEL signal are detected, and if the phase difference between the ΔAZ signal and the ΔEL signal is delayed with respect to the Σ signal, a positive potential signal with a voltage corresponding to the level difference is sent to the opposite side. If the phase difference advances, a negative potential signal with a voltage corresponding to the level difference is output, and the azimuth and elevation angle of the target object are detected.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記の角度検出回路にあっては、各受信系を構成するミ
クサ回路やIF回路に固有の位相ズレがあると入力され
た受信信号の位相の値が変化し、正確な方位角、高低角
を得ることができない。
In the above angle detection circuit, if there is a phase shift inherent in the mixer circuit or IF circuit that constitutes each receiving system, the phase value of the input received signal will change, and accurate azimuth and elevation angles will be detected. can't get it.

そこで、従来は受信系を構成する受信回路ごとに位相ズ
レが0となるよう調整した後、再び受信系の総合位相ズ
レをOとするよう受信回路の位相を補正調整し、受信系
間の位相ズレをなくしていた。また、経年変化や環境変
化によって発生する受信系の位相ズレにおいても上記と
同じ位相調整を行なっている。この位相調整作業は多く
の作業工数を必要とするといった問題がある。
Therefore, conventionally, after adjusting each receiving circuit that makes up the receiving system so that the phase shift is 0, the phase of the receiving circuit is corrected and adjusted again so that the total phase shift of the receiving system is O, and the phase difference between the receiving systems is adjusted. I had eliminated the gap. Furthermore, the same phase adjustment as described above is also performed for phase shifts in the receiving system that occur due to aging or environmental changes. There is a problem in that this phase adjustment work requires a large number of man-hours.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、上記問題点を解消した自動的に各受信系列間
の位相差をなくする位相整合回路を提供するもので、そ
の手段は、標準受信系の出力信号と惨の受信系のそれぞ
れの出力信号との位相差を位相検出器で検出する角度検
出回路の前記標準受信系と前記他の受信系間の位相整合
回路であって、基準信号を発生し前記各受信系の入力端
に出力する基準信号発生回路と、前記他の受信系の信号
系路に設けられ、前記角度検出回路の位相検出器より出
力される前記基準信号の位相差信号に対応して前記他の
受信系の位相差を補正するフェイズシフタとより構成さ
れてなる位相整合回路によってなされる。
The present invention solves the above-mentioned problems and provides a phase matching circuit that automatically eliminates the phase difference between each receiving sequence. A phase matching circuit between the standard reception system and the other reception system of the angle detection circuit that detects a phase difference with an output signal using a phase detector, and generates a reference signal and outputs it to the input end of each reception system. A reference signal generation circuit is provided in the signal path of the other reception system, and the position of the other reception system is determined in response to the phase difference signal of the reference signal output from the phase detector of the angle detection circuit. This is accomplished by a phase matching circuit composed of a phase shifter that corrects the phase difference.

〔作用〕[Effect]

上記位相整合回路は、レーダのパルス繰返し時間内での
角度検出を行う有効時間外を利用し、基準信号発生回路
より基準信号を第1.第2.第3の受信系に同時に入力
し、第1の受信系を基準として第2.第3の受信系間の
それぞれの位相差を各系間に接続されているフェイズ検
出器で検出する。
The above-mentioned phase matching circuit uses the outside of the effective time for angle detection within the pulse repetition time of the radar to generate the reference signal from the reference signal generation circuit in the first. Second. input to the third receiving system at the same time, and the second receiving system is input to the third receiving system as a reference. Each phase difference between the third receiving systems is detected by a phase detector connected between each system.

フェイズ検出器で検出された位相差信号はサンプルホー
ルド回路で号ンプリングされサンプル信号電圧でホール
ドされる。
The phase difference signal detected by the phase detector is sampled by a sample hold circuit and held at a sample signal voltage.

サンプルホールド回路より出力されるホールド信号はA
/D変換器でディジタル信号に変換された後、第2およ
び第3の受信系の入力に設けられたフェイズシフタに入
力される。
The hold signal output from the sample hold circuit is A
After being converted into a digital signal by a /D converter, the signal is input to phase shifters provided at the inputs of the second and third receiving systems.

第2および第3の受信系の入力端に設けられたフェイズ
シフタは、ホールド電圧に対応して受信系間の位相差が
Oとなるよう第2および第3の受信系の位相を補正する
Phase shifters provided at the input ends of the second and third receiving systems correct the phases of the second and third receiving systems so that the phase difference between the receiving systems becomes O in accordance with the hold voltage.

また、フェイズ検出器で位相差を検出するごとに位相差
補正を行なうよう合成器を設け、合成器によりフェイズ
検出器の2回目以降の検出位相差信号とサンプルホール
ド回路のホールド信号を合成し、合成信号によってフェ
イズシフタを位相補正し、ますます位相差が少なくなる
ようにしている。
In addition, a synthesizer is provided to perform phase difference correction every time a phase difference is detected by the phase detector, and the synthesizer synthesizes the second and subsequent detected phase difference signals of the phase detector and the hold signal of the sample and hold circuit. The phase shifter is phase-corrected using the composite signal to further reduce the phase difference.

〔実施例〕〔Example〕

以下、図面を参照して本発明の実施例を詳細に説明する
Embodiments of the present invention will be described in detail below with reference to the drawings.

第1図は本発明の一実施例の位相整合回路のブロック図
、第2図は位相整合回路の動作を説明するめのタイムチ
ャートであり、全図を通じて同一部分には同一符号を付
して示した。
Fig. 1 is a block diagram of a phase matching circuit according to an embodiment of the present invention, and Fig. 2 is a time chart for explaining the operation of the phase matching circuit. Ta.

第1図のブロック図に示すように一実施例の位相整合回
路は、第1.第2.第3の各受信系の入力端に接続され
た結合器15.16.17と、第2および第3の受信系
の入力端と結合器16および17との間に設けられたフ
ェイズシフタ18および19と、フェイズ検出器13お
よび14より出力される第1の受信系を基準とした第2
および第3の受信系間の位相差信号をサンプリングし、
サンプル信号電圧をホールドするサンプルホールド回路
20および21と、前記受信系間の位相差電圧とサンプ
ルホールド回路20および21のホールド電圧を合成す
る合成器25および26と、サンプルホールド回路20
および21のホールド電圧をディジタル信号に変換し、
フェイズシフタ18および19に出力するA/D変換器
22および23と、外部より入力される整合タイミング
信号に同期して基準信号を発生し、前記結合器15.1
6.17に出力する基準信号発生回路24とより構成さ
れる。
As shown in the block diagram of FIG. 1, the phase matching circuit of one embodiment includes a first . Second. A coupler 15, 16, 17 connected to the input end of each third receiving system, and a phase shifter 18 and 19, and a second receiving system based on the first receiving system output from the phase detectors 13 and 14.
and sampling the phase difference signal between the third receiving system,
Sample and hold circuits 20 and 21 that hold sample signal voltages, synthesizers 25 and 26 that combine the phase difference voltage between the receiving systems and the hold voltage of sample and hold circuits 20 and 21, and sample and hold circuit 20.
and converting the hold voltage of 21 into a digital signal,
A/D converters 22 and 23 output to phase shifters 18 and 19, generate a reference signal in synchronization with a matching timing signal input from the outside, and connect the coupler 15.1 to the coupler 15.1.
6.17.

その動作を第2図のタイムチャートを参照して説明する
。第2図Cに示すように、レーダのパルス繰返し期間内
のデータ有効域外の時間CIに外部よりDに示す整合タ
イミング信号D1が基準発生回路24.サンプルホール
ド回路20および21に入力される。基準信号発生回路
24は入力された整合タイミング信号D1に同期して第
2図Eに示すレーダ受信波と同一周波数帯の基準信号E
1を発生し、結合器15.16.17に出力する。
The operation will be explained with reference to the time chart of FIG. As shown in FIG. 2C, at a time CI outside the valid data area within the pulse repetition period of the radar, a matching timing signal D1 shown at D is externally applied to the reference generation circuit 24. It is input to sample and hold circuits 20 and 21. The reference signal generation circuit 24 generates a reference signal E in the same frequency band as the radar received wave shown in FIG. 2E in synchronization with the input matching timing signal D1.
1 and outputs it to the combiner 15.16.17.

結合器15.16.17で入力した基準信号E1は、第
1゜第2.第3の各受信系を通ってフェイズ検出器13
および14に出力される。フェイズ検出器はよく知られ
ているように、その出力は入力する2信号の振幅と位相
差によって変化するので第1の受信系と第2の受信系お
よび第1の受信系と第3の受信系に位相不整合があると
固定誤差となって現れる。
The reference signal E1 inputted to the coupler 15, 16, 17 is connected to the first, second, and second nodes. The phase detector 13 passes through each third receiving system.
and output to 14. As is well known, the output of a phase detector changes depending on the amplitude and phase difference of two input signals, so the output of the phase detector varies depending on the amplitude and phase difference between the two input signals. If there is a phase mismatch in the system, it will appear as a fixed error.

第2図Fに示す信号F1は、第1の受信系と第2の受信
系が位相の不整合によって生じたフェイズ検出器13の
位相検波出力を表しており、フェイズ検出器13が第1
回目の不整合パルスF1を検出すると、この信号はサン
プルホールド回路20によってサンプルホールドされ位
相補正信号GとなってA/D変換器22に入力されてデ
ィジタル信号に変換された後、フェイズシフタ18に出
力される。フェイズシフタ1日は入力された位相差値に
対応して基準信号の位相を補正する。
The signal F1 shown in FIG. 2F represents the phase detection output of the phase detector 13 caused by phase mismatch between the first receiving system and the second receiving system,
When the second mismatch pulse F1 is detected, this signal is sampled and held by the sample and hold circuit 20, becomes a phase correction signal G, is input to the A/D converter 22, is converted into a digital signal, and is then sent to the phase shifter 18. Output. The phase shifter 1 corrects the phase of the reference signal in accordance with the input phase difference value.

また、前記位相補正信号Gは第2回目の整合時    
゛までサンプルホールド回路20によってホールドされ
、第2回目の不整合パルスF2 (第2図F参照)と第
1の合成器25により合成される。この合成信号をフェ
イズシフタ1日に入力し、ますます位相差が少なくなる
ようにしている。なお、第2回目では第1回目ですでに
位相補正がなされているので、位相整合点検時の不整合
パルスF2は非常に小さい。
Moreover, the phase correction signal G is applied at the time of the second matching.
The signal is held by the sample and hold circuit 20 until 20, and is combined with the second mismatched pulse F2 (see FIG. 2F) by the first combiner 25. This composite signal is input to the phase shifter 1, so that the phase difference is further reduced. Note that in the second time, since the phase correction has already been made in the first time, the mismatch pulse F2 at the time of the phase matching check is very small.

以上、第1と第2の受信系の位相整合について述べ□た
が、第1と第3の受信系の位相整合についでも同様な動
作が行なわれる。
The phase matching between the first and second receiving systems has been described above, but the same operation is performed for phase matching between the first and third receiving systems.

このように各受信系間の位相整合が自動的に実現でき、
その位相差はほぼ位相整合ループ利得骨の1まで整合可
能である。
In this way, phase matching between each receiving system can be automatically achieved,
The phase difference can be matched to approximately 1 of the phase matching loop gain bone.

ただし、受信系入力からフェイズ検出器までの位相整合
ができなければ受信系ルートにおいて位相整合がとれた
と言えないので第1の受信系においては入力から第1の
ミクサまで、第2.第3の受信系においては入力から結
合器までの物理的長さを同等とし、また結合器15.1
6.17へ入力する基準信号の位相を合わせる事は勿論
である。
However, if phase matching cannot be achieved from the receiving system input to the phase detector, it cannot be said that phase matching has been achieved in the receiving system route, so in the first receiving system, from the input to the first mixer, the second... In the third receiving system, the physical length from the input to the coupler is the same, and the coupler 15.1
Of course, the phase of the reference signal input to 6.17 must be matched.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、モノパルスレーダ
の3系列の受信系の各系間の位相整合が自動的に整合で
き、経年変化や環境変化により発生する位相ズレも補正
し、常に正確な方位角、高低角を検出することかできる
As explained above, according to the present invention, it is possible to automatically match the phase between each of the three receiving systems of a monopulse radar, correct phase deviations that occur due to aging or environmental changes, and always maintain accurate phase matching. Azimuth and elevation angles can be detected.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の位相整合回路のブロック図
、第2図は位相整合回路の動作を説明するめのタイムチ
ャート、第3図は従来の位相整合を説明するための角度
検出回路のブロック図、第4図はモノパルスレーダアン
テナの動作を説明するためのパターン図である。 図において、1.2.3は第1のミクサ回路、4、 5
. 6は第1のIF回路、?、8.9は第2のミクサ回
路、10.11.12は第2のIF回路、13゜14は
フェイズ検出器、15.16.17は結合器、18.1
9はフェイズシフタ、20.21はサンプルホールド回
路、22.23はA/D変換器、24は基準信号発生回
路、25.26は合成器、27は目標物体をそれぞれ示
第1図 第3図
Fig. 1 is a block diagram of a phase matching circuit according to an embodiment of the present invention, Fig. 2 is a time chart for explaining the operation of the phase matching circuit, and Fig. 3 is an angle detection circuit for explaining conventional phase matching. FIG. 4 is a pattern diagram for explaining the operation of the monopulse radar antenna. In the figure, 1.2.3 is the first mixer circuit, 4, 5
.. 6 is the first IF circuit, ? , 8.9 is the second mixer circuit, 10.11.12 is the second IF circuit, 13°14 is the phase detector, 15.16.17 is the combiner, 18.1
9 is a phase shifter, 20.21 is a sample and hold circuit, 22.23 is an A/D converter, 24 is a reference signal generation circuit, 25.26 is a synthesizer, and 27 is a target object, respectively.

Claims (1)

【特許請求の範囲】[Claims] 標準受信系の出力信号と他の受信系のそれぞれの出力信
号との位相差を位相検出器で検出する角度検出回路の前
記標準受信系と前記他の受信系間の位相整合回路であっ
て、基準信号を発生し前記各受信系の入力端に出力する
基準信号発生回路と、前記他の受信系の信号系路に設け
られ、前記角度検出回路の位相検出器より出力される前
記基準信号の位相差信号に対応して前記他の受信系の位
相差を補正するフェイズシフタとより構成されてなるこ
とを特徴とする位相整合回路。
A phase matching circuit between the standard receiving system and the other receiving system of an angle detection circuit that detects a phase difference between the output signal of the standard receiving system and each output signal of the other receiving system using a phase detector, a reference signal generation circuit that generates a reference signal and outputs it to the input end of each of the receiving systems; and a reference signal generating circuit that is provided in the signal path of the other receiving system and outputs the reference signal from the phase detector of the angle detection circuit. A phase matching circuit comprising: a phase shifter that corrects a phase difference of the other receiving system in response to a phase difference signal.
JP3494285A 1985-02-22 1985-02-22 Phase matching circuit Pending JPS61194377A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3494285A JPS61194377A (en) 1985-02-22 1985-02-22 Phase matching circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3494285A JPS61194377A (en) 1985-02-22 1985-02-22 Phase matching circuit

Publications (1)

Publication Number Publication Date
JPS61194377A true JPS61194377A (en) 1986-08-28

Family

ID=12428225

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3494285A Pending JPS61194377A (en) 1985-02-22 1985-02-22 Phase matching circuit

Country Status (1)

Country Link
JP (1) JPS61194377A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58201081A (en) * 1982-05-20 1983-11-22 Mitsubishi Electric Corp Automatic phase balancing system of radar receiver
JPS58204381A (en) * 1982-05-24 1983-11-29 Mitsubishi Electric Corp Automatic tracking device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58201081A (en) * 1982-05-20 1983-11-22 Mitsubishi Electric Corp Automatic phase balancing system of radar receiver
JPS58204381A (en) * 1982-05-24 1983-11-29 Mitsubishi Electric Corp Automatic tracking device

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