JPS61193458A - Treatment of silicon wafer - Google Patents

Treatment of silicon wafer

Info

Publication number
JPS61193458A
JPS61193458A JP3318185A JP3318185A JPS61193458A JP S61193458 A JPS61193458 A JP S61193458A JP 3318185 A JP3318185 A JP 3318185A JP 3318185 A JP3318185 A JP 3318185A JP S61193458 A JPS61193458 A JP S61193458A
Authority
JP
Japan
Prior art keywords
wafer
oxygen
hydrogen
silicon wafer
heat treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3318185A
Other languages
Japanese (ja)
Inventor
Kikuo Yamabe
紀久夫 山部
Norihei Takai
高井 法平
Hiroshi Shirai
宏 白井
Masaharu Watanabe
正晴 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Coorstek KK
Toshiba Corp
Original Assignee
Toshiba Corp
Toshiba Ceramics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Ceramics Co Ltd filed Critical Toshiba Corp
Priority to JP3318185A priority Critical patent/JPS61193458A/en
Publication of JPS61193458A publication Critical patent/JPS61193458A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To realize appropriate crystal characteristics by a method wherein a silicon wafer is heated to a temperature not lower than 800 deg.C in an atmosphere of hydrogen or inert gas containing some hydrogen for the effective elimination in a short period of time of oxygen precipitates from the silicon wafer surface containing inter-lattice oxygen. CONSTITUTION:An Si wafer 11 equipped with a resistivity of 5-20OMEGA/cm is subjected to heat treatment in an argon atmosphere including 10% of hydrogen for the elimination of oxygen precipitates in the vicinity 11a of the surface of the Si wafer 11. In this process, oxygen in the vicinity 11a of the surface of the Si wafer 11 is diffused outward from the surface of r the formation of a defect-free layer in the vicinity 11a of the wafer surface. Simultaneously, a layer containing few lattices is formed in the inside 11b of the wafer. A process follow wherein the wafer 11 is subjected to oxidation in a dry atmosphere at a temperature not lower than 800 deg.C, preferably at 1,000 deg.C, for the formation of an oxide film 12, whereon a polycrystalline silicon film 13 is subsequently formed containing phosphorus.

Description

【発明の詳細な説明】 (発明の技術分野) 本発明は、格子間酸素を含むシリコンウェハの表面近傍
の酸素析出物を消滅させるシリコンウェハの処理方法に
関する。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a method of processing a silicon wafer for eliminating oxygen precipitates near the surface of the silicon wafer containing interstitial oxygen.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

従来、半導体集積回路の製造には、半導体インゴットを
ウェハ状に切出し、表面研磨を施したウェハをそのまま
集積回路製造シロセスに投入していた。また、集積回路
製造プロセスでは、1000 [℃]を上限とした工程
が一般に採用されていた。
Conventionally, in the manufacture of semiconductor integrated circuits, a semiconductor ingot was cut into wafer shapes, the wafers were surface polished and then fed as they were into an integrated circuit manufacturing system. Furthermore, in the integrated circuit manufacturing process, a process with an upper limit of 1000 [°C] has generally been adopted.

近年、半導体集積回路の高集積化は著しく、素イ、)□
4.□□イb i: m ’v 6ゆ□4o71  。
In recent years, the degree of integration of semiconductor integrated circuits has increased significantly.
4. □□Ib i: m'v 6yu□4o71.

いものがある。このため、プロセスの低温化が検討され
ている。しかし、1000 [℃]以下の工程では、次
に述べるような3iウエハの結晶特性に起因する熱酸化
膜の耐圧不良が発生する。なお、発生原因については今
゛後の硝究により解明されると思われるが、現在推al
lする耐圧不良発生過程は、次のようなものである。即
ち、Siウェハ中に含まれる格子間酸素原子が3i結晶
中の酸素析出物に捕えられて、更に大きな析出物となる
。集積回路製造の熱処理工程時には、この大きな析出物
の回り【こ発生する強い歪場の領域に、重金属等の不純
物が捕獲される。そして、この重金属を含む析出物が熱
酸化膜中に取込まれると酸化膜欠陥となり、耐圧不良を
生じたり、少数キャリア発生のライフタイムを小さくさ
せたりすることになる。
There's something. For this reason, lowering the process temperature is being considered. However, in processes at temperatures below 1000[deg.] C., breakdown voltage failures of the thermal oxide film occur due to the crystal characteristics of the 3i wafer as described below. The cause of the outbreak is expected to be elucidated through subsequent investigation, but there are currently no speculations.
The process of occurrence of breakdown voltage failure is as follows. That is, interstitial oxygen atoms contained in the Si wafer are captured by oxygen precipitates in the 3i crystal, and become even larger precipitates. During the heat treatment process of integrated circuit manufacturing, impurities such as heavy metals are captured in the region of the strong strain field generated around these large precipitates. If these heavy metal-containing precipitates are incorporated into the thermal oxide film, they will cause oxide film defects, resulting in poor breakdown voltage and shortening the lifetime of minority carrier generation.

そこで最近、この微少酸素析出物を除去する方法として
、イントリンシック・ゲッタリング法が注目されている
。即ち、S1ウエハを高温(例えば1150℃)で1〜
100時間の熱処理を行い、結晶育成中に行った過飽和
格子間酸素を外方拡散させ、3tウ工ハ表面から数〜数
10[μTrL]に゛ 亙る酸素濃度の低い領域を形成
する。この工程は同時に、結晶育成時に結晶中に入った
微小析出物を溶解させる効果もある。更に、低温(80
0℃)で数時間の熱処理を追加し、析出物の安定化をは
かった後、通常の集積回路製造工程に投入すると、10
00[℃]の製造工程でウェハ内部で析出物が成長する
。このイントリンシック・ゲッタリング法を集積回路製
造工程に採用すると、ウェハ内に発生した前記微小析出
物がプロセス中にウェハ表面に付着した金属不純物をゲ
ッターし、表面層を不純物のない状態に保つ。従って、
このようなプロセスによって作成された熱酸化膜は欠陥
が少ないと予想される。
Therefore, the intrinsic gettering method has recently been attracting attention as a method for removing these minute oxygen precipitates. That is, the S1 wafer is heated at high temperature (for example, 1150°C)
Heat treatment is carried out for 100 hours, and the supersaturated interstitial oxygen carried out during crystal growth is diffused outward to form a region with low oxygen concentration ranging from several to several tens [μTrL] from the surface of the 3t wafer. This step also has the effect of dissolving minute precipitates that have entered the crystal during crystal growth. Furthermore, low temperature (80
After several hours of heat treatment at 0°C) to stabilize the precipitates, the product was put into the normal integrated circuit manufacturing process.
Precipitates grow inside the wafer during the manufacturing process at 00°C. When this intrinsic gettering method is adopted in the integrated circuit manufacturing process, the minute precipitates generated within the wafer getter metal impurities attached to the wafer surface during the process, keeping the surface layer free of impurities. Therefore,
A thermal oxide film created by such a process is expected to have fewer defects.

しかしながら、この種の方法にあっては次のような問題
があった。即ち、シリコンウェハ表面の酸素析出物を確
実に消滅させるには、高温熱処理を長時間行う必要があ
り、実用性に乏しかった。
However, this type of method has the following problems. That is, in order to reliably eliminate oxygen precipitates on the surface of a silicon wafer, it is necessary to perform high-temperature heat treatment for a long time, which is impractical.

また、高温熱処理を長時間行って十分に表面近傍の酸素
濃度を低くし酸素析出物を溶解したつもりでも、熱酸化
膜の耐圧不良は期待した程少なくならないのが現状であ
る。実際の半導体集積回路の製造工程では上述したより
も複雑な現象が起きているものと思われる。
In addition, even if it is thought that high-temperature heat treatment is performed for a long time to sufficiently lower the oxygen concentration near the surface and dissolve oxygen precipitates, the current situation is that the breakdown voltage failure of the thermal oxide film does not decrease as much as expected. It is believed that more complex phenomena than those described above occur in the actual manufacturing process of semiconductor integrated circuits.

〔発明の目的〕[Purpose of the invention]

本発明は上記の事情を考慮してなされたもので、その目
的とするところは、格子間酸素を含むシリコンウェハ表
面の酸素析出物を単時間且つ効果的に消滅させることが
でき、シリコンウェハの結晶特性の改善をはかり得る実
用性の高いシリコンウェハの処理方法を提供することに
ある。
The present invention has been made in consideration of the above circumstances, and its purpose is to be able to effectively eliminate oxygen precipitates on the surface of a silicon wafer containing interstitial oxygen in a short period of time. An object of the present invention is to provide a highly practical silicon wafer processing method that can improve crystal properties.

〔発明の概要〕[Summary of the invention]

本発明の骨子は、イントリンシック・ゲッタリングにお
けるシリコン表面からの酸素の外方拡散を促進させるた
めに、水素雰囲気を利用することにある。
The gist of the present invention is to utilize a hydrogen atmosphere to promote outward diffusion of oxygen from the silicon surface during intrinsic gettering.

即ち本発明は、格子間酸素を含むシリコンウェハの表面
近傍の酸素を消滅させるシリコンウェハの処理方法にお
いて、前記シリコンウェハを水素或いは水素を含む不活
性ガス雰囲気中で800[℃]以上に、好ましくは10
00[℃]以上に加熱するようにした方法である。
That is, the present invention provides a method for processing a silicon wafer in which oxygen near the surface of the silicon wafer containing interstitial oxygen is extinguished, in which the silicon wafer is preferably heated to 800[° C.] or higher in an atmosphere of hydrogen or an inert gas containing hydrogen. is 10
This method involves heating to 00[°C] or higher.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、水素雰囲気中での熱処理によりシリコ
ンウェハ表面近傍の酸素の外方拡散を促進することがで
き、これにより表面近傍の酸素析出物を短時間で効果的
に消滅さゼることかできる。
According to the present invention, outward diffusion of oxygen near the surface of the silicon wafer can be promoted by heat treatment in a hydrogen atmosphere, thereby effectively eliminating oxygen precipitates near the surface in a short time. I can do it.

このため、イン1へリンシック・ゲッタリングの実用性
が向上し、その後に形成する素子の特性向上をはかり得
る。特に、1000[人]以下の薄いゲート酸化膜を有
するMO8型集積回路の高信頼化を行うことができる。
For this reason, the practicality of in-1 linthic gettering is improved, and the characteristics of elements formed subsequently can be improved. In particular, it is possible to improve the reliability of an MO8 type integrated circuit having a gate oxide film as thin as 1000 [people] or less.

〔発明の実施例〕[Embodiments of the invention]

まず、実施例を説明する前に、本発明の基本原理につい
て説明する。
First, before explaining embodiments, the basic principle of the present invention will be explained.

イントリンシック・ゲッタリングにおけるシリコン中の
酸素析出物の消滅過程は、次のように考えられる。即ち
、高温でシリコンウェハを熱処理すると、シリコン表面
から格子間酸素が外方拡散して、表面近傍の酸素析出物
の回りの格子間酸素濃度が低下する。やがて、固溶限以
下に下がると、酸素析出物から酸素が流出し、再固溶し
始める。
The disappearance process of oxygen precipitates in silicon in intrinsic gettering can be considered as follows. That is, when a silicon wafer is heat-treated at a high temperature, interstitial oxygen diffuses outward from the silicon surface, and the interstitial oxygen concentration around oxygen precipitates near the surface decreases. Eventually, when the temperature drops below the solid solubility limit, oxygen flows out from the oxygen precipitates and begins to dissolve again.

その際の酸素の流れは、酸素析出物とシリコン界面での
固溶反応と、この析出物界面で固溶した酸素が周辺に拡
散する過程によって制限される。再固溶の初期の段階で
は、析出物の半径が大きいた−〇− め、固溶反応による酸素の流出は十分速く拡散の方が全
体の固溶速度を律速する。しかし、固溶が進み、析出物
半径が小さくなると、拡散速度に比べ界面での固溶反応
が遅く反応律速となる。この反応、律速に入ると、固溶
速度が下がり、消滅時間が延びる。
At this time, the flow of oxygen is limited by a solid solution reaction at the interface between the oxygen precipitate and the silicon, and a process in which oxygen dissolved in solid solution at the interface of the precipitate diffuses to the surrounding area. At the initial stage of solid solution re-dissolution, the radius of the precipitate is large, so the outflow of oxygen due to the solid solution reaction is sufficiently fast, and diffusion controls the overall solid solution rate. However, as the solid solution progresses and the precipitate radius becomes smaller, the solid solution reaction at the interface is slower than the diffusion rate and becomes reaction rate-limiting. When this reaction becomes rate-limiting, the rate of solid solution decreases and the extinction time increases.

従来、シリコン表面近傍の酸素析出物を消滅させるため
の高温熱処理は、酸化性雰囲気若しくは不活性ガス雰囲
気で行われており、析出物の再固溶は、酸化物中のs 
r −o−s +の網目構成を熱エネルギーのみで切断
する必要があり、イントリンシック・ゲッタリングを行
っても、その表面に形成された酸化膜の欠陥密度を消滅
するには、高温熱処理を長時間行う必要があった。
Conventionally, high-temperature heat treatment to eliminate oxygen precipitates near the silicon surface has been carried out in an oxidizing atmosphere or an inert gas atmosphere, and the re-solid solution of the precipitates is caused by the sulfur in the oxide.
It is necessary to cut the r -o-s + network structure using only thermal energy, and even if intrinsic gettering is performed, high-temperature heat treatment is required to eliminate the defect density of the oxide film formed on the surface. It needed to be done for a long time.

そこで本発明者等は、これを解決する方法として、高温
熱処理を水素雰囲気中で行うことを検討した。この場合
、水素のシリコン中の固溶限も大きく、拡散係数も10
00 [℃]で約4X107[μm2/hlと大きいの
で、上記高温熱処理を行うと、S1中の酸素析出物に水
素が到達する。
Therefore, the present inventors have considered performing high-temperature heat treatment in a hydrogen atmosphere as a method to solve this problem. In this case, the solid solubility limit of hydrogen in silicon is large, and the diffusion coefficient is also 10.
Since the temperature is as large as approximately 4×10 7 μm 2 /hl at 0.00° C., when the above-mentioned high-temperature heat treatment is performed, hydrogen reaches the oxygen precipitates in S1.

その結果、81表面からの酸素の外方拡散によって、消
滅過程に入り、さらに界面反゛応律速段階に入った微小
析出物の界面において、水素を介在した還元反応が進み
、界面反応を促進させ消滅速度が増大する。従って、水
素を含む雰囲気中で高)品熱処理をしたS1ウエハでは
、表面近傍に酸化性雰囲気で高温熱処理した3iウエハ
に比べ、より短時間で且つ完全に酸素析出物を消滅させ
ることが可能となる。
As a result, the outward diffusion of oxygen from the 81 surface caused the annihilation process to occur, and at the interface of the microprecipitates, which entered the interfacial reaction rate-determining stage, a reduction reaction mediated by hydrogen proceeded, promoting the interfacial reaction. Extinction speed increases. Therefore, it is possible to completely eliminate oxygen precipitates in an S1 wafer that has been heat-treated in a hydrogen-containing atmosphere in a shorter time than in a 3i wafer that has been heat-treated at a high temperature in an oxidizing atmosphere near the surface. Become.

以下、本発明の詳細を図示の実施例によって説明する。Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

第1図(a)(b)は本発明の一実施例方法に係わるM
OSキャパシタの製造工程を示す断面図であり、チョク
ラルスキー法(CZ法)によって製造された3iウエハ
に適用した例である。
FIGS. 1(a) and 1(b) show M related to an embodiment of the method of the present invention.
3 is a cross-sectional view showing the manufacturing process of an OS capacitor, and is an example applied to a 3i wafer manufactured by the Czochralski method (CZ method).

まず、第1図(a)に示す如く面方位(100)、仕抵
抗5〜2010cm]のSiウェハ11を、10[%]
の水素を含むアルゴンガス中でミ1190[℃]の温度
で10分間熱処理することにより、81表面近傍の酸素
析出物を消滅させて結晶特性の改善をはかる。これによ
り、Siウェハ11の表面は第1図(a)中破線P部を
第2図に拡大して示す如く、ウェハ表面近傍の酸素は外
方拡散してしまい、表面近傍11aに無欠陥層が形成さ
れる。これと同時に、ウェハの内部11bには、微小欠
陥層が形成される。
First, as shown in FIG.
By performing heat treatment at a temperature of 1190 [° C.] for 10 minutes in argon gas containing hydrogen, oxygen precipitates near the surface of 81 are eliminated and crystal properties are improved. As a result, oxygen in the vicinity of the wafer surface diffuses outward, and the surface of the Si wafer 11 has a defect-free layer in the vicinity of the surface 11a, as shown in FIG. is formed. At the same time, a minute defect layer is formed inside the wafer 11b.

次いで、上記ウェハ11を乾燥雰囲気中で、1000 
[℃]の温度で35分間の処理により酸化し、第1図(
b)に示す如く厚さ400[入]の酸化膜12を形成し
た。続いて、LPCVD法により酸化膜12上にリン添
加多結晶シリコン膜13を厚さ4000 [人]形成し
た。その後、多結晶シリコン膜13を写真蝕刻法により
パターニングし、ゲート電極とした。
Next, the wafer 11 is heated at 1000° C. in a dry atmosphere.
It is oxidized by treatment at a temperature of [°C] for 35 minutes, and the result is shown in Fig.
As shown in b), an oxide film 12 with a thickness of 400 mm was formed. Subsequently, a phosphorus-doped polycrystalline silicon film 13 was formed on the oxide film 12 to a thickness of 4,000 mm using the LPCVD method. Thereafter, the polycrystalline silicon film 13 was patterned by photolithography to form a gate electrode.

上記形成された試料の耐圧不良率を′測定したところ第
3図に示す如き結果が得られた。ここで1、図中Aは熱
処理を施さない場合、Bは酸化性雰囲気中での熱処理を
行った場合、Cは本実施例方法による場合を示している
。なお、ゲート面積は、いずれも10[#lIl+2]
であり、酸化膜電界が7[MV]のときグー1〜電流が
1[μA]以上のものを不良と判定した。
When the breakdown voltage defect rate of the sample formed above was measured, the results shown in FIG. 3 were obtained. Here, 1. In the figure, A shows the case where no heat treatment was performed, B shows the case where the heat treatment was performed in an oxidizing atmosphere, and C shows the case where the method of this embodiment was used. Note that the gate area is 10 [#lIl+2] in both cases.
When the oxide film electric field was 7 [MV], those whose current was 1 [μA] or more were determined to be defective.

第3図から明らかなように、Bの場合はAの場合に比べ
ある程度の改善が見られるが十分ではない。これに対し
、Cの場合(本実施例の場合)、Bの場合に比しても顕
著な改善が見られる。
As is clear from FIG. 3, there is some improvement in case B compared to case A, but it is not sufficient. On the other hand, in the case of C (in this example), a remarkable improvement is seen compared to the case of B.

このように本実施例方法によれば、イントリンシック・
ゲッタリングを水素雰囲気中で行うことにより、Siウ
ェハ表面近傍の酸素析出物を効果的に消滅させることが
できる。このため、熱酸化膜12の欠陥密度を著しく低
減させることができる。従って、半導体集積回路に及ぼ
す波及効果は絶大である。例えば、MO8集積回路での
ゲート酸化膜の薄膜化を容易にし、動作速度を高め、動
作マージンを広くする□ことができ、動作に対する信頼
性を高めることができる。  − なお、本発明は上述した実施例方法に限定されるもので
はない。例えば、前記イントリンシック・ゲッタリング
を行う際の熱処理温度は1190[℃]に限るものでは
なく、800.[℃]以上であればよい。但し、処理時
間の短縮をはかる目的からは1000 [℃]以上にす
る方が望ましい。
In this way, according to the method of this embodiment, the intrinsic
By performing gettering in a hydrogen atmosphere, oxygen precipitates near the surface of the Si wafer can be effectively eliminated. Therefore, the defect density of the thermal oxide film 12 can be significantly reduced. Therefore, the ripple effect on semiconductor integrated circuits is enormous. For example, it is possible to easily reduce the thickness of the gate oxide film in an MO8 integrated circuit, increase the operating speed, widen the operating margin, and improve the reliability of the operation. - Note that the present invention is not limited to the above-described method. For example, the heat treatment temperature when performing the above-mentioned intrinsic gettering is not limited to 1190 [°C], but is 800°C. It is sufficient if the temperature is [°C] or higher. However, for the purpose of shortening the processing time, it is preferable to set the temperature to 1000 [°C] or higher.

さらに、熱処理する際の雰囲気中の水素の割合いは10
[%]に限るものではなく、適宜変更可能である。水素
1001%]でも効果はあるが、この場合高温熱処理中
に爆発する虞れがあり、熱処理装置の防爆対策等を十分
に行う必要がある。
Furthermore, the proportion of hydrogen in the atmosphere during heat treatment is 10
It is not limited to [%] and can be changed as appropriate. Hydrogen 1001%] is also effective, but in this case there is a risk of explosion during high-temperature heat treatment, and it is necessary to take sufficient explosion-proof measures for the heat treatment equipment.

10[%]の水素を含む窒素ガス中で高温熱処理を行う
場合には、ウェハ表面に変質層が形成されたらしく、熱
処理後化学的にウェハ表面を0.1[μTrL]程度以
上除去する必要があった。通常の気密性を持った高温熱
処理装置で20[%]の水素を含むアルゴンガス中で相
当数の高温熱処理を行ったが爆発等の事故は起こってい
ない。また、上記の熱処理温度及び水素の割合い等の条
件の他に熱処理時間等の条件も、仕様に応じて適宜変更
可能である。ここで、温度が高い程、更に時間が長い程
シリコン中の酸素析出物の消滅が表面からより深い領域
まで完全になされる。つまり、前記酸化膜の厚さが厚い
程、熱処理温度を高く、時間を長くする必要がある。
When high-temperature heat treatment is performed in nitrogen gas containing 10% hydrogen, a degraded layer appears to be formed on the wafer surface, and it is necessary to chemically remove more than 0.1 μTrL of the wafer surface after the heat treatment. there were. A considerable number of high-temperature heat treatments were performed in argon gas containing 20% hydrogen in a conventional airtight high-temperature heat treatment apparatus, but no accidents such as explosions occurred. Further, in addition to the above conditions such as the heat treatment temperature and the proportion of hydrogen, conditions such as the heat treatment time can also be changed as appropriate depending on the specifications. Here, the higher the temperature and the longer the time, the more completely the oxygen precipitates in the silicon disappear from the surface to the deeper region. That is, the thicker the oxide film, the higher the heat treatment temperature and the longer the heat treatment time.

また、前記実施例では、MOSキャパシタの製造に応用
したが、MOSFET及び他のMO8集積回路は勿論、
他の熱酸化膜を有する各種半導体素子のウェハ処理に適
用することができる。その他、本発明の要旨を逸脱しな
い範囲で、種々変形して実施することができる。
In addition, although the above embodiment was applied to the manufacture of MOS capacitors, it can of course be applied to the manufacture of MOSFETs and other MO8 integrated circuits.
It can be applied to wafer processing of various semiconductor devices having other thermal oxide films. In addition, various modifications can be made without departing from the gist of the present invention.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)(b)は本発明の一実施例方法に係わるM
OSキャパシタの製造工程を示す断面図、第2図は上記
第1図(a)に破線Pで囲んだ部分を拡大して示す模式
図、第3図は上記実施例方法による効果を説明するため
のものでグー1〜酸化膜の耐圧不良率を示す特性図であ
る。 11・・・3iウエハ、11a・・・ウェハの表面近傍
領域、’11b・・・ウェハの内部領域、12・・・熱
酸化膜(ゲート酸化膜)、13・・・リン添加多結晶シ
リコン膜。 出願人代理人 弁理士 鈴汀武彦 第1図 第2図 〜\〜−−−−− 第3図
FIGS. 1(a) and 1(b) show M related to an embodiment of the method of the present invention.
2 is a cross-sectional view showing the manufacturing process of an OS capacitor, FIG. 2 is a schematic diagram showing an enlarged view of the part surrounded by the broken line P in FIG. It is a characteristic diagram showing the breakdown voltage failure rate of Goo 1 to oxide film. 11... 3i wafer, 11a... Wafer surface vicinity region, '11b... Wafer internal region, 12... Thermal oxide film (gate oxide film), 13... Phosphorus-doped polycrystalline silicon film . Applicant's agent Patent attorney Takehiko Suzuta Figure 1 Figure 2 ~\~ Figure 3

Claims (4)

【特許請求の範囲】[Claims] (1)格子間酸素を含むシリコンウェハの表面近傍の酸
素を消滅させるシリコンウェハの処理方法において、前
記シリコンウェハを水素或いは水素を含む不活性ガス雰
囲気中で800[℃]以上に加熱することを特徴とする
シリコンウェハの処理方法。
(1) In the silicon wafer processing method for eliminating oxygen near the surface of the silicon wafer containing interstitial oxygen, the silicon wafer is heated to 800 [°C] or more in an atmosphere of hydrogen or an inert gas containing hydrogen. Characteristic silicon wafer processing method.
(2)前記シリコンウェハの処理温度を1000[℃]
以上に設定したことを特徴とする特許請求の範囲第1項
記載のシリコンウェハの処理方法。
(2) The processing temperature of the silicon wafer is 1000 [℃]
A method for processing a silicon wafer according to claim 1, characterized in that the above settings are made.
(3)前記熱処理する際の雰囲気は、水素を20[%]
以下含む不活性ガス雰囲気であることを特徴とする特許
請求の範囲第1項又は第2項記載のシリコンウェハの処
理方法。
(3) The atmosphere during the heat treatment contains 20% hydrogen.
3. The method of processing a silicon wafer according to claim 1, wherein the atmosphere is an inert gas atmosphere containing:
(4)前記不活性ガスとして、アルゴンを用いることを
特徴とする特許請求の範囲第3項記載のシリコンウェハ
の処理方法。
(4) The silicon wafer processing method according to claim 3, wherein argon is used as the inert gas.
JP3318185A 1985-02-21 1985-02-21 Treatment of silicon wafer Pending JPS61193458A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3318185A JPS61193458A (en) 1985-02-21 1985-02-21 Treatment of silicon wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3318185A JPS61193458A (en) 1985-02-21 1985-02-21 Treatment of silicon wafer

Publications (1)

Publication Number Publication Date
JPS61193458A true JPS61193458A (en) 1986-08-27

Family

ID=12379332

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3318185A Pending JPS61193458A (en) 1985-02-21 1985-02-21 Treatment of silicon wafer

Country Status (1)

Country Link
JP (1) JPS61193458A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0673059A2 (en) * 1994-03-07 1995-09-20 Advanced Micro Devices, Inc. Semiconductor wafer with pre-process denudation
JPH0897222A (en) * 1994-09-26 1996-04-12 Toshiba Ceramics Co Ltd Manufacture of silicon wafer, and silicon wafer
US6809015B2 (en) 1998-12-28 2004-10-26 Shin-Etsu Handotai Co., Ltd. Method for heat treatment of silicon wafers and silicon wafer
JP2006156973A (en) * 2004-10-25 2006-06-15 Toyota Motor Corp Manufacturing method of metal insulator semiconductor device
US7211141B2 (en) 2003-08-12 2007-05-01 Shin-Etsu Handotai Co., Ltd. Method for producing a wafer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59202640A (en) * 1983-05-02 1984-11-16 Toshiba Corp Treatment for semiconductor wafer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59202640A (en) * 1983-05-02 1984-11-16 Toshiba Corp Treatment for semiconductor wafer

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0673059A2 (en) * 1994-03-07 1995-09-20 Advanced Micro Devices, Inc. Semiconductor wafer with pre-process denudation
EP0673059A3 (en) * 1994-03-07 1998-09-16 Advanced Micro Devices, Inc. Semiconductor wafer with pre-process denudation
JPH0897222A (en) * 1994-09-26 1996-04-12 Toshiba Ceramics Co Ltd Manufacture of silicon wafer, and silicon wafer
US6809015B2 (en) 1998-12-28 2004-10-26 Shin-Etsu Handotai Co., Ltd. Method for heat treatment of silicon wafers and silicon wafer
US7011717B2 (en) 1998-12-28 2006-03-14 Shin-Etsu Handotai Co., Ltd. Method for heat treatment of silicon wafers and silicon wafer
US7211141B2 (en) 2003-08-12 2007-05-01 Shin-Etsu Handotai Co., Ltd. Method for producing a wafer
JP2006156973A (en) * 2004-10-25 2006-06-15 Toyota Motor Corp Manufacturing method of metal insulator semiconductor device

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