JPS6119185B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention provides a side sound protection circuit (hereinafter referred to as an automatic switching type side sound protection circuit) that has a plurality of balanced circuit networks and automatically selects the balanced circuit network with the best side sound protection characteristics among them. ) relates to a circuit that can improve the selection accuracy of a balanced circuit network. An example of a conventional side sound protection circuit of this type is shown in FIG. Refer to the same figure. Reference numerals 11 and 12 are respectively side sound prevention circuit parts for suppressing the transmitting signal from being transmitted as side sound to the receiving circuit. There are also various forms. The side sound protection circuit sections 11 and 12 each have four terminals, the first terminal is connected to the transmitting terminal 1, the second terminal is connected to the line terminal 2, and the third terminal is a receiving output. terminals 3 and 4, and the fourth terminal is the sweep circuit 1
7, 18 to balanced network groups 15, 16. In addition, the reception output terminals 3 and 4 are connected to a comparison circuit 21 via comparison signal forming sections 26 and 27, respectively. comparison signal forming section 26,
27 includes amplifier circuits 13 and 14 and rectification and smoothing circuits 19 and 20, respectively. Note that 22 is a Schmitt circuit, and 24 and 25 are communication path switches, respectively. Further, 5 is a receiving terminal. Next, the operation will be explained. First, when the circuit is powered on, the polarity of the output of the Schmitt circuit 22 is initially set to positive or negative. For example, the output of the Schmitt circuit 22 causes a communication path switch 24 to be activated.
is closed, the communication path switch 25 is opened, the sweep of the sweep circuit 17 is stopped, and the sweep of the sweep circuit 18 is started. As a result, the side sound protection circuit section 11
(H ₁ ), one circuit network Z _N1 of the balanced circuit network group 15 is connected, and each circuit network Z _N1 of the balanced circuit network group 16 is connected to the side sound protection circuit section 12 (H ₂ ). _ZN2 ,…
...Z _Ni is connected sequentially. Next, when the transmitting signal e _T is input to the transmitting terminal 1, the side sound circuit section 11
(H ₁ ), 12 (H ₂ ) receiver output terminals 3 and 4 have sidetone e.
_S1 and e _S2 occur. Here, the sidetone e _S1 is determined by the balanced network Z _N1 and the line impedance, and e _S2
is determined by the balanced circuit network connected to the side noise prevention circuit section 12 (H ₂ ) and the line impedance. Then, the side sounds e _S1 and e _S2 enter the comparison circuit 21 via the amplifier circuits 13 and 14 and the rectification and smoothing circuits 19 and 20, and the average levels _S1 and _S2 are compared, and the output is sent to the Schmitt circuit 22. be guided. When the sidetone e _S1 is smaller than e _S2 (e _S1 <e _S2 ), the polarity of the output of the Schmitt circuit 22 does not change, and the channel switches 24 and 25 and the sweep circuits 17 and 18 maintain the same state as the initial state. And side sound protection circuit section 12
(H ₂ ) is sequentially switched, for example, P
When the th balanced network Z _NP is connected, the sidetone e _S2
When e _S1 becomes smaller than e S1 (e _S1 >e _S2 ), the polarity of the output of Schmitt circuit 22 is reversed, and channel switch 25 is closed and channel switch 24 is opened. Therefore, the side sound prevention circuit section 12 (H ₂ ) having the smaller side sound is connected to the communication path, and the side sound prevention circuit section 11 (H ₁ ) is disconnected from the communication path. At the same time, the sweep circuit 18
stops the sweep and continues to connect the balanced network Z _NP to the side sound protection circuit section 12 (H ₂ ). On the other hand, the sweep circuit 17 starts sweeping and sweeps Z _N1 , Z _N2 , . . . of the balanced circuit network group 15.
...Z _Ni is sequentially connected to the side sound prevention circuit section 11 (H ₁ ). After that, the size of the sidetone is automatically compared in the same way,
The balanced network with the smallest sidetone is selected from the balanced networks Z _N1 to Z _Ni . Also, when the receiving signal e _L is input to the line terminal 2,
Reception signal outputs e _R1 and e _R2 are generated at the reception output terminals 3 and 4 of the side sound circuit sections 11 (H ₁ ) and 12 (H ₂ ), respectively. However, regardless of the connected balanced circuit network, the side noise prevention circuit section 11 is set so that e _R1 = e _R2 .
(H ₁ ), 12 (H ₂ ), and two comparison signal forming circuits composed of amplifier circuits 13, 14 and rectifier circuits 19, 20 are designed so that the input signals _R1 and _R2 of the comparison circuit 21 are equal. If sections 26 and 27 are designed, the output of comparison circuit 21 will not change even if a received signal is input. Here, side sound prevention circuit parts 11 (H ₂ ), 12 (H ₂ )
If configured as shown in FIG. 2, the levels of the reception signal outputs e _R1 and e _R2 can be made equal regardless of the impedances Z _N1 and Z _N2 of the balanced network. However, in order to increase the detection sensitivity of the sidetone level in order to improve the selection accuracy of the balanced circuit network, in order to set _R1 = _R2 , the degree of symmetry between the comparison signal shaping sections 26 and 27 (hereinafter referred to as balanced extremely high precision is required. Therefore, if the degree of balance between the comparison signal shaping sections 26 and 27 is not sufficiently large, the output of the comparison circuit 21 will change depending on the reception signal, and the selection operation of the balanced circuit network will change regardless of the magnitude of the sidetone level. (hereinafter referred to as malfunction due to reception signal). In order to prevent malfunctions caused by such reception signals, it is necessary to design the comparative signal shaping sections 26 and 27 so that the degree of balance between them is sufficiently high, that is, their input and output characteristics are equal, as described above. However, since this type of conventional side sound prevention circuit section was configured as shown in the example in FIG.
Extremely high precision is required to adjust the balance such as the gain of The disadvantage was that it was difficult to The present invention has been made to eliminate the drawbacks of the prior art as described above, and an object of the present invention is to design two comparison signal shaping sections so that the input/output characteristics of each of them are equal. It is an object of the present invention to provide an automatically switching type side sound prevention circuit which is easy to perform, prevents malfunctions caused by received signals, and improves the accuracy of selecting a balanced circuit network. The key point of the configuration of the present invention is that the comparison signal shaping section is configured by a digital circuit. Next, embodiments of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram showing one embodiment of the present invention. In the figure, 1 is a transmission terminal, 2 is a line terminal, 3 and 4 are reception output terminals of the side sound protection circuit,
5 is a receiver terminal, 11 and 12 are side sound protection circuit parts, 1
7 and 18 are sweep circuits that sequentially connect the balanced circuit network to the side sound prevention circuit section; 15 and 16 are a group of balanced circuit networks; 23
2 is a comparison control unit that compares the magnitude of the sidetone level;
4 and 25 are communication path switches, 26 and 27 are comparison signal forming units, 31 and 32 are analog-to-digital converters, 33 and 34 are gate circuits that divide the digitized signal into multiple word intervals, and 35 and 36 are adders. The circuits 37 and 38 are temporary storage circuits, 39 is a comparison circuit, 40 is a control circuit for controlling the sweep operation of the sweep circuits 17 and 18 and the switching operation of the communication path switches 24 and 25, and 41 is a clock generation circuit. The operation will be explained below. First, when the circuit is powered on, the control circuit 40
is driven, the communication path switch 24 is closed, the communication path switch 25 is opened, the sweep of the sweep circuit 17 is stopped, and the sweep of the sweep circuit 18 is started. Therefore, one of the circuit networks Z N1 in the balanced circuit network group 15 is connected to the side sound prevention circuit section 11 (H ₁ ), and the balanced circuit network Z _N1 is connected to the side sound prevention circuit section 12 (H ₂ ). The circuit networks Z _N1 , Z _N2 , . . . Z _Ni of group 16 are connected in sequence. Next, when the transmitting signal e _T is input to the transmitting terminal 1, side sounds e _S1 and e _S2 are generated at the receiving output terminals 3 and 4 of the side sound protection circuit sections 11 (H ₁ ) and 12 (H ₂ ). and e _S
1 , e _S2 are analog-to-digital converters 31, 3
2 into digital signals e _S1 ', e _S2 ', which are divided into N word intervals by gate circuits 33 and 34. Next, the adder circuits 35 and 36 add the sum of N words (e _S11 ′ to e _S1N ′, e _S21 ′ to e _S2N ′).

【formula】

[Formula] is calculated and each value is stored in temporary storage circuits 37 and 38. Then, the comparison circuit 39 compares the respective sums (this is a comparison of the sum of fixed words, so it is equivalent to the comparison of the average value of N words), and the output of the comparison circuit 39 yields
The control circuit 40 is driven.

In the case of [Equation], the control circuit 40 is not driven, and the communication path switches 24 and 25 and the sweep circuits 17 and 18 maintain the same state. Then, the balanced circuit networks of the side sound protection circuit 12 (H ₂ ) are sequentially switched, and for example, when the Pth balanced circuit network Z _NP is connected,

When [Equation] is reached, the control circuit 40 is driven by the output of the comparison circuit 39, closes the communication path switch 25, and opens the communication path switch 24. Therefore, the side sound prevention circuit section 1 with smaller side sound
2 (H ₂ ) is connected to the communication path, and the side sound protection circuit section 1
1 (H ₁ ) is disconnected from the communication path. At the same time, the sweep circuit 18 stops sweeping and continues to connect the balanced network Z _NP to the side noise prevention circuit section 12 (H ₂ ). On the other hand, the sweep circuit 17 starts sweeping, and the circuit networks Z _N1 , Z _N2 , . . . Z _Ni of the balanced circuit network group 15
(H ₁ ). Thereafter, the magnitude of the sum of the N words of the digitized sidetones is similarly compared, and the balanced circuit network with the smallest sidetone is selected from among the balanced circuit networks Z _N1 to Z _Ni . Furthermore, when the reception signal e _L is input to the line terminal 2, reception signals e _R1 and e _R2 are generated at the reception output terminals 3 and 4 of the side sound protection circuit sections 11 (H ₁ ) and 12 (H ₂ ), respectively. Here, side sound protection circuit parts 11 (H ₁ ), 12
As before, (H ₂ ) can be designed such that e _R1 =e _R2 regardless of the impedance of the connected balanced network. Furthermore, comparison circuit 3
9 inputs,

[Formula] and

Analog-to-digital converters 31 and 3
2. Gate circuits 33 and 34, adder circuits 35 and 3
6. It is necessary to design two comparison signal shaping sections 26 and 27 consisting of temporary storage circuits 37 and 38. Here, two analog-to-digital converters 3
1.32 quantization accuracy is a problem, but when analog signals of the same level are input to two analog-to-digital converters of the same type, the deviation of the digital signals output (i.e., quantization accuracy) is at most the maximum. One lower bit (for example, if the reference voltage is 5V in a 10-bit analog-to-digital converter, the difference between whether the lowest bit becomes "1" or "0" is converted to the voltage of the analog input signal. do
5V/2 ¹⁰ = approximately 4.9mV), the output 2
This problem can be solved by configuring the comparator circuit 39 so that the output of the comparator circuit 39 is not output when there is only a difference of one least significant bit between the two digital signals. That is, the addition circuit 35,
36, the sum of N words is calculated, so when analog signals of the same level are input, the least significant bit of the digital signal output from one analog-to-digital converter is always "1", and the other analog-to-digital converter outputs. Assuming the worst case in which the least significant bit of the digital signal is always "0", the comparator circuit is designed so that the output of the comparator circuit 39 will not occur if the difference is less than the sum of N words, that is, the difference equivalent to N in decimal notation. By providing a threshold value in 39, it is possible to prevent malfunctions caused by deviations in quantization precision between the two analog-to-digital converters 31 and 32. Even in this case, it is not necessary to adjust the balance between the analog-to-digital converters 31 and 32. Since the gate circuit, addition circuit, and temporary storage circuit are all circuits that accumulate and count bits, there are problems with the balance between the gate circuits 33 and 34, the addition circuits 35 and 36, and the temporary storage circuits 37 and 38. There isn't. Therefore, in the case of this invention, two comparison signal forming sections 2
The balance between 6 and 27 can be made sufficiently large. Further, FIG. 4 shows an embodiment in which each circuit is used in a time-division manner so that the two systems of comparison signal forming sections 26 and 27 in FIG. 3 are replaced by one system. In Fig. 4, the same symbols as in Fig. 3 indicate corresponding parts, 42 is a circuit that samples two analog signals input from terminals 3 and 4 at the same time and outputs them in a time-division manner, and 43 is an analog/digital circuit. Converter, 44 is a gate circuit, 45 is an adder circuit,
46 is a switching circuit that causes the temporary storage circuits 37 and 38 to separately store the sum of the two sidetone levels added in a time-division manner. The circuit operation in FIG. 4 is similar to that in FIG. 3. However, in the case of FIG. 4, the clock frequency of the clock generation circuit 41 needs to be set twice that of the case of FIG. 3, since each circuit is used in a time-division manner. As shown in FIG. 4, by handling two analog signals with one analog-to-digital converter 43, the problem of quantization accuracy of the two analog-to-digital converters with the configuration shown in FIG. 3 is solved. , it becomes possible to sufficiently increase the degree of balance of the portions corresponding to the two comparison signal shaping sections 26 and 27 in FIG. 3 more easily than in the case of FIG. Moreover, in the case of FIG. 4, the number of parts can be reduced to about 1/2 compared to the configuration of FIG. 3. Therefore, in the case of the present invention, the selection operation of the balanced circuit network is completely independent of the reception signal and is performed only by the sidetone signal generated by the transmission signal, so that there is no malfunction caused by the reception signal. The selection accuracy of the balanced network can be improved. Furthermore, the detection sensitivity of the magnitude of the two sidetone levels is determined by the number of quantization bits of the analog-to-digital converter, and even if the deviation in the quantization precision of the two analog-to-digital converters is the largest, it is determined by the second bit from the lowest. It becomes possible to identify up to a corresponding level difference. As explained above, according to the present invention, it is possible to sufficiently increase the degree of balance between the two comparison signal shaping sections in the automatically switching type sidetone circuit. As a result, in the selection operation of the balanced circuit network, there is an advantage that the selection accuracy of the balanced circuit network can be improved without causing malfunctions due to the reception signal. Furthermore, by using one comparison signal shaping section in a time-division manner, the problem of quantization accuracy of the two analog-to-digital converters can also be solved. Furthermore, the digitization of the comparison control section of this invention is as follows:
It also has the advantage of being advantageous for downsizing and economy due to the use of ICs, etc.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional automatic switching type side sound prevention circuit, FIG. 2 is a circuit diagram showing an example of the configuration of the side sound prevention circuit section in FIG. 1, and FIG.
FIG. 4 is a block diagram showing another embodiment of the invention. Code explanation, 1...Talking terminal, 2...Line terminal,
3, 4... Receiving output terminal of side sound protection circuit section, 5...
Receiving terminal, 11, 12... side sound protection circuit section, 13,
14... Amplifier circuit, 15, 16... Balanced circuit network group, 17, 18... Sweep circuit, 19, 20... Rectification and smoothing circuit, 21... Comparison circuit, 22... Schmitt circuit, 23... Comparison control Part, 24, 25...
Communication path switch, 26, 27... Comparison signal forming unit, 31, 32... Analog-digital converter, 33, 34... Gate circuit, 35, 36...
Addition circuit, 37, 38...Temporary storage circuit, 39...
... Comparison circuit, 40 ... Control circuit, 41 ... Clock generation circuit, 42 ... Time division circuit, 43 ... Analog-digital converter, 44 ... Gate circuit,
45...addition circuit, 46...switching circuit.

Claims (1)

[Claims] 1 A first terminal into which a transmitting signal is input, a second terminal connected to a line, and a third terminal connected to a receiving circuit.
and a fourth terminal connected to the balanced circuit network, and for suppressing the transmitting signal inputted from the first terminal from being transmitted as sidetone from the third terminal to the receiving circuit. , connected to a pair of first and second side sound prevention circuit sections and fourth terminals of each of the first and second circuit sections via first and second sweeping means, respectively. means for converting the sidetone outputs obtained from the first and second sets of balanced circuit networks and the third terminals of each of the first and second circuit sections into digital signals, and then comparing the digital signals; The plurality of balanced circuit networks of the first and second sets are applied to the fourth terminals of the first and second circuit sections in a time-sharing manner by alternately sweeping the first and second sweeping means. Switching and connecting sequentially, selecting the balanced circuit network that minimizes the sidetone output based on the comparison result output of the comparing means during that time, and continuing the connection,
A side sound protection circuit comprising: control means for connecting the circuit section to which the circuit network belongs to a receiving circuit.