JPS61191063A - Compound semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a photodiode, whose p-n junction is not exposed on an InGaAs surface, by forming the second layer comprising first conducting type In0.53Ga0.47As at a part on the first layer comprising first conducting type InP, implanting impurities in a region including the entire surface of the second layer, thereby forming the PIN photodiodes. CONSTITUTION:On a semi-insulating InP substrate 1, an n-type InP (or InGaAsP close to this) layer 2 is formed. An n-type In0.53Ga0.47As (or InGaAsP close to this) layer 3 is formed at a part on the layer 2. Then Zn is implanted or diffused in a region including the entire surface of the layer 3, and a (p) region 4 is formed. Thus a PIN photodiode 10 is formed. Then, the p-n junction plane of the photodiode 10, which is exposed on the surface, becomes the InP layer 2. Therefore leak currents on the surface can be reduced. When an FET 20 is formed in the layer 2 in the same chip, the surface leak currents at the p-n junction due to the layer 2 and a (p) region 5 at a gate part can be made small.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a compound semiconductor device in which a photodiode having a semiconductor heterojunction and a junction field effect transistor are integrated.

Conventional technology In optical fiber communication in the 1.0 to 1.7 μm band (long wavelength band), high-purity optical fiber has low dispersion in this wavelength band.

Because it exhibits low loss characteristics, it is attracting attention as a means of long-distance transmission. As a light receiving element in this long wavelength band,
Go, InxGal) (Ag 1-7F7 (hereinafter abbreviated as InGaAsP) or InassG*o, a7P
(hereinafter abbreviated as 1nGaAs), a PIN photodiode, an avalanche photodiode, or an integrated element of a PIN photodiode and an amplification field-effect transistor (hereinafter abbreviated as PIN/FICT) is being developed. . Among them, PIN/FIT has low noise,
I
Development is underway using nG4Aj or InGaAgP-based materials.

The above PIN/FIET is made of InP, InGaAs, or InGaAg epitaxially grown on an InP substrate.
The PIN photodetector and FIT are integrated using a layer of P, but the surface layer of InGaAs or InGaAgP, which has a composition close to InGaAs, is extremely unstable, especially at the p-n junction. When exposed to the surface, a large leakage current occurred. InGaA
For s PIN photodiodes, InGaAs
A device with a structure in which a pn junction is formed on the InP surface by forming a mesa structure and diffusing impurities into a region that includes the entire surface of InGaAs, or forming an InP layer on the InGaAs and forming a pn junction on the surface of the InP layer. PIN with impurities partially diffused
elements have been proposed.

However, regarding the leakage current of PIN/FIT, although passivation techniques using polyimide and the like have been studied, the structure has hardly been studied.

FIG. 2 shows the cross-sectional structure of a conventional Prechey-type PIN/FIT, and FIG. 3 shows the cross-sectional structure of a conventional mesa-type PXN/FKT. In FIG. 2, reference numeral 21 denotes a semi-insulating substrate, on which an n-type InGaAs layer is formed, and by diffusing Zn from its surface, a gate diffusion layer 23. A light receiving portion diffusion layer 24 is formed.

25.26, 27.28 are source electrodes, respectively.

These are a gate electrode, a drain electrode, and a light receiving part electrode.

26.28 are connected on the surface, and 27
．． The voltage generated between 28 causes an amplified drain current to flow from 26 to 27.

In FIG. 3, 31 is an n-type In
P layer 32, n-type InGaAS layer 33 and Kp-type InG
A1834 layer is formed and the source electrode 35.a of the F'ET is formed.
Gate electrode 36. The drain electrode 37 is formed of the n-type InP layer 3
It is installed on the surface of 2. 38°39 are respectively,
This is a light receiving part electrode installed on 34 and 32. The operating principle is the planar type P I If/F K T shown in Figure 2.
It is exactly the same.

Problems to be Solved by the Invention The features of the PIN/FIT shown in Fig. 2 are that it has a planar structure and is easy to manufacture, and that InGaAs with high mobility is used for the channel of the FIT. But I
Since it is exposed on the nGaAs 220 surface, there is a problem in that the leakage current is as large as several tens of nm or more. In the P I N/F K T shown in Figure 3, the pn junction in the FET section is exposed on the InP surface, making it possible to reduce surface leakage current; pn
Since the junction is formed on the surface of InGaAs, there is a problem in that it is difficult to ensure low dark current properties.

The present invention solves these problems and replaces the conventional PIN/F
Unlike IT, the pn junction is not exposed to the surface of InGaAs or InGaAsP with a composition similar to this, and Pn has a low dark current.
This realizes IN/FET.

Means for Solving the Problems The present invention provides an I layer of the first conductivity type on a semi-insulating InP substrate.
A first layer of nP or InGaAs zASlyPy is formed, and further a part of the first layer is made of InGaAs of a first conductivity type.
As or 'th layer InxGa, zA! 11 Inz'G2L + whose composition is closer to InGaAs than the yPy layer
It has a second layer of z'As + y'Py', and an impurity for making the second conductivity type is diffused or implanted into a region including the entire surface of the second layer to release the light-receiving element, and The above problem is solved by forming a compound semiconductor device characterized in that an electric circuit such as an FIT is formed in the first layer in a region where the second layer does not exist.

Operation By the above means, the p-n junction is
Since it is exposed on the surface of nGaAsP, surface leakage current is reduced.

EXAMPLE An example of the present invention is shown in FIG. 1 is a semi-insulating substrate, on which θ00's is formed an n-type InP layer 2 with a thickness of about 2 μm as a first layer and an n-type In0.5! layer with a thickness of about 3 μm as a second layer. I
G”O, 47 S layer 3 is formed, InGaAgnGa
Mesa etching is performed except for the As layer. In mesa structure
Z is applied to the region 4 including the entire surface of GaAs and the surface 5 of the InP layer.
n is diffused to form a light receiving section and a gate section of the FET. Note that the impurity may be ion-implanted. 6.
7, 8, and 9 are a source electrode, a gate electrode, a drain electrode, and a light receiving part electrode, respectively. In this example,
The diameter of the light receiving part is 100μmφ, and the gate width is 6μm.
m, and the gate length is 1. According to this structure, the pn junction of the light receiving section is not exposed to the n-type InGaAg surface, but is only exposed to the n-type ZnP surface with low mobility. In addition,
In the second layer 3, the first layer is InxGal-2A31yPy
When the composition of the first layer is Ino, 53Ga
0047 Inx/G2L with high mobility close to As,
-xzAs, y/py tetoFLLd The LD effect of the present invention can be exhibited.

As a result of measuring the characteristics of the PIN/FICT of the above example, it was found that the leakage current could be reduced from about 20 nm to about 0.1 nÅ or less compared to a conventional PIN/FICT of the same size.

In the example, the FiET is formed on the n-InP layer, but a part of the n-InP layer is etched, and the n-type region and the p-type region are formed on the surface of the semi-insulating substrate by diffusion or ion implantation. Even if a FICT is formed by forming a region, it is completely equivalent.

Effects of the Invention As described above, according to the present invention, a P I N/F with low dark current can be obtained.
It is possible to realize ET.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the structure of a PIN/FIT in an embodiment of the present invention, and Fig. 2 is a diagram showing a conventional pre-chip type PIN/FE.
A diagram showing the structure of T, Figure 3 is a conventional mesa-shaped P r N
It is a figure which shows the structure of /FKT. 1...Semi-insulating InP substrate, 2...
N-type InP layer, 3...P-type InGtAs layer, 4
...P region, 6...Gate electrode.

Claims (1)

[Claims] On the semi-insulating InP substrate, InP of the first conductivity type or In
The first _xGa_1_−_xAs_1_−_yP_y
A layer of In_0_. of the first conductivity type is formed in a part of this first layer. _5_3Ga_0_. _4_7As or the above In_xGa_1_-_xAs_1_-_yP_
In_0_. of the composition than y. _5_3Ga_0_. ＿４
In_x_'Ga_1_-_x_'As close to _7As
a second layer _1_−_y_′P_y;
An impurity that makes the region a second conductivity type is diffused or ion-implanted into a region including the entire surface of the layer, and an electric circuit is formed in the first layer in the region where the second layer does not exist. A compound semiconductor device characterized by: