JPS61190953A - Wire bonder - Google Patents

Wire bonder

Info

Publication number
JPS61190953A
JPS61190953A JP60030389A JP3038985A JPS61190953A JP S61190953 A JPS61190953 A JP S61190953A JP 60030389 A JP60030389 A JP 60030389A JP 3038985 A JP3038985 A JP 3038985A JP S61190953 A JPS61190953 A JP S61190953A
Authority
JP
Japan
Prior art keywords
bonding
lead
wire
capillary
wire bonder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60030389A
Other languages
Japanese (ja)
Other versions
JPH0447973B2 (en
Inventor
Hiroshi Munakata
広志 宗像
Nobuhiro Takasugi
高杉 信博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Original Assignee
Hitachi Tokyo Electronics Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Tokyo Electronics Co Ltd, Hitachi Ltd filed Critical Hitachi Tokyo Electronics Co Ltd
Priority to JP60030389A priority Critical patent/JPS61190953A/en
Publication of JPS61190953A publication Critical patent/JPS61190953A/en
Publication of JPH0447973B2 publication Critical patent/JPH0447973B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7825Means for applying energy, e.g. heating means
    • H01L2224/783Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301Capillary
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To enable a bonding at the central position of a lead by mounting an arithmetic operation section computing the position of indication of optimum bonding in the actual lead to a control system. CONSTITUTION:A control system 2 has a recognition section 21, which recognizes an inner lead 18A and an electrode pad 19A for a semiconductor structure 17 form a signal from a TV camera 20 and outputs the central position of the structure 17 as a recognition data, a memory section 22, which previously memorizes the relative quantities of deviation of the positions of indication of optimum bonding (positions where the center of a capillary must be positioned) to the central position of various inner leads and electrode pads as data, and an arithmetic operation section 23 determining the absolute positions of indication of optimum bonding of the inner lead 18A and the electrode pad 19A in the present semiconductor structure 17 by outputs from the recognition section 21 and the deviation data memorized to the memory section 22. Accordingly, a wire bonder can be automated.

Description

【発明の詳細な説明】 〔技術分野〕 本発明はワイヤボンダに関し、特にリードへのワイヤボ
ンディングを高信頼度に行うことのできるワイヤボンダ
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a wire bonder, and particularly to a wire bonder that can perform wire bonding to leads with high reliability.

〔前景技術〕[Foreground technology]

半導体装置のリードフレームやパッケージベース上に固
着した半導体ペレットの電極パッドを、リードフレーム
やパッケージベースの外部導出用のリードに電気的に接
続するためにワイヤボンディングが行われるが、近年の
この種のワイヤボンダは、電極パッドやリードを自動的
に認識した上でその認識位置にワイヤを接続する自動ワ
イヤボンダとして構成されることが多い。たとえば、か
かる技術を述べである例としては、工業調査会発行電子
材料1983年11月号別冊、昭和58年11月15日
発行P、140〜145がある。
Wire bonding is performed to electrically connect the electrode pads of semiconductor pellets fixed on the lead frame or package base of a semiconductor device to the external leads of the lead frame or package base. Wire bonders are often configured as automatic wire bonders that automatically recognize electrode pads and leads and then connect wires to the recognized positions. For example, examples that describe such techniques include Kogyo Kenkyukai, Electronic Materials, November 1983 issue, special edition, November 15, 1983, P, 140-145.

そして、通常では電極パッドやリードの認識位置は夫々
の中心位置に設定しており、ここにボンディングツール
を位置決めしてワイヤボンディングを行うようになって
いる。
Usually, the recognition positions of the electrode pads and leads are set at their respective center positions, and the bonding tool is positioned here to perform wire bonding.

ところで、ワイヤの先端にボールを形成しキャピラリで
このボールを潰しながら熱圧着を行ういわゆるネイルヘ
ッドボンディング法を用いて電極パッドへの第1ボンデ
イングを行うワイヤボンダでは、キャピラリ中心とボン
ディング中心とが常に一致しているので前述した認識方
法をそのまま利用しても、認識位置とワイヤボンディン
グ位置とが常に一致し、電極パッドに良好なボンディン
グを行うことができる。
By the way, in a wire bonder that performs the first bonding to an electrode pad using the so-called nail head bonding method, in which a ball is formed at the tip of the wire and the capillary crushes the ball while performing thermocompression bonding, the center of the capillary and the center of bonding are always aligned. Therefore, even if the above-described recognition method is used as is, the recognition position and the wire bonding position always match, and good bonding to the electrode pad can be performed.

しかしながら、このワイヤボンダでも、第4図、第5図
に示すように、キャピラリ30の一側でワイヤ31を押
し潰しながらリード32への圧着を行う第2ボンディン
グ時には、実際のボンディング位置Bxがキャピラリ3
0の中心位置Cxに対してワイヤ31の張設方向側にず
れてしまうため、リード認識位置(リード中心位置)C
x上に正しくボンディングできなくなる。特に、この現
象はリード32延設方向とワイヤ31の張設方向(平面
xy方向)のずれが大きい程影響が大になり、場合によ
ってはリードの端部にボンディングが行われたり或いは
ボンディングが不良になることもあり、ワイヤボンディ
ングの信頼性を低下させる原因となっている。
However, even with this wire bonder, as shown in FIGS. 4 and 5, during the second bonding in which the wire 31 is pressed onto the lead 32 while being crushed on one side of the capillary 30, the actual bonding position Bx is
The lead recognition position (lead center position) C
It becomes impossible to bond correctly on x. In particular, the effect of this phenomenon becomes greater as the deviation between the extending direction of the leads 32 and the extending direction of the wire 31 (plane This is a cause of deterioration in the reliability of wire bonding.

このため、これまでのこの種のワイヤボンダでは、特に
多ピン型の半導体装置のワイヤボンディングにおいて信
頼性が低くなり、これに対処するには全てのリードに対
して予め最適ボンディング位置を求めかつこれをプログ
ラム化しなければならない等、作業が複雑化されかつ汎
用性に乏しいという問題もある。
For this reason, conventional wire bonders of this type have low reliability, especially when bonding wires to multi-pin semiconductor devices. There are also problems in that the work is complicated, as it has to be programmed, and it lacks versatility.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、常にリードの好ましい位置にワイヤの
ボンディングを行うことができ、半導体装置の信頼性の
向上を図ることのできるワイヤボンダを提供することに
ある。   ゛ 本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。
SUMMARY OF THE INVENTION An object of the present invention is to provide a wire bonder that can always bond a wire to a preferred position on a lead and improve the reliability of a semiconductor device.゛The above and other objects and novel features of the present invention are as follows:
It will become clear from the description of this specification and the accompanying drawings.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。
A brief overview of typical inventions disclosed in this application is as follows.

すなわち、リードの中心位置を認識する認識部と、この
中心位置に対する最適ボンディング指示位置の偏倚量を
記憶する記憶部と、これら認識部と記憶部の各出力に基
づいて実際のリードにおける最適ボンディング指示位置
を算出する演算部とをワイヤボンダの制御系内に備える
ことにより予めセルフテーチングによって求められかつ
記憶部内に記憶された偏倚量によってリードの中心位置
から偏倚された最適ボンディング指示位置を容易に求め
ることができ、良好なワイヤボンディングを可能として
半導体装置の信頼性の向上を図ることができる。
In other words, there is a recognition unit that recognizes the center position of the lead, a storage unit that stores the amount of deviation of the optimum bonding instruction position with respect to this center position, and an optimum bonding instruction for the actual lead based on the respective outputs of these recognition unit and storage unit. By providing a calculation unit that calculates the position in the control system of the wire bonder, it is possible to easily determine the optimal bonding instruction position that is offset from the center position of the lead by the amount of deviation determined in advance by self-teaching and stored in the storage unit. This enables good wire bonding and improves the reliability of the semiconductor device.

〔実施例〕〔Example〕

第1図は本発明を金線を用いたネイルヘッドボンディン
グに適用したワイヤボンダの実施例の全体構成図であり
、図において1はワイヤボンダ本体、2は制御系である
FIG. 1 is an overall configuration diagram of an embodiment of a wire bonder in which the present invention is applied to nail head bonding using gold wire. In the figure, 1 is the wire bonder main body, and 2 is a control system.

前記ワイヤボンダ本体1は、XYテーブル10上に搭載
したボンディングヘッド11に上下揺動可能なボンディ
ングアーム12を支持し、その先端にキャピラリ13を
固着している。このキャピラリ13は公知のように先端
部を円錐筒状とし、前記ボンディングへラド11の上部
に支持したプーリ15に巻回しているボンディングワイ
ヤとしての金線14の先端をその中空孔内に挿通してい
る。また、前記ボンディングアーム12は図外のカム機
構により上下揺動され、この揺動に伴なって前記キャピ
ラリ13を上下動させることは言うまでもない。
The wire bonder main body 1 supports a bonding arm 12 that is vertically swingable on a bonding head 11 mounted on an XY table 10, and has a capillary 13 fixed to the tip thereof. As is well known, this capillary 13 has a conical tip end, and the tip of a gold wire 14 as a bonding wire wound around a pulley 15 supported on the upper part of the bonding rod 11 is inserted into its hollow hole. ing. Further, it goes without saying that the bonding arm 12 is swung up and down by a cam mechanism (not shown), and that the capillary 13 is moved up and down along with this oscillation.

一方、前記キャピラリ13の下方位置には、ボンディン
グステージ16を配置しており、ワイヤボンディングさ
れる半導体構体17をその上に載置している。この半導
体構体17は、本例ではリードフレーム18上に半導体
ペレット19を固着し、リードフレーム18のインナリ
ード18Aと半導体ペレット19の電極パッド19Aと
の間に前記金線14を接続する。
On the other hand, a bonding stage 16 is arranged below the capillary 13, and a semiconductor structure 17 to be wire-bonded is placed thereon. In this example, in this semiconductor structure 17, a semiconductor pellet 19 is fixed on a lead frame 18, and the gold wire 14 is connected between an inner lead 18A of the lead frame 18 and an electrode pad 19A of the semiconductor pellet 19.

また、前記キャピラリ13の上方にはTVカメラ20を
ボンディングヘッドエ1に支持し、前記ボンディングス
テージ16上の半導体構体17の表面を撮像することが
できる。
Further, a TV camera 20 is supported by the bonding head 1 above the capillary 13, and can image the surface of the semiconductor structure 17 on the bonding stage 16.

他方、前記制御系2は、前記TVカメラ20の信号から
半導体構体17のインナリード18Aと電極パッド19
Aを公知のパターン認識法によって認識してその中心位
置を認識データとして出力する認識部21と、予め種々
のインナリードや電極パッドの中心位置に対する最適ボ
ンディング指示位置(キャピラリの中心が位置すべき位
置)の相対的な偏倚量をデータとして記憶しておく記憶
部22と、前記認識部21の出力と記憶部22に記憶さ
れている偏倚データとで現在の半導体構体17における
インナリード18A、電極バッド19Aの絶対的な最適
ボンディング指示位置を決定する演算部23とを備えて
いる。前記記憶部22には、外部の設計データ24と前
記認識部21の夫々の出力に基づいて所定の計算を行う
セルフテーチ°ング部25を付設し、ここから前記した
偏倚データを取り込んでこれを記憶するようになってい
る。また、演算部23は前記XYテーブルエ0をコント
ロールするコントローラ26を接続し、キャピラリ13
を最適ボンディング指示位置に設定することができる。
On the other hand, the control system 2 controls the inner lead 18A of the semiconductor structure 17 and the electrode pad 19 from the signal from the TV camera 20.
A recognition unit 21 recognizes A using a known pattern recognition method and outputs the center position as recognition data, and a recognition unit 21 that recognizes the center position of A by a known pattern recognition method and outputs the center position as recognition data, and determines in advance the optimum bonding instruction position (the position where the center of the capillary should be located) with respect to the center position of various inner leads and electrode pads. ), and the output of the recognition section 21 and the bias data stored in the storage section 22 are used to determine the current inner lead 18A and electrode pad in the semiconductor structure 17. The calculation unit 23 determines the absolute optimum bonding instruction position of 19A. The storage unit 22 is provided with a self-teaching unit 25 that performs predetermined calculations based on external design data 24 and the respective outputs of the recognition unit 21, from which the bias data described above is taken in and stored. It is supposed to be done. Further, the calculation unit 23 is connected to a controller 26 that controls the XY table 0, and the capillary 13
can be set to the optimum bonding instruction position.

なお、前記制御系2の各部は図外のコンピュータによっ
て集中制御されるように構成できることは言うまでもな
い0図中、27はリード等を視覚認識するためのモニタ
である。
It goes without saying that each part of the control system 2 can be configured to be centrally controlled by a computer (not shown), and numeral 27 in FIG.

次に、以上の構成のワイヤボンダを用いたワイヤボンデ
ィング作用を説明する。
Next, a wire bonding operation using the wire bonder having the above configuration will be explained.

先ず、ボンディングステージ16上のワイヤボンディン
グすべき半導体構体17をTVカメラ20で撮像して各
インナリード18Aや電極パッド19Aをモニタ27に
映すと共に、マーカを各インナリード18Aや電極パッ
ド19Aの最適ボンディング指示位置に合わせる。なお
、各電極パッド19Aでは最適ボンディング指示位置は
中心位置に一致するので問題は生ぜずしたがってここで
はインナリード18Aの場合について説明する。
First, the semiconductor structure 17 to be wire-bonded on the bonding stage 16 is imaged with the TV camera 20, each inner lead 18A and electrode pad 19A is displayed on the monitor 27, and a marker is set to determine the optimal bonding of each inner lead 18A and electrode pad 19A. Align with the indicated position. Incidentally, in each electrode pad 19A, the optimum bonding instruction position coincides with the center position, so no problem occurs, and therefore, the case of the inner lead 18A will be explained here.

すなわち、インナリード18A’の場合には、第2図お
よび第3図のようにインナリード18Aの延設方向と、
金線14の張設方向によって、キャピラリ13の中心が
位置するのに最適な位置、つまり最適ボンディング指示
位置f3−nが各々のインナリード18Aの中心位置C
nに対して偏倚される。したがって、この最適ボンディ
ング指示位置へのマーク合わせを設計データ24を利用
する等して、全てのインナリードに対して行う。
That is, in the case of the inner lead 18A', as shown in FIGS. 2 and 3, the direction in which the inner lead 18A extends,
Depending on the stretching direction of the gold wire 14, the optimum position for the center of the capillary 13, that is, the optimum bonding instruction position f3-n, is the center position C of each inner lead 18A.
biased against n. Therefore, mark alignment to this optimum bonding instruction position is performed for all inner leads by using the design data 24 or the like.

一方、認識部21は各インナリード18Aを認識するこ
とにより各リードの中心位置、換言すれば金線14が実
際にボンディングされるべき位置を認識する。
On the other hand, by recognizing each inner lead 18A, the recognition unit 21 recognizes the center position of each lead, in other words, the position where the gold wire 14 is actually to be bonded.

すると、セルフテーチング部25は、認識部21のイン
ナリード18Aの位置認識データ、つまり各インナリー
ド18Aの中心位置Cnと、マーカにより位置合わせさ
れた最適ボンディング指示位置Bnとで両者のXY方向
の偏倚量(Xn、Yn)を自動的に計算し、偏倚データ
として記憶部22に記憶させる。この計算は複数本のイ
ンナリードの全てについて行われ、これによりこの構体
の半導体構体17におけるインナリード18Aの全てに
対し、その中心位置に対する最適ボンディング指示位置
の相対的な偏倚量が記憶される。すなわち、セルフテー
チングが完了される。
Then, the self-teaching unit 25 uses the position recognition data of the inner leads 18A of the recognition unit 21, that is, the center position Cn of each inner lead 18A and the optimal bonding instruction position Bn aligned by the marker, to determine the position of both in the XY direction. The amount of deviation (Xn, Yn) is automatically calculated and stored in the storage unit 22 as deviation data. This calculation is performed for all of the plurality of inner leads, and thereby the relative deviation amount of the optimum bonding instruction position with respect to the center position is stored for all of the inner leads 18A in the semiconductor structure 17 of this structure. That is, self-teaching is completed.

したがって、ワイヤボンディングされる一連の複数個の
半導体構体17が順次ボンディングステージ16上に移
動されてくると、各半導体構体17はその都度TVカメ
ラ20に撮像され、認識部21によって各インナリード
18Aの中心位置が認識される。この中心位置は認識デ
ータとして演算部23へ送出される。
Therefore, when a series of semiconductor structures 17 to be wire bonded are sequentially moved onto the bonding stage 16, each semiconductor structure 17 is imaged by the TV camera 20 each time, and the recognition unit 21 identifies each inner lead 18A. The center position is recognized. This center position is sent to the calculation unit 23 as recognition data.

すると、演算部23は、各インナリード18Aに対応す
る偏倚データを記憶部22から取り込みここで両データ
の相対位置と、前記の中心位置に基づいて、各インナリ
ード18Aにおける絶対的な最適ボンディング指示位置
を算出する。そして、コントローラ26を制御すること
により、XYテ−プル10を位置制御してキャピラリ1
3の中心をこの最適ボンディング指示位置に設定し、イ
ンナリード18Aへのワイヤボンディングを実行するこ
とになる。
Then, the calculation unit 23 fetches the bias data corresponding to each inner lead 18A from the storage unit 22, and calculates the absolute optimal bonding instruction for each inner lead 18A based on the relative position of both data and the center position. Calculate the position. Then, by controlling the controller 26, the position of the XY table 10 is controlled and the capillary 1 is
3 is set at this optimum bonding instruction position, and wire bonding to the inner lead 18A is performed.

このようにして、キャピラリ13を位置設定してワイヤ
ボンディングを行えば、第3図に示すように金、v11
4はキャピラリ13の先端における金線張設方向の一例
においてインナリード18Aに熱圧着され、この位置B
aはキャピラリ13の中心位置Caからは偏倚されるが
、この偏倚量は予め記憶していた前述の偏倚量(X n
 s Y n )に等しく、したがって金、11111
4は最適ボンディング指示位置からこの量だけ偏倚され
たインナリード18Aの中心位置Caにボンディングさ
れることになる。
In this way, if the capillary 13 is positioned and wire bonding is performed, gold, v11 and
4 is thermocompression bonded to the inner lead 18A in an example of the direction in which the gold wire is stretched at the tip of the capillary 13, and this position B
a is deviated from the center position Ca of the capillary 13, but this amount of deviation is equal to the previously memorized amount of deviation (X n
s Y n ), therefore gold, 11111
4 is bonded to the center position Ca of the inner lead 18A, which is offset by this amount from the optimum bonding instruction position.

これにより、最初にセルフテーチングを行っておけば、
以後の同一構成の多数の半導体構体17の全てのインナ
リード18Aに対して最適なワイヤボンディングを自動
的に行うことができる。
By doing this, if you do self-teaching first,
Optimal wire bonding can be automatically performed for all the inner leads 18A of a large number of semiconductor structures 17 having the same configuration thereafter.

〔効果〕〔effect〕

(1)ワイヤボンダの制御系に、リードの中心位置を認
識する認識部と、この中心位置に対する最適ボンディン
グ指示位置の偏倚量を記憶する記憶部と、前記認識部と
記憶部の各出力に基づいて、実際のリードにおける最適
ボンディング指示位置を算出する演算部とを備えている
ので、リードを認識すれば全てのリードに対して最適な
位置へキャピラリを設定し、リードの中心位置へのボン
ディングを可能にして信頼性の高いワイヤボンディング
を実現できる。
(1) The control system of the wire bonder includes a recognition unit that recognizes the center position of the lead, a storage unit that stores the amount of deviation of the optimal bonding instruction position with respect to this center position, and a control system that uses the It is equipped with a calculation unit that calculates the optimal bonding instruction position for the actual lead, so once the lead is recognized, the capillary can be set to the optimal position for all leads, and bonding can be performed at the center position of the lead. Highly reliable wire bonding can be achieved.

(2)中心位置に対する最適ボンディング指示位置の偏
倚量を求めてこれを記憶部に記憶させるセルフテーチン
グ部を有しているので、前記偏倚量をワイヤボンダ自身
で設定でき、ワイヤボンダの自動化を図ることができる
(2) Since it has a self-teaching section that calculates the amount of deviation of the optimum bonding instruction position with respect to the center position and stores it in the storage section, the amount of deviation can be set by the wire bonder itself, and the wire bonder can be automated. Can be done.

以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。
Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

例えば、制御系認識部、記憶部、演算部は夫々独立した
構成とする必要はなく、制御系全体をコンピュータで構
成した上で各部と同一の機能をプログラム化する等ソフ
ト技術で実現できるようにしてもよい。
For example, the control system recognition section, storage section, and calculation section do not need to be configured independently; instead, the entire control system can be configured using a computer, and the same functions as each section can be programmed using software technology. You can.

C利用分野〕 以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である金線を用いたワイヤ
ボンダに適用した場合について説明したが、それに限定
されるものではなく、金線以外のアルミニウム線、銅線
を用いたネイルヘッドボンディング方式のワイヤボンダ
にも適用できる。
C Field of Application] The above explanation has mainly been about the case where the invention made by the present inventor is applied to a wire bonder using gold wire, which is the field of application that formed the background of the invention, but it is not limited thereto. It can also be applied to nail head bonding type wire bonders using aluminum wires and copper wires other than wires.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のワイヤボンダの全体構成図、第2図は
半導体構体の電極パッド、リードを示す一部の拡大平面
図、 第3図はリードの拡大平面図、 第4図および第5図はボンディング位置ずれを説明する
ための図であって、第4図は断面図、第5図は平面図で
ある。 1・・・ワイヤボンダ本体、2・・・制御系、10・・
・XYテーブル、11・・・ボンディングヘッド、12
・・・ボンディングアーム、13・・・キャピラリ、1
4・・・金線、16・・・ボンディングステージ、17
・・・半導体構体、18・・・リードフレーム、18A
・・・インナリード、19・・・半導体ペレット、19
A・・・電極パッド、20・・・TVカメラ、21・・
・認識部、22・・・記憶部、23・・・演算部、24
・・・設計データ、25・・・セルフテーチング部、2
6・・・コントローラ。 第  2  図 1a 第  3  図
FIG. 1 is an overall configuration diagram of the wire bonder of the present invention, FIG. 2 is an enlarged plan view of a portion of the electrode pads and leads of the semiconductor structure, FIG. 3 is an enlarged plan view of the leads, and FIGS. 4 and 5. FIG. 4 is a cross-sectional view and FIG. 5 is a plan view for explaining the bonding position shift. 1... Wire bonder body, 2... Control system, 10...
・XY table, 11...bonding head, 12
...Bonding arm, 13...Capillary, 1
4... Gold wire, 16... Bonding stage, 17
...Semiconductor structure, 18...Lead frame, 18A
... Inner lead, 19 ... Semiconductor pellet, 19
A... Electrode pad, 20... TV camera, 21...
- Recognition unit, 22... Storage unit, 23... Calculation unit, 24
...Design data, 25...Self-teaching section, 2
6... Controller. Figure 2 Figure 1a Figure 3

Claims (1)

【特許請求の範囲】 1、ボンディングステージ上に載置された半導体構体の
リードを認識し、このリード上にワイヤボンダ本体のキ
ャピラリを位置設定してワイヤボンディングを行なわせ
る制御系を備えてなるワイヤボンダであって、前記制御
系は前記リードの中心位置を認識する認識部と、この中
心位置に対するキャピラリが位置すべき最適ボンディン
グ指示位置の偏倚量を記憶する記憶部と、これら認識部
と記憶部の各出力に基づいて現在ワイヤボンディングさ
れるべき半導体構体のリードへの最適ボンディング指示
位置を算出しかつキャピラリをこの位置に設定し得る演
算部とを備えることを特徴とするワイヤボンダ。 2、記憶部はセルフテーチング部を有し、最先の半導体
構体に対して認識したリード中心位置と、このリードに
対して予め設定された最適ボンディング指示位置とから
偏倚量を求め得るように構成してなる特許請求の範囲第
1項記載のワイヤボンダ。
[Claims] 1. A wire bonder equipped with a control system that recognizes the leads of a semiconductor structure placed on a bonding stage, positions a capillary of a wire bonder main body on the leads, and performs wire bonding. The control system includes a recognition unit that recognizes the center position of the lead, a storage unit that stores the amount of deviation of the optimal bonding instruction position at which the capillary should be located with respect to this center position, and each of the recognition unit and storage unit. A wire bonder comprising: an arithmetic unit capable of calculating an optimal bonding instruction position to a lead of a semiconductor structure to be currently wire-bonded based on an output and setting a capillary at this position. 2. The memory section has a self-teaching section, so that the amount of deviation can be determined from the lead center position recognized with respect to the first semiconductor structure and the optimal bonding instruction position set in advance for this lead. A wire bonder according to claim 1, comprising:
JP60030389A 1985-02-20 1985-02-20 Wire bonder Granted JPS61190953A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60030389A JPS61190953A (en) 1985-02-20 1985-02-20 Wire bonder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60030389A JPS61190953A (en) 1985-02-20 1985-02-20 Wire bonder

Publications (2)

Publication Number Publication Date
JPS61190953A true JPS61190953A (en) 1986-08-25
JPH0447973B2 JPH0447973B2 (en) 1992-08-05

Family

ID=12302551

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60030389A Granted JPS61190953A (en) 1985-02-20 1985-02-20 Wire bonder

Country Status (1)

Country Link
JP (1) JPS61190953A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0262777A2 (en) * 1986-09-02 1988-04-06 Kabushiki Kaisha Toshiba Wire bonding device
JPH05160192A (en) * 1991-12-06 1993-06-25 Toshiba Corp Semiconductor fabricating system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0262777A2 (en) * 1986-09-02 1988-04-06 Kabushiki Kaisha Toshiba Wire bonding device
EP0262777A3 (en) * 1986-09-02 1989-08-23 Kabushiki Kaisha Toshiba Wire bonding device wire bonding device
JPH05160192A (en) * 1991-12-06 1993-06-25 Toshiba Corp Semiconductor fabricating system

Also Published As

Publication number Publication date
JPH0447973B2 (en) 1992-08-05

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