JPS61190672A - Integrator - Google Patents

Integrator

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Publication number
JPS61190672A
JPS61190672A JP3017185A JP3017185A JPS61190672A JP S61190672 A JPS61190672 A JP S61190672A JP 3017185 A JP3017185 A JP 3017185A JP 3017185 A JP3017185 A JP 3017185A JP S61190672 A JPS61190672 A JP S61190672A
Authority
JP
Japan
Prior art keywords
signal
inversion
circuit
output signal
integrator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3017185A
Other languages
Japanese (ja)
Other versions
JPS6360434B2 (en
Inventor
Toshiro Sakane
坂根 敏朗
Sadao Takenaka
竹中 貞夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3017185A priority Critical patent/JPS61190672A/en
Publication of JPS61190672A publication Critical patent/JPS61190672A/en
Publication of JPS6360434B2 publication Critical patent/JPS6360434B2/ja
Granted legal-status Critical Current

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Abstract

PURPOSE:To obtain an integrator of small integration output voltage drift against fluctuation of temperature of a circular or fluctuation of power source voltage by leading middle point voltage of an inversion and a non-inversion signal to an input terminal of a differential amplifier circuit as a reference signal. CONSTITUTION:An input pulse signal is waveform shaped by a D type flip-flop 11, and the non-inversion output signal Q is inputted to an integrating circuit 12 to find an integration value. The integration value is further inputted to an inversion input terminal of an operational amplifier 15. Middle point voltage between a non-inversion output signal Q and an inversion output signal Q' is inputted to another non-inversion input terminal of the operational amplifier 15 as a reference signal, and the operational amplifier 15 amplifies and outputs the integration value from the integrating circuit 12 making the middle point voltage a basis. At this time, even if the inputted non-inversion output signal Q causes fluctuation of level, the middle point voltage fluctuates by the same amount, and fluctuation of level is canceled by the operational amplifier 15.

Description

【発明の詳細な説明】 〔概 要〕 積分器に関するものであり、入力パルス信号から得た反
転信号と非反転信号のうちの一方を積分した電圧と、両
信号の中点電圧との差を差動増幅回路で出力することに
より、温度変動、電源電圧変動などに起因する出力電圧
ドリフトの少ない積分器を実現している。
[Detailed Description of the Invention] [Summary] This relates to an integrator that calculates the difference between the voltage obtained by integrating one of an inverted signal and a non-inverted signal obtained from an input pulse signal and the midpoint voltage of both signals. By outputting from a differential amplifier circuit, an integrator with less output voltage drift caused by temperature fluctuations, power supply voltage fluctuations, etc. is realized.

〔産業上の利用分野〕[Industrial application field]

本発明は積分器に関する。本発明の積分器は、例えばデ
ィジタル通信システムにおいて用いられるトランスバー
サル等化器の積分回路などに適用することが可能である
The present invention relates to an integrator. The integrator of the present invention can be applied to, for example, an integrating circuit of a transversal equalizer used in a digital communication system.

トランスバーサル等化器ではタップ係数を決める相関器
に積分器を用いていて、出力電圧ト3リフトの少ない積
分器が望まれている。
In a transversal equalizer, an integrator is used as a correlator for determining tap coefficients, and an integrator with a small output voltage lift is desired.

〔従来の技術〕[Conventional technology]

従来の一般的な積分器が第4図に示される。従来形の積
分器は演算増幅器21の人出方間帰還回路にキャパシタ
C20と抵抗器R20からなる時定数回路を備える。こ
の積分器においては、デユーティ比の変化するパルス信
号が抵抗器R21を介して入力されてアナログ量の積分
出力値が出力され、デユーティ比が50%のときに積分
出力値が零となるように可変抵抗器VR20でオフセッ
ト調整が行われる。
A conventional general integrator is shown in FIG. The conventional integrator includes a time constant circuit consisting of a capacitor C20 and a resistor R20 in the output feedback circuit of the operational amplifier 21. In this integrator, a pulse signal whose duty ratio changes is inputted via the resistor R21, and an integrated output value of an analog quantity is outputted, so that the integrated output value becomes zero when the duty ratio is 50%. Offset adjustment is performed with variable resistor VR20.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

第4図の積分器においては、周囲温度変動あるいは電源
電圧変動等により入力信号レベルがドリフトするとそれ
がそのまま積分器出力電圧のドリフトとなって現れると
いう問題点がある。
The integrator shown in FIG. 4 has a problem in that if the input signal level drifts due to ambient temperature fluctuations or power supply voltage fluctuations, this will directly appear as a drift in the integrator output voltage.

したがって本発明の目的は、回路の温度変動あるいは電
源電圧変動等に対しても積分出力電圧ドリフトの少ない
積分器を提供することにある。
Therefore, it is an object of the present invention to provide an integrator with less integrated output voltage drift even with circuit temperature fluctuations or power supply voltage fluctuations.

c問題点を解決するための手段〕 上述の問題点を解決するために、第1図に示すように、
入力パルス信号の反転信号および非反転信号を作成する
回路1、該反転信号および非反転信号の一方の信号を積
分する積分回路2、該反転信号および非反転信号の中点
電圧を取り出す回路3、および、該積分回路の積分出力
信号と咳取り出す回路の中点電圧信号とがそれぞれ入力
される差動増幅回路4、を備えた積分器が提供される。
Measures for solving problem C] In order to solve the above problem, as shown in Figure 1,
A circuit 1 that creates an inverted signal and a non-inverted signal of an input pulse signal, an integrating circuit 2 that integrates one of the inverted signal and the non-inverted signal, a circuit 3 that extracts the midpoint voltage of the inverted signal and the non-inverted signal, An integrator is provided which includes a differential amplifier circuit 4 to which the integrated output signal of the integrating circuit and the midpoint voltage signal of the cough removal circuit are respectively input.

〔作 用〕[For production]

入力パルス信号の反転信号と非反転信号のうちの一方は
積分回路2で積分されて積分値が求められる。この積分
値は差動増幅回路4で増幅されることとなるが、差動増
幅回路は一方の入力端子に反転および非反転信号の中点
電圧が基準信号として導かれているので、入力パルス信
号が温度変動あるいは電源電圧変動などにより電圧レベ
ルのドリフトを生じても、該基準信号も一諸にドリフト
し、結局これらのドリフトは時間的に平均すると差動増
幅回路4で相殺されることとなり、最終的な積分出力信
号には現れない。
One of the inverted signal and the non-inverted signal of the input pulse signal is integrated by an integrating circuit 2 to obtain an integral value. This integral value will be amplified by the differential amplifier circuit 4, but since the differential amplifier circuit has one input terminal led to the midpoint voltage of the inverted and non-inverted signals as a reference signal, the input pulse signal Even if a voltage level drift occurs due to temperature fluctuations or power supply voltage fluctuations, the reference signal also drifts, and eventually these drifts are canceled out by the differential amplifier circuit 4 when averaged over time. It does not appear in the final integrated output signal.

〔実施例〕〔Example〕

本発明の一実施例としての積分器が第2図に示される。 An integrator according to one embodiment of the invention is shown in FIG.

第2図において、D形フリフプフロノプ11のD入力端
子には、デユーティ比が可変制御されるパルス信号が入
力される。D形フリップフロップ11は非反転出力信号
Qと反転出力信号間とを出力しており、非反転出力信号
Qは積分回路12を介して演算増幅器15の反転入力端
子に導かれる。
In FIG. 2, a pulse signal whose duty ratio is variably controlled is input to the D input terminal of the D-type flip-flop 11. The D-type flip-flop 11 outputs between a non-inverted output signal Q and an inverted output signal, and the non-inverted output signal Q is led to an inverted input terminal of an operational amplifier 15 via an integrating circuit 12.

また非反転出力信号Qと反転出力信号間とは抵抗分圧器
R1とR2(R1=R2)によりその中点電圧が求めら
れ、この中点電圧は一端が接地あるいは基準電圧に接続
されたオフセット調整用の可変抵抗器VRIを経て演算
増幅器15の非反転入力端子に基準信号として導かれる
。第4図にはこの非反転出力信号Qと反転出力信号間の
波形が示される。この波形図からも分かるように、中点
電圧は2つの波形Q、、!:Tが交差する点、例えば入
力信号がTTLレベルの時はTTLレベルの約半分の動
電圧となる。
Moreover, the midpoint voltage between the non-inverted output signal Q and the inverted output signal is determined by resistor voltage dividers R1 and R2 (R1=R2), and this midpoint voltage is offset adjusted by connecting one end to the ground or reference voltage. The signal is guided to the non-inverting input terminal of the operational amplifier 15 as a reference signal via the variable resistor VRI. FIG. 4 shows the waveform between the non-inverted output signal Q and the inverted output signal. As you can see from this waveform diagram, the midpoint voltage has two waveforms Q...! : At the point where T intersects, for example, when the input signal is at TTL level, the dynamic voltage is approximately half of the TTL level.

演算増幅器15は差動増幅回路として働くものであり、
帰還抵抗器R3が接続されており、その出力信号は積分
装置の最終的な積分出力信号となる。
The operational amplifier 15 works as a differential amplifier circuit,
A feedback resistor R3 is connected and its output signal becomes the final integrated output signal of the integrator.

この第2図装置では、入力パルス信号のデユーティ比が
50%のときに演算増幅器15の出力信号すなわち積分
出力信号が零となるように積分回路12の積分定数およ
び可変抵抗器VRIによるオフセット・レベルが調整さ
れる。
In the device shown in FIG. 2, the integration constant of the integrating circuit 12 and the offset level by the variable resistor VRI are adjusted so that the output signal of the operational amplifier 15, that is, the integrated output signal becomes zero when the duty ratio of the input pulse signal is 50%. is adjusted.

第2図装置の動作が以下に説明される。The operation of the FIG. 2 apparatus will now be described.

入力パルス信号はD形フリップフロップ11で打ち直さ
れて波形整形され、その非反転出力信号Qは積分回路1
2に入力されて積分値が求められ、その積分値はさらに
演算増幅器15の一方の反転入力端子に入力される。
The input pulse signal is reshaped and waveform-shaped by the D-type flip-flop 11, and its non-inverted output signal Q is sent to the integrating circuit 1.
2 to obtain an integral value, and the integral value is further input to one inverting input terminal of the operational amplifier 15.

演算増幅器15の他方の非反転入力端子には非反転出力
信号Qと反転出力信号間の中点電圧が基準信号として入
力されているから、演算増幅器15はこの中点電圧を基
準にして積分回路12からの積分値を増幅し出力する。
Since the midpoint voltage between the noninverting output signal Q and the inverting output signal is input as a reference signal to the other non-inverting input terminal of the operational amplifier 15, the operational amplifier 15 performs an integration circuit using this midpoint voltage as a reference. The integrated value from 12 is amplified and output.

いま装置周囲の温度変動あるいは電源電圧変動等により
入力パルス信号の電圧レベルが変化したものとする。す
ると第5図に示される非反転出力信号Qおよび反転出力
信号間の電圧レベルはそのレベル変化に従い共に上昇す
るか、あるいは下降する。これはその中点電圧について
も同様である。
Now assume that the voltage level of the input pulse signal has changed due to temperature fluctuations around the device or power supply voltage fluctuations. Then, the voltage levels between the non-inverted output signal Q and the inverted output signal shown in FIG. 5 either rise or fall in accordance with the level change. The same applies to the midpoint voltage.

したがって入力信号の電圧レベル変動にともない積分回
路12に入力される非反転出力信号Qはレベル変動を生
じることになるが、それと同じ大きさだけ中点電圧も変
動するので、このレベル変動は時間的に平均すると演算
増幅器15で相殺されることとなり、最終的な積分器の
積分出力信号には現れない。
Therefore, as the voltage level of the input signal changes, the level of the non-inverted output signal Q input to the integrating circuit 12 will change, but since the midpoint voltage will also change by the same amount, this level change will occur over time. When averaged over , it is canceled out by the operational amplifier 15 and does not appear in the final integrated output signal of the integrator.

本発明の実施にあたっては種々の変形態様をとることが
可能である。例えば第2回の実施例では入力パルス信号
の反転および非反転の出力信号を得るための回路として
D形フリップフロップを用いているが、これに限らず例
えば入力パルス信号を2分岐してその一方をインバータ
を介するようにした回路であワてもよい。また同実施例
では入力パルス信号の非反転出力信号を積分回路に入力
させているが、もちろん反転出力信号を入力させるもの
であってもよい。
Various modifications can be made in carrying out the invention. For example, in the second embodiment, a D-type flip-flop is used as a circuit for obtaining inverted and non-inverted output signals of the input pulse signal, but the invention is not limited to this, and for example, the input pulse signal can be split into two and one of the two is used. It is also possible to use a circuit that uses an inverter. Further, in the same embodiment, the non-inverted output signal of the input pulse signal is inputted to the integrating circuit, but it is of course possible to input the inverted output signal.

更に演算増幅器の出力電圧にリミッタ効果を持たせる為
に、第2図の積分器14内に示す様なダイオードD、、
Dt、抵抗R4,R5からなる回路を抵抗R3に並列に
接続することにより、第3図に示す様なリミッタ特性を
持たせることが可能である。
Furthermore, in order to have a limiter effect on the output voltage of the operational amplifier, a diode D as shown in the integrator 14 in FIG.
By connecting a circuit consisting of Dt, resistors R4 and R5 in parallel to resistor R3, it is possible to provide limiter characteristics as shown in FIG.

本発明に係る積分器の具体的な適用例が第6図に示°さ
れる。第6図の装置は多値直交振幅変調方式を用いたデ
ィジタル通信システムに用いられるトランスバーサル等
化器である。
A specific application example of the integrator according to the present invention is shown in FIG. The device shown in FIG. 6 is a transversal equalizer used in a digital communication system using a multilevel orthogonal amplitude modulation method.

第6図において、記号Tで表わされるブロックはアナロ
グ遅延線、同様にΣはサムアンプ、DECは識別回路、
FFはフリップフロップ、SRは遅延素子としてのシフ
トレジスタであり、図中の排他的論理和回路は相関器と
して働く。記号fであられされるブロックが本発明に係
る積分器であり、その積分出力信号によって図面左側の
対応する乗算器の係数が制御される。
In FIG. 6, the block represented by the symbol T is an analog delay line, Σ is a sum amplifier, DEC is an identification circuit,
FF is a flip-flop, SR is a shift register as a delay element, and the exclusive OR circuit in the figure works as a correlator. The block denoted by the symbol f is an integrator according to the present invention, and its integral output signal controls the coefficients of the corresponding multiplier on the left side of the drawing.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、装置の温度変動あるいは電源電圧変動
等により入力ディジタル信号がドリフトした場合にも、
最終的な積分出力信号における電圧ドリフトは大幅に低
減される。
According to the present invention, even if the input digital signal drifts due to temperature fluctuations in the device or power supply voltage fluctuations,
Voltage drift in the final integrated output signal is significantly reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の原理ブロック図、第2図は本発明の一
実施例としての積分器の回路図、第3図は本発明による
リミッタ特性図、第4図は従来形の積分器の回路図、第
5図は第2図装置における ゛D形ラフリップフロップ
出力波形図、第6図は本発明の積分器を適用したトラン
スバーサル等化器のブロック図である。 1・・・反転・非反転信号作成回路、 2.12・・・積分回路、 3.13・・・中点電圧作成回路、 4.14・・・差動増幅回路、 11・・・D形フリップフロップ、 21、31・・・演算増幅器。 第1図 本発明の原理ブロック図 弗30 本発明によるlJミッタ特性図
Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a circuit diagram of an integrator as an embodiment of the present invention, Fig. 3 is a limiter characteristic diagram according to the present invention, and Fig. 4 is a diagram of a conventional integrator. 5 is a diagram of the D-type rough flip-flop output waveform in the device shown in FIG. 2, and FIG. 6 is a block diagram of a transversal equalizer to which the integrator of the present invention is applied. 1... Inverting/non-inverting signal generation circuit, 2.12... Integrating circuit, 3.13... Midpoint voltage generation circuit, 4.14... Differential amplifier circuit, 11... D type Flip-flop, 21, 31... operational amplifier. Fig. 1 Block diagram of the principle of the present invention 30 lJ transmitter characteristics diagram according to the present invention

Claims (1)

【特許請求の範囲】 1、入力パルス信号の反転信号および非反転信号を作成
する回路(1)、 該反転信号および非反転信号の一方の信号を積分する積
分回路(2)、 該反転信号および非反転信号の中点電圧を取り出す回路
(3)、および、 該積分回路の積分出力信号と該取り出す回路の中点電圧
信号とがそれぞれ入力される差動増幅回路(4)、 を備えた積分器。
[Claims] 1. A circuit (1) that creates an inverted signal and a non-inverted signal of an input pulse signal, an integrating circuit (2) that integrates one of the inverted signal and the non-inverted signal, the inverted signal and An integrator comprising: a circuit (3) for extracting a midpoint voltage of a non-inverted signal; and a differential amplifier circuit (4) to which an integral output signal of the integrator circuit and a midpoint voltage signal of the retrieving circuit are respectively input. vessel.
JP3017185A 1985-02-20 1985-02-20 Integrator Granted JPS61190672A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3017185A JPS61190672A (en) 1985-02-20 1985-02-20 Integrator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3017185A JPS61190672A (en) 1985-02-20 1985-02-20 Integrator

Publications (2)

Publication Number Publication Date
JPS61190672A true JPS61190672A (en) 1986-08-25
JPS6360434B2 JPS6360434B2 (en) 1988-11-24

Family

ID=12296302

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3017185A Granted JPS61190672A (en) 1985-02-20 1985-02-20 Integrator

Country Status (1)

Country Link
JP (1) JPS61190672A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04342674A (en) * 1991-05-17 1992-11-30 Mitsubishi Motors Corp Floor for vehicle and manufacture thereof
JP2009092381A (en) * 2007-10-03 2009-04-30 Japan Aviation Electronics Industry Ltd Geomagnetic sensor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04342674A (en) * 1991-05-17 1992-11-30 Mitsubishi Motors Corp Floor for vehicle and manufacture thereof
JP2009092381A (en) * 2007-10-03 2009-04-30 Japan Aviation Electronics Industry Ltd Geomagnetic sensor device

Also Published As

Publication number Publication date
JPS6360434B2 (en) 1988-11-24

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