JPS61189008A - Automatic gain control amplifier - Google Patents

Automatic gain control amplifier

Info

Publication number
JPS61189008A
JPS61189008A JP2769285A JP2769285A JPS61189008A JP S61189008 A JPS61189008 A JP S61189008A JP 2769285 A JP2769285 A JP 2769285A JP 2769285 A JP2769285 A JP 2769285A JP S61189008 A JPS61189008 A JP S61189008A
Authority
JP
Japan
Prior art keywords
circuit
voltage
holding
output
amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2769285A
Other languages
Japanese (ja)
Inventor
Keiichi Nishikawa
啓一 西川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2769285A priority Critical patent/JPS61189008A/en
Publication of JPS61189008A publication Critical patent/JPS61189008A/en
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To shorten the response time by connecting a rectifying element which conducts by a constant forward voltage, between a control terminal of an amplifier circuit and an input terminal of a comparing circuit, and holding a voltage difference between the terminals within a prescribed value. CONSTITUTION:A peak holding circuit 2 sets a crest value of an output signal Vout as a holding voltage V2. A comparing circuit 3 compares this holding voltage V2 and a reference voltage Vref, but its output V3 is delayed by a delay time of the comparing circuit 3 after the holding voltage V2 has risen. Also, a smoothing circuit 4 also generates an output voltage Vcont with a prescribed delay time. However, during this delay time, the holding voltage V2 of the peak holding circuit 2 and the output voltage Vcont of the smoothing circuit 4 exceeds a forward voltage of a diode 5, therefore, a current flows through the diode 5 to the smoothing circuit 4 from the peak holding circuit 2, and as a result, at the almost same time as a rise of the holding voltage V2 of the peak holding circuit 2, the output of the smoothing circuit 4, namely, the control voltage Vcont rises.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、増幅利得を自動的に制御する増幅器に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an amplifier that automatically controls amplification gain.

〔従来の技術〕[Conventional technology]

第3図は従来の自動利得制御増幅器の一例を示すブロッ
ク図であり、図において1は制御電圧Vcontにより
利得を制御できる増幅回路、2は上記増幅回路lで入力
信号Vinが増幅された出力信号Voutの波高値を保
持するピークホールド回路、3は上記ピークホールド回
路2で保持された保持電圧■2と予め設定された基準電
圧Vrefとを比較する比較回路、4は例えば、コンデ
ンサC1,C2と抵抗Rより構成され、上記比較回路3
の出力V3を平滑化し、上記増幅回路1の利得を制御す
る制御電圧Vcontを発生させる平滑回路である。
FIG. 3 is a block diagram showing an example of a conventional automatic gain control amplifier. In the figure, 1 is an amplifier circuit whose gain can be controlled by a control voltage Vcont, and 2 is an output signal obtained by amplifying the input signal Vin in the amplifier circuit 1. A peak hold circuit that holds the peak value of Vout; 3 a comparison circuit that compares the holding voltage 2 held by the peak hold circuit 2 with a preset reference voltage Vref; 4, for example, a comparison circuit with capacitors C1 and C2; Comprising a resistor R, the comparison circuit 3
This is a smoothing circuit that smoothes the output V3 of the amplifier circuit 1 and generates a control voltage Vcont that controls the gain of the amplifier circuit 1.

次に動作について説明する。なお、第4図はこの従来例
における各信号波形図である。増幅回路lに長時間にわ
たり入力信号Vinがないと、出力Voutには何も発
生せず、このためピークホールド回路2の保持電圧V2
はOV付近となる。
Next, the operation will be explained. Note that FIG. 4 is a diagram of each signal waveform in this conventional example. If there is no input signal Vin to the amplifier circuit 1 for a long time, nothing will occur at the output Vout, and therefore the holding voltage V2 of the peak hold circuit 2 will decrease.
is near OV.

この保持電圧V2は基準電圧Vrefより十分像いため
、比較回路3の出力■3は負の最大電圧となる。平滑回
路4は上記比較回路3の出力■3を平滑化するが、この
場合は比較回路3の出力v3が長時間食の最大電圧にな
っているため平滑回路4の出力、すなわち制御電圧Vc
ontも負の最大電圧になり、この結果増幅回路1の利
得は最大となる。
Since this holding voltage V2 is sufficiently higher than the reference voltage Vref, the output (3) of the comparator circuit 3 becomes the negative maximum voltage. The smoothing circuit 4 smoothes the output 3 of the comparison circuit 3, but in this case, since the output v3 of the comparison circuit 3 is the maximum voltage of the long eclipse, the output of the smoothing circuit 4, that is, the control voltage Vc
ont also becomes the maximum negative voltage, and as a result, the gain of the amplifier circuit 1 becomes maximum.

この状態で増幅回路1にある振幅をもった入力信号Vi
nが入力されると、増幅回路1は最大利得で入力信号V
inを増幅し、所定の振幅以上の出力信号Voutを出
力する。ピークホールド回路2はこの出力信号Vout
の波高値を保持し、比較回路3はこの保持電圧■2と基
準電圧Vrefを比較する。この時、増幅回路1の°出
力信号Voutは通常より振幅が大きいため、保持電圧
■2は基準電圧Vrefよりも高(なり、比較回路3の
出力■3が通常よりも高い電圧となる。
In this state, the input signal Vi with a certain amplitude to the amplifier circuit 1
When n is input, the amplifier circuit 1 receives the input signal V at maximum gain.
in and outputs an output signal Vout having a predetermined amplitude or more. The peak hold circuit 2 receives this output signal Vout
The comparator circuit 3 compares this held voltage (2) with the reference voltage Vref. At this time, since the output signal Vout of the amplifier circuit 1 has a larger amplitude than usual, the holding voltage 2 becomes higher than the reference voltage Vref, and the output 3 of the comparator circuit 3 becomes a higher voltage than usual.

平滑回路4はこの出力v3を平滑化し、制御電圧Vco
ntとする。これにより増幅回路1の利得は下がり、こ
の繰り返しによりピークホールド回路2の保持電圧■2
と基準電圧Vrefがほぼ等しくなるように増幅回路1
の利得が制御され、この結果増幅回路1の出力信号Vo
uLの振幅は入力信号Vinの振幅にかかわらずほぼ一
定となる。
The smoothing circuit 4 smoothes this output v3 and makes the control voltage Vco
nt. As a result, the gain of the amplifier circuit 1 decreases, and by repeating this, the holding voltage of the peak hold circuit 2
and the reference voltage Vref are approximately equal to each other.
As a result, the output signal Vo of the amplifier circuit 1 is controlled.
The amplitude of uL is approximately constant regardless of the amplitude of the input signal Vin.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、従来の自動利得制御増幅器は以上のように構成
されていたので、比較回路3や平滑回路4等が本来存す
る遅延時間により、無信号入力から信号入力へ変化した
際の出力信号Voutの振幅を一定にするまでの応答時
間が長く、このため入力信号Vinの変化時点よりこの
応答時間が経過するまでは使用できないなどの問題点が
あった。
However, since the conventional automatic gain control amplifier is configured as described above, the amplitude of the output signal Vout when changing from a no-signal input to a signal input is It takes a long response time to make the input signal Vin constant, and therefore there is a problem that it cannot be used until this response time has elapsed from the time when the input signal Vin changes.

この発明は上記のような問題点を解消するためになされ
たもので、応答時間が短く、入力信号振幅の変動に伴な
う使用不能期間を少なくできる自動利得制御増幅器を得
ることを目的とするものである。
This invention was made to solve the above-mentioned problems, and an object of the present invention is to provide an automatic gain control amplifier that has a short response time and can reduce unusable periods due to fluctuations in input signal amplitude. It is something.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る自動利得制御増幅器は、増幅回路の制御
端子と比較回路の入力端子間に、一定の順方向電圧で導
通ずる整流素子を接続し、上記各端子間の電圧差を一定
値以内に保つようにしたものである。
The automatic gain control amplifier according to the present invention connects a rectifying element that conducts at a constant forward voltage between the control terminal of the amplifier circuit and the input terminal of the comparator circuit, and keeps the voltage difference between the terminals within a constant value. It was designed to be kept.

〔作用〕[Effect]

この発明においては、増幅回路の制御端子と比較回路の
入力端子間の電圧差が一定値以上となると整流素子が導
通することにより、入力信号振幅の変化に対する遅延時
間を補償するように作用する。
In this invention, when the voltage difference between the control terminal of the amplifier circuit and the input terminal of the comparator circuit exceeds a certain value, the rectifying element becomes conductive, thereby acting to compensate for the delay time with respect to changes in the input signal amplitude.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第1
図において、1は制御端子1aに印加される制御電圧V
contにより利得が変化する増幅回路、2はこの増幅
回路1の出力信号Voutの波高値を保持するピークホ
ールド回路、3はこのピークホールド回路2により保持
され、入力端子3aに印加される電圧V2と予め設定さ
れた基準電圧Vrefとを比較する比較回路、4は例え
ば2つのコンデンサCIと02及び抵抗Rがπ型に接続
されることにより構成された平滑回路、5はピークホー
ルド回路2の出力、すなわち比較回路3の入力端子3a
にアノード、平滑回路4の出力、すなわち増幅回路1の
制御端子1aにカソードを接続した整流素子として最も
一般的なダイオードであり、保持電圧■2が制御電圧V
contより一定の順方向電圧以上高くなった場合に導
通ずる。
An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is the control voltage V applied to the control terminal 1a.
2 is a peak hold circuit that holds the peak value of the output signal Vout of this amplifier circuit 1; 3 is a voltage V2 held by this peak hold circuit 2 and applied to the input terminal 3a; 4 is a smoothing circuit configured by connecting two capacitors CI and 02 and a resistor R in a π type; 5 is the output of peak hold circuit 2; In other words, the input terminal 3a of the comparator circuit 3
This is the most common diode as a rectifying element, with its anode connected to the output of the smoothing circuit 4, that is, the control terminal 1a of the amplifier circuit 1, and the holding voltage 2 is the control voltage V.
It becomes conductive when the forward voltage becomes higher than cont by a certain forward voltage.

次に動作について説明する。なお、第2図は本実施例に
おける各信号波形図である。入力信号Vinが長期にわ
たり入力されないと増幅回路1の出力Voutには何も
発生せず、このためピークホールド回路2の保持電圧V
2はほぼ0■付近となっている。この保持電圧V2は基
準電圧Vrefより十分像いため比較回路3の出力■3
は負の最大電圧となる。この時、ピークホールド回路2
の保持電圧■2と比較回路3の出力■3との差はダイオ
ード5の順方向電圧より大きいため、平滑回路4の出力
電圧、すなわち制御電圧Vcontはピークホールド回
路2の保持電圧■2よりダイオード5の順方向電圧骨だ
け電圧降下した電圧となる。
Next, the operation will be explained. Note that FIG. 2 is a diagram of each signal waveform in this embodiment. If the input signal Vin is not input for a long period of time, nothing will occur at the output Vout of the amplifier circuit 1, and therefore the holding voltage V of the peak hold circuit 2 will decrease.
2 is almost 0 ■. Since this holding voltage V2 is sufficiently higher than the reference voltage Vref, the output of the comparator circuit 3 is
is the maximum negative voltage. At this time, peak hold circuit 2
Since the difference between the holding voltage (■2) and the output (■3) of the comparator circuit 3 is larger than the forward voltage of the diode 5, the output voltage of the smoothing circuit 4, that is, the control voltage Vcont, is smaller than the holding voltage (■2) of the peak hold circuit 2. The voltage is lowered by the forward voltage of 5.

この状態で通常の振幅をもつ入力信号Vinが入力され
ると増幅回路1は通常より大きな利得で増幅し、出力信
号Voutを出力する。このときの出力信号Voutの
振幅は期待する振幅よりも大きなものとなる。ピークホ
ールド回路2は、この出力信号Voutの波高値を保持
電圧■2とする。比較回路3はこの保持電圧■2と基準
電圧Vrefを比較するが、その出力■3は保持電圧V
2が立上ってから比較回路3の遅延時間だけ遅れる。ま
た平滑回路4も一定の遅延時間をもって出力電圧■C0
ntを発生させる。しかしこの遅延時間の間は、ピーク
ホールド回路2の保持電圧■2と平滑回路4の出力電圧
Vcontはダイオード5の順方向電圧以上あり、この
ためピークホールド回路2より平滑回路4の方へダイオ
ード5を通って電流が流れ、この結果ピークホールド回
路2の保持電圧V2の立上りとほぼ同時に平滑回路4の
出力、すなわち制御電圧Vcontが立上がることにな
る。
In this state, when an input signal Vin having a normal amplitude is input, the amplifier circuit 1 amplifies it with a gain larger than normal and outputs an output signal Vout. The amplitude of the output signal Vout at this time is larger than the expected amplitude. The peak hold circuit 2 sets the peak value of the output signal Vout as a holding voltage (2). The comparator circuit 3 compares this holding voltage (2) with the reference voltage Vref, and its output (3) is the holding voltage V.
2 is delayed by the delay time of the comparison circuit 3. In addition, the smoothing circuit 4 also outputs a voltage C0 with a certain delay time.
Generate nt. However, during this delay time, the holding voltage 2 of the peak hold circuit 2 and the output voltage Vcont of the smoothing circuit 4 are higher than the forward voltage of the diode 5. A current flows through it, and as a result, the output of the smoothing circuit 4, that is, the control voltage Vcont, rises almost simultaneously with the rise of the holding voltage V2 of the peak hold circuit 2.

これにより増幅回路1の利得は安定状態に近づくと同時
に、平滑回路4のコンデンサC2への充電も速くなる。
As a result, the gain of the amplifier circuit 1 approaches a stable state, and at the same time, charging of the capacitor C2 of the smoothing circuit 4 becomes faster.

次に、この状態から比較回路3および平滑回路4の遅延
時間が経過すると、平滑回路4の出力電圧Vcontと
保持電圧V2の差がダイオード5の順方向電圧以下にな
り、ダイオード5には電流が流れなくなる。この後は従
来の回路動作と同様になる。
Next, when the delay time of the comparator circuit 3 and the smoothing circuit 4 elapses from this state, the difference between the output voltage Vcont of the smoothing circuit 4 and the holding voltage V2 becomes less than the forward voltage of the diode 5, and the current flows through the diode 5. It stops flowing. After this, the circuit operation is similar to that of the conventional circuit.

これらの作用により、この実施例による自動利得制御増
幅器の応答速度は従来のものに比べ高速になる。  −
Due to these effects, the response speed of the automatic gain control amplifier according to this embodiment is faster than that of the conventional one. −
.

なお、上記実施例ではダイオード5のカソードを平滑回
路4の出力に、アノードをピークホールド回路2の出力
に接続したものを示したが、増幅回路1の制御電圧と利
得の関係が上記実施例と逆の特性を持っている場合はカ
ソード、アノードの接続は逆となる。
In the above embodiment, the cathode of the diode 5 is connected to the output of the smoothing circuit 4, and the anode is connected to the output of the peak hold circuit 2. However, the relationship between the control voltage and the gain of the amplifier circuit 1 is different from the above embodiment. If they have opposite characteristics, the cathode and anode connections will be reversed.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、増幅回路の制御端
子と比較回路の入力端子間に、一定の順方向電圧で導通
ずる整流素子を接続し、上記各端子間の電圧差を一定値
以内に保つようにしたことにより、遅延時間を補償する
ことができるので、応答時間が短く、入力信号振幅の変
動に伴う使用不能期間を少なくすることができる自動利
得制御増幅器が得られるという効果がある。
As explained above, according to the present invention, a rectifying element that conducts at a constant forward voltage is connected between the control terminal of the amplifier circuit and the input terminal of the comparison circuit, and the voltage difference between the terminals is kept within a constant value. Since delay time can be compensated for by keeping the gain constant at .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例を示すブロック図、第2図
は上記実施例における各信号波形図、第3図は従来例を
示すブロック図、第4図は上記実施例の各信号波形図で
ある。 1・・・増幅回路、la・・・制御端子、3・・・比較
回路、3a・・・入力端子、5・・・整流素子。 なお、図中間−又は相当部分には同一符号を用いている
。 代理人  大  岩  増  雄(ばか2名)第1m!
       第3図 Vin 4 t    Vin      。
Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a diagram of each signal waveform in the above embodiment, Fig. 3 is a block diagram showing a conventional example, and Fig. 4 is a diagram of each signal waveform of the above embodiment. It is a diagram. DESCRIPTION OF SYMBOLS 1... Amplification circuit, la... Control terminal, 3... Comparison circuit, 3a... Input terminal, 5... Rectifying element. Note that the same reference numerals are used for the middle part of the figure or corresponding parts. Agent Masuo Oiwa (2 idiots) 1st meter!
FIG. 3 Vin 4 t Vin.

Claims (1)

【特許請求の範囲】[Claims] 増幅利得が制御可能な増幅回路と、予め設定された基準
電圧と上記増幅回路の出力信号に対応する電圧とを比較
する比較回路とを備え、上記比較回路の出力にもとづき
上記増幅回路の利得を制御するようにした自動利得制御
増幅器において、上記増幅回路の制御端子と上記比較回
路の入力端子間に、一定の順方向電圧で導通する整流素
子を接続し、上記各端子間の電圧差を一定値以内に保つ
ようにしたことを特徴とする自動利得制御増幅器。
The amplifier circuit includes an amplifier circuit whose amplification gain can be controlled, and a comparison circuit that compares a preset reference voltage with a voltage corresponding to the output signal of the amplifier circuit, and calculates the gain of the amplifier circuit based on the output of the comparison circuit. In the automatic gain control amplifier, a rectifying element that conducts at a constant forward voltage is connected between the control terminal of the amplifier circuit and the input terminal of the comparison circuit, and the voltage difference between the terminals is kept constant. An automatic gain control amplifier characterized in that the gain is maintained within a certain value.
JP2769285A 1985-02-15 1985-02-15 Automatic gain control amplifier Pending JPS61189008A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2769285A JPS61189008A (en) 1985-02-15 1985-02-15 Automatic gain control amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2769285A JPS61189008A (en) 1985-02-15 1985-02-15 Automatic gain control amplifier

Publications (1)

Publication Number Publication Date
JPS61189008A true JPS61189008A (en) 1986-08-22

Family

ID=12228015

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2769285A Pending JPS61189008A (en) 1985-02-15 1985-02-15 Automatic gain control amplifier

Country Status (1)

Country Link
JP (1) JPS61189008A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01175018U (en) * 1988-05-31 1989-12-13

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01175018U (en) * 1988-05-31 1989-12-13

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